From a726318c6081bfc80361a7da1ffb8bf92cf2844b Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Thu, 27 Feb 2014 19:31:42 +0100 Subject: [PATCH] re-connected GbE to clock... --- cts/config_default.vhd | 2 +- cts/trb3_central.prj | 12 +- cts/trb3_central.vhd | 3 +- cts/trb3_central_constraints.lpf | 247 ++++++++++++++++--------------- 4 files changed, 139 insertions(+), 125 deletions(-) diff --git a/cts/config_default.vhd b/cts/config_default.vhd index daf5769..2c371db 100644 --- a/cts/config_default.vhd +++ b/cts/config_default.vhd @@ -22,7 +22,7 @@ package config is --Which external trigger module (ETM) to use? type ETM_CHOICE_type is (ETM_CHOICE_MBS_VULOM, ETM_CHOICE_MAINZ_A2); - constant ETM_CHOICE : ETM_CHOICE_type := ETM_CHOICE_MBS_VULOM; + constant ETM_CHOICE : ETM_CHOICE_type := ETM_CHOICE_MAINZ_A2; ------------------------------------------------------------------------------ --End of configuration diff --git a/cts/trb3_central.prj b/cts/trb3_central.prj index 805f14e..43fb895 100644 --- a/cts/trb3_central.prj +++ b/cts/trb3_central.prj @@ -98,8 +98,12 @@ add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_frame_constr.vhd" #add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_packet_constr_nologic.vhd" add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_packet_constr.vhd" #add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_packet_constr_simple_sender.vhd" + + +#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_ipu2gbe_simple_sender.vhd" add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_ipu2gbe.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_ipu2gbe_nologic.vhd" + + add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ip_configurator.vhd" add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_buf.vhd" add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_setup.vhd" @@ -108,10 +112,7 @@ add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/mb_mac_sim.vhd" add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/slv_mac_memory.vhd" #add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/slv_register.vhd" add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/ip_mem.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/serdes/serdes_gbe_0_extclock_8b.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b_ecp3.vhd" add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/serdes_gbe_0ch.vhd" add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/mac_init_mem.vhd" @@ -126,7 +127,6 @@ add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_512x32.vhd" add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_2048x8x16.vhd" add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_65536x18x9.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_1024x16x8.vhd" add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb.vhd" add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/debug_fifo_2kx16.vhd" @@ -145,9 +145,9 @@ add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_construc add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_4kx18x9.vhd" add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_4kx8_ecp3.vhd" add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_512x32x8.vhd" +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_32kx9_flags.vhd" add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_ipu_interface.vhd" add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_event_constr.vhd" -add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_32kx9_flags.vhd" #trbnet and base files diff --git a/cts/trb3_central.vhd b/cts/trb3_central.vhd index 2a89882..393a6c3 100755 --- a/cts/trb3_central.vhd +++ b/cts/trb3_central.vhd @@ -634,7 +634,8 @@ THE_MAIN_PLL : pll_in200_out100 OSCInst0 : OSCF -- internal oscillator with frequency of 2.5MHz port map ( OSC => osc_int); - + +clk_125_i <= CLK_GPLL_RIGHT; --------------------------------------------------------------------------- -- The TrbNet media interface (SFP) diff --git a/cts/trb3_central_constraints.lpf b/cts/trb3_central_constraints.lpf index ce437e2..b053e22 100644 --- a/cts/trb3_central_constraints.lpf +++ b/cts/trb3_central_constraints.lpf @@ -117,39 +117,41 @@ LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_4_gen_iobufs_3_gen_iobuf_IOBUF/genINITOB #GbE Part -FREQUENCY NET "GBE/serdes_clk_125" 125.000000 MHz ; -FREQUENCY NET "GBE/CLK_125_OUT_inferred_clock" 125.00 MHz ; -FREQUENCY NET "GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/clk_int_SERDES_GBE/ff_txfullclk" 125.000000 MHz ; -FREQUENCY NET "GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/clk_int_SERDES_GBE/ff_rxfullclk" 125.000000 MHz ; +#GbE Part + +FREQUENCY NET "gen_ethernet_hub_GBE/serdes_clk_125" 125.000000 MHz ; +FREQUENCY NET "gen_ethernet_hub_GBE/CLK_125_OUT_inferred_clock" 125.00 MHz ; +FREQUENCY NET "gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/clk_int_SERDES_GBE/ff_txfullclk" 125.000000 MHz ; +FREQUENCY NET "gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/clk_int_SERDES_GBE/ff_rxfullclk" 125.000000 MHz ; -FREQUENCY NET "GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/sd_tx_clock" 125.000000 MHz ; -FREQUENCY NET "GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/sd_rx_clock" 125.000000 MHz ; -FREQUENCY NET "GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/refclkcore" 125.000000 MHz ; +FREQUENCY NET "gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/sd_tx_clock" 125.000000 MHz ; +FREQUENCY NET "gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/sd_rx_clock" 125.000000 MHz ; +FREQUENCY NET "gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/refclkcore" 125.000000 MHz ; -FREQUENCY NET "GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/CLK_RX_OUT" 125.000000 MHz ; -FREQUENCY NET "GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/clk_int_SERDES_GBE/CLK_TX_OUT_inferred_clock" 125.000000 MHz ; +FREQUENCY NET "gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/CLK_RX_OUT" 125.000000 MHz ; +FREQUENCY NET "gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/clk_int_SERDES_GBE/CLK_TX_OUT_inferred_clock" 125.000000 MHz ; -FREQUENCY PORT "GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/clk_int_SERDES_GBE/PCSC_INST.FF_TX_F_CLK" 125.000000 MHz; -FREQUENCY PORT "GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/clk_int_SERDES_GBE/PCSC_INST.FF_RX_F_CLK" 125.000000 MHz; +FREQUENCY PORT "gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/clk_int_SERDES_GBE/PCSC_INST.FF_TX_F_CLK" 125.000000 MHz; +FREQUENCY PORT "gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/clk_int_SERDES_GBE/PCSC_INST.FF_RX_F_CLK" 125.000000 MHz; UGROUP "tsmac" - BLKNAME GBE/imp_gen_MAC - BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES - BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SGMII_GBE_PCS - BLKNAME GBE/FRAME_RECEIVER - BLKNAME GBE/FRAME_TRANSMITTER; + BLKNAME gen_ethernet_hub_GBE/imp_gen_MAC + BLKNAME gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES + BLKNAME gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SGMII_GBE_PCS + BLKNAME gen_ethernet_hub_GBE/FRAME_RECEIVER + BLKNAME gen_ethernet_hub_GBE/FRAME_TRANSMITTER; UGROUP "controllers" - BLKNAME GBE/MAIN_CONTROL - BLKNAME GBE/RECEIVE_CONTROLLER - BLKNAME GBE/TRANSMIT_CONTROLLER; + BLKNAME gen_ethernet_hub_GBE/MAIN_CONTROL + BLKNAME gen_ethernet_hub_GBE/RECEIVE_CONTROLLER + BLKNAME gen_ethernet_hub_GBE/TRANSMIT_CONTROLLER; UGROUP "gbe_rx_tx" - BLKNAME GBE/FRAME_CONSTRUCTOR - BLKNAME GBE/MAIN_CONTROL/protocol_selector/TrbNetData/MB_IP_CONFIG - BLKNAME GBE/MAIN_CONTROL/protocol_selector/TrbNetData/THE_IP_CONFIGURATOR -# BLKNAME GBE/MAIN_CONTROL/protocol_selector/TrbNetData/PACKET_CONSTRUCTOR -# BLKNAME GBE/MAIN_CONTROL/protocol_selector/TrbNetData/THE_IPU_INTERFACE - BLKNAME GBE/setup_imp_gen_SETUP; + BLKNAME gen_ethernet_hub_GBE/FRAME_CONSTRUCTOR + BLKNAME gen_ethernet_hub_GBE/MB_IP_CONFIG + BLKNAME gen_ethernet_hub_GBE/THE_IP_CONFIGURATOR +# BLKNAME gen_ethernet_hub_GBE/PACKET_CONSTRUCTOR + #BLKNAME gen_ethernet_hub_GBE/THE_IPU_INTERFACE + BLKNAME gen_ethernet_hub_GBE/setup_imp_gen_SETUP; #REGION "GBE_REGION" "R20C65D" 36 42 DEVSIZE; @@ -158,106 +160,117 @@ UGROUP "gbe_rx_tx" FREQUENCY NET "GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/un1_PCS_SERDES_1" 125.000000 MHz ; FREQUENCY NET "GBE/serdes_clk_125_c" 125.000000 MHz ; #REGION "GBE_MAIN_REGION" "R50C64C" 65 64 DEVSIZE; + #LOCATE UGROUP "controllers" REGION "GBE_MAIN_REGION" ; +#LOCATE UGROUP "gbe_rx_tx" REGION "GBE_MAIN_REGION" ; + + + +REGION "MED0" "R69C4D" 35 40 DEVSIZE; +FREQUENCY NET "gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/un1_PCS_SERDES_1" 125.000000 MHz ; +FREQUENCY NET "gen_ethernet_hub_GBE/serdes_clk_125_c" 125.000000 MHz ; #LOCATE UGROUP "tsmac" REGION "MED0" ; BLOCK JTAGPATHS ; UGROUP "sd_tx_to_pcs" - BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_TX_PROC_sd_tx_correct_disp_q - BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q_0 - BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q_1 - BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q_2 - BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q_3 - BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q_4 - BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q_5 - BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q_6 - BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q_7 - BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_TX_PROC_sd_tx_kcntl_q; + BLKNAME gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_TX_PROC_sd_tx_correct_disp_q + BLKNAME gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q_0 + BLKNAME gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q_1 + BLKNAME gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q_2 + BLKNAME gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q_3 + BLKNAME gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q_4 + BLKNAME gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q_5 + BLKNAME gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q_6 + BLKNAME gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q_7 + BLKNAME gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_TX_PROC_sd_tx_kcntl_q; UGROUP "sd_rx_to_pcs" - BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_cv_error_q - BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q_0 - BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q_1 - BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q_2 - BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q_3 - BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q_4 - BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q_5 - BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q_6 - BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q_7 - BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_disp_error_q - BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_kcntl_q; + BLKNAME gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_cv_error_q + BLKNAME gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q_0 + BLKNAME gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q_1 + BLKNAME gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q_2 + BLKNAME gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q_3 + BLKNAME gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q_4 + BLKNAME gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q_5 + BLKNAME gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q_6 + BLKNAME gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q_7 + BLKNAME gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_disp_error_q + BLKNAME gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_kcntl_q; UGROUP "pcs_tx_to_mac" - BLKNAME GBE/pcs_tx_en_q - BLKNAME GBE/pcs_tx_en_qq - BLKNAME GBE/pcs_tx_er_q - BLKNAME GBE/pcs_tx_er_qq - BLKNAME GBE/pcs_txd_q_0 - BLKNAME GBE/pcs_txd_q_1 - BLKNAME GBE/pcs_txd_q_2 - BLKNAME GBE/pcs_txd_q_3 - BLKNAME GBE/pcs_txd_q_4 - BLKNAME GBE/pcs_txd_q_5 - BLKNAME GBE/pcs_txd_q_6 - BLKNAME GBE/pcs_txd_q_7 - BLKNAME GBE/pcs_txd_qq_0 - BLKNAME GBE/pcs_txd_qq_1 - BLKNAME GBE/pcs_txd_qq_2 - BLKNAME GBE/pcs_txd_qq_3 - BLKNAME GBE/pcs_txd_qq_4 - BLKNAME GBE/pcs_txd_qq_5 - BLKNAME GBE/pcs_txd_qq_6 - BLKNAME GBE/pcs_txd_qq_7; + BLKNAME gen_ethernet_hub_GBE/pcs_tx_en_q + BLKNAME gen_ethernet_hub_GBE/pcs_tx_en_qq + BLKNAME gen_ethernet_hub_GBE/pcs_tx_er_q + BLKNAME gen_ethernet_hub_GBE/pcs_tx_er_qq + BLKNAME gen_ethernet_hub_GBE/pcs_txd_q_0 + BLKNAME gen_ethernet_hub_GBE/pcs_txd_q_1 + BLKNAME gen_ethernet_hub_GBE/pcs_txd_q_2 + BLKNAME gen_ethernet_hub_GBE/pcs_txd_q_3 + BLKNAME gen_ethernet_hub_GBE/pcs_txd_q_4 + BLKNAME gen_ethernet_hub_GBE/pcs_txd_q_5 + BLKNAME gen_ethernet_hub_GBE/pcs_txd_q_6 + BLKNAME gen_ethernet_hub_GBE/pcs_txd_q_7 + BLKNAME gen_ethernet_hub_GBE/pcs_txd_qq_0 + BLKNAME gen_ethernet_hub_GBE/pcs_txd_qq_1 + BLKNAME gen_ethernet_hub_GBE/pcs_txd_qq_2 + BLKNAME gen_ethernet_hub_GBE/pcs_txd_qq_3 + BLKNAME gen_ethernet_hub_GBE/pcs_txd_qq_4 + BLKNAME gen_ethernet_hub_GBE/pcs_txd_qq_5 + BLKNAME gen_ethernet_hub_GBE/pcs_txd_qq_6 + BLKNAME gen_ethernet_hub_GBE/pcs_txd_qq_7; UGROUP "pcs_rx_to_mac" - BLKNAME GBE/pcs_rx_en_q - BLKNAME GBE/pcs_rx_en_qq - BLKNAME GBE/pcs_rx_er_q - BLKNAME GBE/pcs_rx_er_qq - BLKNAME GBE/pcs_rxd_q_0 - BLKNAME GBE/pcs_rxd_q_1 - BLKNAME GBE/pcs_rxd_q_2 - BLKNAME GBE/pcs_rxd_q_3 - BLKNAME GBE/pcs_rxd_q_4 - BLKNAME GBE/pcs_rxd_q_5 - BLKNAME GBE/pcs_rxd_q_6 - BLKNAME GBE/pcs_rxd_q_7 - BLKNAME GBE/pcs_rxd_qq_0 - BLKNAME GBE/pcs_rxd_qq_1 - BLKNAME GBE/pcs_rxd_qq_2 - BLKNAME GBE/pcs_rxd_qq_3 - BLKNAME GBE/pcs_rxd_qq_4 - BLKNAME GBE/pcs_rxd_qq_5 - BLKNAME GBE/pcs_rxd_qq_6 - BLKNAME GBE/pcs_rxd_qq_7; + BLKNAME gen_ethernet_hub_GBE/pcs_rx_en_q + BLKNAME gen_ethernet_hub_GBE/pcs_rx_en_qq + BLKNAME gen_ethernet_hub_GBE/pcs_rx_er_q + BLKNAME gen_ethernet_hub_GBE/pcs_rx_er_qq + BLKNAME gen_ethernet_hub_GBE/pcs_rxd_q_0 + BLKNAME gen_ethernet_hub_GBE/pcs_rxd_q_1 + BLKNAME gen_ethernet_hub_GBE/pcs_rxd_q_2 + BLKNAME gen_ethernet_hub_GBE/pcs_rxd_q_3 + BLKNAME gen_ethernet_hub_GBE/pcs_rxd_q_4 + BLKNAME gen_ethernet_hub_GBE/pcs_rxd_q_5 + BLKNAME gen_ethernet_hub_GBE/pcs_rxd_q_6 + BLKNAME gen_ethernet_hub_GBE/pcs_rxd_q_7 + BLKNAME gen_ethernet_hub_GBE/pcs_rxd_qq_0 + BLKNAME gen_ethernet_hub_GBE/pcs_rxd_qq_1 + BLKNAME gen_ethernet_hub_GBE/pcs_rxd_qq_2 + BLKNAME gen_ethernet_hub_GBE/pcs_rxd_qq_3 + BLKNAME gen_ethernet_hub_GBE/pcs_rxd_qq_4 + BLKNAME gen_ethernet_hub_GBE/pcs_rxd_qq_5 + BLKNAME gen_ethernet_hub_GBE/pcs_rxd_qq_6 + BLKNAME gen_ethernet_hub_GBE/pcs_rxd_qq_7; USE PRIMARY NET "CLK_GPLL_RIGHT_c" ; -FREQUENCY NET "GBE/serdes_rx_clk_c" 125.000000 MHz PAR_ADJ 25.000000 ; -FREQUENCY NET "GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/clk_int_SERDES_GBE/FF_TX_F_CLK_0" 125.000000 MHz PAR_ADJ 25.000000 ; -FREQUENCY NET "GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/clk_int_SERDES_GBE/FF_TX_F_CLK_1" 125.000000 MHz PAR_ADJ 25.000000 ; -FREQUENCY NET "GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/clk_int_SERDES_GBE/FF_TX_F_CLK_2" 125.000000 MHz PAR_ADJ 25.000000 ; -FREQUENCY NET "GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/clk_int_SERDES_GBE/FF_TX_F_CLK_3" 125.000000 MHz PAR_ADJ 25.000000 ; +FREQUENCY NET "gen_ethernet_hub_GBE/serdes_rx_clk_c" 125.000000 MHz PAR_ADJ 25.000000 ; +FREQUENCY NET "gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/clk_int_SERDES_GBE/FF_TX_F_CLK_0" 125.000000 MHz PAR_ADJ 25.000000 ; +FREQUENCY NET "gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/clk_int_SERDES_GBE/FF_TX_F_CLK_1" 125.000000 MHz PAR_ADJ 25.000000 ; +FREQUENCY NET "gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/clk_int_SERDES_GBE/FF_TX_F_CLK_2" 125.000000 MHz PAR_ADJ 25.000000 ; +FREQUENCY NET "gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/clk_int_SERDES_GBE/FF_TX_F_CLK_3" 125.000000 MHz PAR_ADJ 25.000000 ; + +MAXDELAY NET "gen_ethernet_hub_GBE/pcs_rx_en_q" 1.5 ns; +MAXDELAY NET "gen_ethernet_hub_GBE/pcs_rx_er_q" 1.5 ns; +MAXDELAY NET "gen_ethernet_hub_GBE/pcs_rxd_q_0" 1.5 ns; +MAXDELAY NET "gen_ethernet_hub_GBE/pcs_rxd_q_1" 1.5 ns; +MAXDELAY NET "gen_ethernet_hub_GBE/pcs_rxd_q_2" 1.5 ns; +MAXDELAY NET "gen_ethernet_hub_GBE/pcs_rxd_q_3" 1.5 ns; +MAXDELAY NET "gen_ethernet_hub_GBE/pcs_rxd_q_4" 1.5 ns; +MAXDELAY NET "gen_ethernet_hub_GBE/pcs_rxd_q_5" 1.5 ns; +MAXDELAY NET "gen_ethernet_hub_GBE/pcs_rxd_q_6" 1.5 ns; +MAXDELAY NET "gen_ethernet_hub_GBE/pcs_rxd_q_7" 1.5 ns; -MAXDELAY NET "GBE/pcs_rx_en_q" 1.5 ns; -MAXDELAY NET "GBE/pcs_rx_er_q" 1.5 ns; -MAXDELAY NET "GBE/pcs_rxd_q_0" 1.5 ns; -MAXDELAY NET "GBE/pcs_rxd_q_1" 1.5 ns; -MAXDELAY NET "GBE/pcs_rxd_q_2" 1.5 ns; -MAXDELAY NET "GBE/pcs_rxd_q_3" 1.5 ns; -MAXDELAY NET "GBE/pcs_rxd_q_4" 1.5 ns; -MAXDELAY NET "GBE/pcs_rxd_q_5" 1.5 ns; -MAXDELAY NET "GBE/pcs_rxd_q_6" 1.5 ns; -MAXDELAY NET "GBE/pcs_rxd_q_7" 1.5 ns; +DEFINE PORT GROUP "RX_GRP" "gen_ethernet_hub_GBE/pcs_rx_en_q" + "gen_ethernet_hub_GBE/pcs_rx_er_q" + "gen_ethernet_hub_GBE/pcs_rxd_q_*"; +INPUT_SETUP GROUP "RX_GRP" 3.500000 ns HOLD 0.000000 ns CLKPORT "gen_ethernet_hub_GBE/serdes_rx_clk_c" ; -DEFINE PORT GROUP "RX_GRP" "GBE/pcs_rx_en_q" - "GBE/pcs_rx_er_q" - "GBE/pcs_rxd_q_*"; -INPUT_SETUP GROUP "GBE/RX_GRP" 3.500000 ns HOLD 0.000000 ns CLKPORT "GBE/serdes_rx_clk_c" ; +PRIORITIZE NET "gen_ethernet_hub_GBE/pcs_rx_en_q" 100; +PRIORITIZE NET "gen_ethernet_hub_GBE/pcs_rx_er_q" 100; +PRIORITIZE NET "gen_ethernet_hub_GBE/pcs_rxd_q_0" 100; +PRIORITIZE NET "gen_ethernet_hub_GBE/pcs_rxd_q_1" 100; +PRIORITIZE NET "gen_ethernet_hub_GBE/pcs_rxd_q_2" 100; +PRIORITIZE NET "gen_ethernet_hub_GBE/pcs_rxd_q_3" 100; +PRIORITIZE NET "gen_ethernet_hub_GBE/pcs_rxd_q_4" 100; +PRIORITIZE NET "gen_ethernet_hub_GBE/pcs_rxd_q_5" 100; +PRIORITIZE NET "gen_ethernet_hub_GBE/pcs_rxd_q_6" 100; +PRIORITIZE NET "gen_ethernet_hub_GBE/pcs_rxd_q_7" 100; +PRIORITIZE NET "gen_ethernet_hub_GBE/pcs_rxd_q_0" 100; +PRIORITIZE NET "gen_ethernet_hub_GBE/serdes_rx_clk_c" 80; -PRIORITIZE NET "GBE/pcs_rx_en_q" 100; -PRIORITIZE NET "GBE/pcs_rx_er_q" 100; -PRIORITIZE NET "GBE/pcs_rxd_q_0" 100; -PRIORITIZE NET "GBE/pcs_rxd_q_1" 100; -PRIORITIZE NET "GBE/pcs_rxd_q_2" 100; -PRIORITIZE NET "GBE/pcs_rxd_q_3" 100; -PRIORITIZE NET "GBE/pcs_rxd_q_4" 100; -PRIORITIZE NET "GBE/pcs_rxd_q_5" 100; -PRIORITIZE NET "GBE/pcs_rxd_q_6" 100; -PRIORITIZE NET "GBE/pcs_rxd_q_7" 100; -PRIORITIZE NET "GBE/pcs_rxd_q_0" 100; -PRIORITIZE NET "GBE/serdes_rx_clk_c" 80; +BLOCK PATH FROM CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_cpu_if*" TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_tx_mac*" ; +BLOCK PATH FROM CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_cpu_if*" TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_rx_mac*" ; -- 2.43.0