From a7c39e6967f13d4ca28f3021f65687e8dd475835 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Fri, 14 Sep 2012 09:17:03 +0000 Subject: [PATCH] *** empty log message *** --- wasa/panda_dirc_wasa.vhd | 21 ++++++++++++++++----- wasa/sim/machxo.mpf | 4 ++-- wasa/trb3_periph_padiwa.vhd | 32 ++++++++++---------------------- 3 files changed, 28 insertions(+), 29 deletions(-) diff --git a/wasa/panda_dirc_wasa.vhd b/wasa/panda_dirc_wasa.vhd index ad8f0bb..c431f7c 100644 --- a/wasa/panda_dirc_wasa.vhd +++ b/wasa/panda_dirc_wasa.vhd @@ -190,7 +190,8 @@ signal flash_go : std_logic; signal flash_busy : std_logic; signal flash_err : std_logic; -signal inp_select : integer range 0 to 15 := 0; +signal inp_select : integer range 0 to 31 := 0; +signal inp_invert : std_logic_vector(15 downto 0); signal input_enable : std_logic_vector(15 downto 0); signal inp_status : std_logic_vector(15 downto 0); signal led_status : std_logic_vector(4 downto 0); @@ -391,7 +392,8 @@ THE_IO_REG_READ : process begin when x"0" => spi_reg20_i <= input_enable; when x"1" => spi_reg20_i <= inp_status; when x"2" => spi_reg20_i <= x"00" & "000" & led_status(4) & leds; - when x"3" => spi_reg20_i <= x"000" & std_logic_vector(to_unsigned(inp_select,4)); + when x"3" => spi_reg20_i <= x"00" & "000" & std_logic_vector(to_unsigned(inp_select,5)); + when x"4" => spi_reg20_i <= inp_invert; when others => null; end case; else @@ -410,7 +412,8 @@ THE_IO_REG_WRITE : process begin when x"0" => input_enable <= spi_data_i; when x"1" => null; when x"2" => led_status <= spi_data_i(4 downto 0); - when x"3" => inp_select <= to_integer(unsigned(spi_data_i(3 downto 0))); + when x"3" => inp_select <= to_integer(unsigned(spi_data_i(4 downto 0))); + when x"4" => inp_invert <= spi_data_i; when others => null; end case; end if; @@ -435,14 +438,22 @@ end process; --------------------------------------------------------------------------- -- Rest of the I/O --------------------------------------------------------------------------- -CON <= INP and not input_enable; +CON <= (INP xor inp_invert) and not input_enable; SPARE_LINE(0) <= '0'; --clk_26; SPARE_LINE(1) <= '0'; --clk_i; SPARE_LINE(2) <= '0'; --timer(18); SPARE_LINE(3) <= '0'; -SPARE_LVDS <= INP(inp_select+1); + +SPARE_OUTPUT : process(INP, inp_select, input_enable) + begin + if inp_select < 16 then + SPARE_LVDS <= INP(inp_select+1); + else + SPARE_LVDS <= or_all(INP and not input_enable); + end if; + end process; -- TEST_LINE(0) <= '0'; -- TEST_LINE(15 downto 1) <= (others => '0'); diff --git a/wasa/sim/machxo.mpf b/wasa/sim/machxo.mpf index ac15a64..7b8bc7d 100644 --- a/wasa/sim/machxo.mpf +++ b/wasa/sim/machxo.mpf @@ -1657,11 +1657,11 @@ Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 v Project_File_4 = /d/jspc22/trb/cvs/trb3/wasa/source/spi_slave.vhd Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1346854393 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 5 dont_compile 0 cover_nosub 0 vhdl_use93 2002 Project_File_5 = /d/jspc22/trb/cvs/trb3/wasa/version.vhd -Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1346921672 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 1 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1346921672 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 1 dont_compile 0 cover_nosub 0 vhdl_use93 2002 Project_File_6 = /d/jspc22/trb/cvs/trb3/base/trb3_components.vhd Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1346765030 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 9 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_7 = /d/jspc22/trb/cvs/trb3/wasa/panda_dirc_wasa.vhd -Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1346921711 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 0 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1346921711 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 1 cover_noshort 0 compile_to work compile_order 0 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_8 = /d/jspc22/trb/cvs/trbnet/trb_net_std.vhd Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1346849814 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 10 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_9 = /d/jspc22/trb/cvs/trb3/wasa/source/tb/pwm_tb.vhd diff --git a/wasa/trb3_periph_padiwa.vhd b/wasa/trb3_periph_padiwa.vhd index 97faf85..6127fbb 100644 --- a/wasa/trb3_periph_padiwa.vhd +++ b/wasa/trb3_periph_padiwa.vhd @@ -28,9 +28,6 @@ entity trb3_periph_padiwa is CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 0, not used SERDES_TX : out std_logic_vector(3 downto 2); SERDES_RX : in std_logic_vector(3 downto 2); - SFP_TXDIS : out std_logic; - SFP_MOD : inout std_logic_vector(2 downto 0); - SFP_LOS : in std_logic; FPGA5_COMM : inout std_logic_vector(11 downto 0); --Bit 0/1 input, serial link RX active @@ -39,7 +36,7 @@ entity trb3_periph_padiwa is --Connections SPARE_LINE : inout std_logic_vector( 3 downto 0); - INP : in std_logic_vector(64 downto 1); + INP : in std_logic_vector(63 downto 0); --Flash ROM & Reboot FLASH_CLK : out std_logic; @@ -49,10 +46,10 @@ entity trb3_periph_padiwa is PROGRAMN : out std_logic; --reboot FPGA --DAC - OUT_SDO : out std_logic_vector(3 downto 0); - IN_SDI : in std_logic_vector(3 downto 0); - OUT_SCK : out std_logic_vector(3 downto 0); - OUT_CS : out std_logic_vector(3 downto 0); + OUT_SDO : out std_logic_vector(4 downto 1); + IN_SDI : in std_logic_vector(4 downto 1); + OUT_SCK : out std_logic_vector(4 downto 1); + OUT_CS : out std_logic_vector(4 downto 1); --Misc TEMPSENS : inout std_logic; --Temperature Sensor CODE_LINE : in std_logic_vector(1 downto 0); @@ -208,11 +205,8 @@ architecture trb3_periph_padiwa_arch of trb3_periph_padiwa is signal padiwa_sdi : std_logic; signal padiwa_sdo : std_logic; - --FPGA Test - signal time_counter : unsigned(31 downto 0); - --TDC - signal hit_in_i : std_logic_vector(64 downto 1); + signal hit_in_i : std_logic_vector(63 downto 0); --TDC component component TDC @@ -412,7 +406,8 @@ begin REGIO_CTRL_REG_OUT => ctrl_reg, --start 0xc0 REGIO_STAT_STROBE_OUT => stat_reg_strobe, REGIO_CTRL_STROBE_OUT => ctrl_reg_strobe, - REGIO_VAR_ENDPOINT_ID => (others => '0'), + REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE, + REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'), BUS_ADDR_OUT => regio_addr_out, BUS_READ_ENABLE_OUT => regio_read_enable_out, @@ -619,14 +614,7 @@ padiwa_sdi <= or_all(IN_SDI and not padiwa_cs(3 downto 0)); -- TEST_LINE(15 downto 0) <= (others => '0'); ---------------------------------------------------------------------------- --- Test Circuits ---------------------------------------------------------------------------- - process - begin - wait until rising_edge(clk_100_i); - time_counter <= time_counter + 1; - end process; + ------------------------------------------------------------------------------- -- TDC @@ -641,7 +629,7 @@ padiwa_sdi <= or_all(IN_SDI and not padiwa_cs(3 downto 0)); CLK_TDC => CLK_PCLK_LEFT, -- Clock used for the time measurement CLK_READOUT => clk_100_i, -- Clock for the readout REFERENCE_TIME => timing_trg_received_i, -- Reference time input - HIT_IN => hit_in_i(16 downto 1), -- Channel start signals + HIT_IN => hit_in_i(15 downto 0), -- Channel start signals TRG_WIN_PRE => ctrl_reg(42 downto 32), -- Pre-Trigger window width TRG_WIN_POST => ctrl_reg(58 downto 48), -- Post-Trigger window width -- -- 2.43.0