From a954e2e24a83aa2474838dd860eb2ae6467e9c8b Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Mon, 4 Jul 2022 18:21:06 +0200 Subject: [PATCH] base vewrsion --- gbe_hub/trb3sc_gbe_hub.lpf | 2 +- gbe_hub/trb3sc_gbe_hub.vhd | 150 ++----------------------------------- 2 files changed, 6 insertions(+), 146 deletions(-) diff --git a/gbe_hub/trb3sc_gbe_hub.lpf b/gbe_hub/trb3sc_gbe_hub.lpf index e9316a9..36c1877 100644 --- a/gbe_hub/trb3sc_gbe_hub.lpf +++ b/gbe_hub/trb3sc_gbe_hub.lpf @@ -1,7 +1,7 @@ # locate the PCS blocks LOCATE COMP "GBE/physical_impl_gen.physical/impl_gen.gbe_serdes/PCSD_INST" SITE "PCSD"; -LOCATE COMP "GBE/physical/gbe_serdes/PCSD_INST" SITE "PCSC"; +#LOCATE COMP "GBE/physical/gbe_serdes/PCSD_INST" SITE "PCSC"; FREQUENCY NET "CLK_CORE_PCLK_c" 200.0 MHz; FREQUENCY NET "CLK_SUPPL_PCLK_c" 125.0 MHz; diff --git a/gbe_hub/trb3sc_gbe_hub.vhd b/gbe_hub/trb3sc_gbe_hub.vhd index 88fa8e5..cd3897e 100644 --- a/gbe_hub/trb3sc_gbe_hub.vhd +++ b/gbe_hub/trb3sc_gbe_hub.vhd @@ -118,68 +118,6 @@ architecture trb3sc_arch of trb3sc_gbe_hub is signal gsc_busy : std_logic; signal status : std_logic_vector(15 downto 0); - - ---------------------------------------------------------------- --- signal tx_pll_lol_i : std_logic; --- signal tx_clk_avail_i : std_logic; --- signal tx_pcs_rst_i : std_logic; --- signal sync_tx_quad_i : std_logic; --- signal link_tx_ready_i : std_logic; --- signal link_rx_ready_i : std_logic_vector(3 downto 0); --- signal status_raw : std_logic_vector(31 downto 0); - - --- component gbe_med_raw is --- generic( --- LINKS_ACTIVE : std_logic_vector(3 downto 0) := "1111" --- ); --- port( --- RESET : in std_logic; --- GSR_N : in std_logic; --- CLK_SYS : in std_logic; --- CLK_125 : in std_logic; --- CLK_125_RX : out std_logic_vector(3 downto 0); --- -- MAC status and config --- MAC_READY_CONF_OUT : out std_logic_vector(3 downto 0); --- MAC_RECONF_IN : in std_logic_vector(3 downto 0) := (others => '0'); --- MAC_AN_READY_OUT : out std_logic_vector(3 downto 0); --- -- MAC data interface --- MAC_FIFOAVAIL_IN : in std_logic_vector(3 downto 0) := (others => '0'); --- MAC_FIFOEOF_IN : in std_logic_vector(3 downto 0) := (others => '0'); --- MAC_FIFOEMPTY_IN : in std_logic_vector(3 downto 0) := (others => '0'); --- MAC_RX_FIFOFULL_IN : in std_logic_vector(3 downto 0) := (others => '0'); --- -- MAC TX interface --- MAC_TX_DATA_IN : in std_logic_vector(4 * 8 - 1 downto 0) := (others => '0'); --- MAC_TX_READ_OUT : out std_logic_vector(3 downto 0); --- MAC_TX_DISCRFRM_OUT : out std_logic_vector(3 downto 0); --- MAC_TX_STAT_EN_OUT : out std_logic_vector(3 downto 0); --- MAC_TX_STATS_OUT : out std_logic_vector(4 * 31 - 1 downto 0); --- MAC_TX_DONE_OUT : out std_logic_vector(3 downto 0); --- -- MAC RX interface --- MAC_RX_FIFO_ERR_OUT : out std_logic_vector(3 downto 0); --- MAC_RX_STATS_OUT : out std_logic_vector(4 * 32 - 1 downto 0); --- MAC_RX_DATA_OUT : out std_logic_vector(4 * 8 - 1 downto 0); --- MAC_RX_WRITE_OUT : out std_logic_vector(3 downto 0); --- MAC_RX_STAT_EN_OUT : out std_logic_vector(3 downto 0); --- MAC_RX_EOF_OUT : out std_logic_vector(3 downto 0); --- MAC_RX_ERROR_OUT : out std_logic_vector(3 downto 0); --- -- SFP Connection --- SD_PRSNT_N_IN : in std_logic_vector(3 downto 0) := (others => '0'); --- SD_LOS_IN : in std_logic_vector(3 downto 0) := (others => '0'); --- SD_TXDIS_OUT : out std_logic_vector(3 downto 0); --- -- SerDes control --- TX_PLOL_LOL_OUT : out std_logic; --- TX_PCS_RST_IN : in std_logic; --- RX_LINK_READY_OUT : out std_logic_vector(3 downto 0); --- TX_LINK_READY_IN : in std_logic; --- -- Debug --- STATUS_OUT : out std_logic_vector(4 + 8 - 1 downto 0); --- DEBUG_OUT : out std_logic_vector(63 downto 0) --- ); --- end component gbe_med_raw; - --- attribute syn_noprune : boolean; --- attribute syn_noprune of gbe_med_raw : component is true; begin @@ -226,7 +164,7 @@ THE_CLOCK_RESET : entity work.clock_reset_handler PCSSW_EQ <= x"0"; PCSSW_PE <= x"F"; -- PCSSW <= "11100100"; -- SFP2 on D1, Addon on B3 - PCSSW <= "01001110"; -- SFP2 on TX_LINK_READY_INB3, AddOn on D1 + PCSSW <= "01001110"; -- SFP2 on B3, AddOn on D1 --------------------------------------------------------------------------- -- PCSD as test point (SFP2) @@ -294,6 +232,8 @@ THE_CLOCK_RESET : entity work.clock_reset_handler DEBUG_OUT => open ); + SFP_TX_DIS(1) <= '1'; + ------------------------------------------------------------------------------- -- SCTRL endpoint for GbE standalone ------------------------------------------------------------------------------- @@ -421,12 +361,12 @@ THE_CLOCK_RESET : entity work.clock_reset_handler LED_YELLOW <= not status(5); --'0'; GEN_HUB_LEDS : for i in 0 to 6 generate - LED_HUB_LINKOK(i+1) <= not '1'; + LED_HUB_LINKOK(i+1) <= not '0'; LED_HUB_TX(i+1) <= not '0'; LED_HUB_RX(i+1) <= not '0'; end generate; - LED_HUB_LINKOK(8) <= not '1'; + LED_HUB_LINKOK(8) <= not '0'; LED_HUB_TX(8) <= not '0'; LED_HUB_RX(8) <= not '0'; LED_SFP_GREEN(0) <= not '0'; @@ -438,84 +378,4 @@ end generate; LED_WHITE(1) <= not additional_reg(31); --'0'; LED_WHITE(0) <= not status(8); --'0'; - ---------------------------------------------------------------------------- ---------------------------------------------------------------------------- --- THE_GBE_MED_RAW: gbe_med_raw --- generic map( --- LINKS_ACTIVE => "1111" --- ) --- port map( --- RESET => reset_i, --- GSR_N => GSR_N, --- CLK_SYS => clk_sys, --- CLK_125 => CLK_SUPPL_PCLK, --- CLK_125_RX => open, --- -- MAC status and config --- MAC_READY_CONF_OUT => open, --- MAC_RECONF_IN => (others => '0'), --- MAC_AN_READY_OUT => open, --- -- MAC data interface --- MAC_FIFOAVAIL_IN => (others => '0'), --- MAC_FIFOEOF_IN => (others => '0'), --- MAC_FIFOEMPTY_IN => (others => '0'), --- MAC_RX_FIFOFULL_IN => (others => '0'), --- -- MAC TX interface --- MAC_TX_DATA_IN => (others => '0'), --- MAC_TX_READ_OUT => open, --- MAC_TX_DISCRFRM_OUT => open, --- MAC_TX_STAT_EN_OUT => open, --- MAC_TX_STATS_OUT => open, --- MAC_TX_DONE_OUT => open, --- -- MAC RX interface --- MAC_RX_FIFO_ERR_OUT => open, --- MAC_RX_STATS_OUT => open, --- MAC_RX_DATA_OUT => open, --- MAC_RX_WRITE_OUT => open, --- MAC_RX_STAT_EN_OUT => open, --- MAC_RX_EOF_OUT => open, --- MAC_RX_ERROR_OUT => open, --- -- SFP Connection --- SD_PRSNT_N_IN => HUB_MOD0(4 downto 1), --(others => '0'), --- SD_LOS_IN => HUB_LOS(4 downto 1), --(others => '0'), --- SD_TXDIS_OUT => HUB_TXDIS(4 downto 1), --open, --- -- SerDes control --- TX_PLOL_LOL_OUT => tx_pll_lol_i, --- TX_PCS_RST_IN => tx_pcs_rst_i, --- RX_LINK_READY_OUT => link_rx_ready_i, --- TX_LINK_READY_IN => link_tx_ready_i, --- -- Debug --- STATUS_OUT => status_raw, --open, --- DEBUG_OUT => open --- ); - --- LED_HUB_LINKOK(1) <= not status_raw(0 * 8 + 2); --- LED_HUB_RX(1) <= not status_raw(0 * 8 + 1); --- LED_HUB_TX(1) <= not status_raw(0 * 8 + 0); - --- LED_HUB_LINKOK(2) <= not status_raw(1 * 8 + 2); --- LED_HUB_RX(2) <= not status_raw(1 * 8 + 1); --- LED_HUB_TX(2) <= not status_raw(1 * 8 + 0); - --- LED_HUB_LINKOK(3) <= not status_raw(2 * 8 + 2); --- LED_HUB_RX(3) <= not status_raw(2 * 8 + 1); --- LED_HUB_TX(3) <= not status_raw(2 * 8 + 0); - --- LED_HUB_LINKOK(4) <= not status_raw(3 * 8 + 2); --- LED_HUB_RX(4) <= not status_raw(3 * 8 + 1); --- LED_HUB_TX(4) <= not status_raw(3 * 8 + 0); - --- -- RSL for TX of SerDes, based on extRSL logic --- THE_MAIN_TX_RST: main_tx_reset_RS --- port map ( --- CLEAR => clear, --- CLK_REF => CLK_SUPPL_PCLK, --- TX_PLL_LOL_IN => tx_pll_lol_i, --- TX_CLOCK_AVAIL_IN => '1', -- not needed here --- TX_PCS_RST_CH_C_OUT => tx_pcs_rst_i, --- SYNC_TX_QUAD_OUT => open, --not needed here --- LINK_TX_READY_OUT => link_tx_ready_i, --- STATE_OUT => open --- ); - end architecture; -- 2.43.0