From a9cbe588d627e726f273846b5042cf694286267f Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Tue, 18 Jul 2017 18:42:29 +0200 Subject: [PATCH] Use raw clock rather than 200 MHz output from PLL --- code/clock_reset_handler.vhd | 8 ++++---- combiner/par.p2t | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/code/clock_reset_handler.vhd b/code/clock_reset_handler.vhd index 1c4f4cd..82c87d7 100644 --- a/code/clock_reset_handler.vhd +++ b/code/clock_reset_handler.vhd @@ -61,9 +61,9 @@ THE_PLL : entity work.pll_240_100 --PLL with 200 MHz input! ); gen_slow_clock : if USE_120_MHZ = 0 generate - RAW_CLK_OUT <= clock_200; + RAW_CLK_OUT <= clock_200_raw; sys_clk_i <= clock_100; - REF_CLK_OUT <= clock_200; + REF_CLK_OUT <= clock_200_raw; end generate; gen_fast_clock : if USE_120_MHZ = 1 generate RAW_CLK_OUT <= clock_240; @@ -72,7 +72,7 @@ gen_fast_clock : if USE_120_MHZ = 1 generate end generate; -clear_n_i <= timer(24) when rising_edge(CLOCK_IN); +clear_n_i <= timer(24) when rising_edge(clock_200_raw); process begin wait until rising_edge(sys_clk_i); @@ -109,7 +109,7 @@ THE_RESET_HANDLER : trb_net_reset_handler RESET_OUT <= reset_i; -last_reset_i <= reset_i when rising_edge(CLOCK_IN); +last_reset_i <= reset_i when rising_edge(clock_200_raw); reset_rising <= reset_i and not last_reset_i; --------------------------------------------------------------------------- diff --git a/combiner/par.p2t b/combiner/par.p2t index a89b69b..7f2e7bf 100644 --- a/combiner/par.p2t +++ b/combiner/par.p2t @@ -4,7 +4,7 @@ -n 1 -y -s 12 --t 31 +-t 33 -c 1 -e 2 #-g guidefile.ncd -- 2.43.0