From aa06321a382ee751f754eaa04cbf505c0d86a335 Mon Sep 17 00:00:00 2001 From: palka Date: Thu, 3 Dec 2009 16:28:18 +0000 Subject: [PATCH] new --- multiplicyty.vhd | 174 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 174 insertions(+) create mode 100644 multiplicyty.vhd diff --git a/multiplicyty.vhd b/multiplicyty.vhd new file mode 100644 index 0000000..9abed72 --- /dev/null +++ b/multiplicyty.vhd @@ -0,0 +1,174 @@ +library IEEE; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.all; +use work.version.all; +use work.trb_net_std.all; +use work.trb_net16_hub_func.all; +use ieee.std_logic_arith.all; + +entity multiplicyty is + + port ( + RESET : in std_logic; + CLK : in std_logic; + SIGNAL_IN : in std_logic_vector(5 downto 0); + SIGNAL_OUT : out std_logic_vector(7 downto 0) + ); +end multiplicyty; + +architecture multiplicyty of multiplicyty is +signal signal_out_i : std_logic_vector(9 downto 0); +begin + + + MULT1: process(CLK) + begin + if rising_edge(CLK) then + case SIGNAL_IN is + when "000001" => signal_out_i(0) <= '1'; + when "000010" => signal_out_i(0) <= '1'; + when "000100" => signal_out_i(0) <= '1'; + when "001000" => signal_out_i(0) <= '1'; + when "010000" => signal_out_i(0) <= '1'; + when "100000" => signal_out_i(0) <= '1'; + when others => signal_out_i(0) <= '0'; + end case; + end if; + end process MULT1; + + MULT2: process(CLK) + begin + if rising_edge(CLK) then + case SIGNAL_IN is + when "000011" => signal_out_i(1) <= '1'; + when "000101" => signal_out_i(1) <= '1'; + when "001001" => signal_out_i(1) <= '1'; + when "010001" => signal_out_i(1) <= '1'; + when "100001" => signal_out_i(1) <= '1'; + when "000110" => signal_out_i(1) <= '1'; + when "001010" => signal_out_i(1) <= '1'; + when "010010" => signal_out_i(1) <= '1'; + when "100010" => signal_out_i(1) <= '1'; + when "001100" => signal_out_i(1) <= '1'; + when "010100" => signal_out_i(1) <= '1'; + when "100100" => signal_out_i(1) <= '1'; + when "011000" => signal_out_i(1) <= '1'; + when "101000" => signal_out_i(1) <= '1'; + when "110000" => signal_out_i(1) <= '1'; + when others => signal_out_i(1) <= '0'; + end case; + end if; + end process MULT2; + + MULT3: process (CLK) + begin + if rising_edge(CLK) then + case SIGNAL_IN is + when "111000" => signal_out_i(2) <= '1'; + when "110100" => signal_out_i(2) <= '1'; + when "110010" => signal_out_i(2) <= '1'; + when "110001" => signal_out_i(2) <= '1'; + when "101001" => signal_out_i(2) <= '1'; + when "100101" => signal_out_i(2) <= '1'; + when "100011" => signal_out_i(2) <= '1'; + when "011100" => signal_out_i(2) <= '1'; + when "011010" => signal_out_i(2) <= '1'; + when "011001" => signal_out_i(2) <= '1'; + when "010101" => signal_out_i(2) <= '1'; + when "010011" => signal_out_i(2) <= '1'; + when "001110" => signal_out_i(2) <= '1'; + when "001101" => signal_out_i(2) <= '1'; + when "001011" => signal_out_i(2) <= '1'; + when "000111" => signal_out_i(2) <= '1'; + when "101100" => signal_out_i(2) <= '1'; + when "101010" => signal_out_i(2) <= '1'; + when "100110" => signal_out_i(2) <= '1'; + when "010110" => signal_out_i(2) <= '1'; + when others => signal_out_i(2) <= '0'; + end case; + end if; + end process MULT3; + + MULT4: process(CLK) + begin + if rising_edge(CLK) then + case SIGNAL_IN is + when "111100" => signal_out_i(3) <= '1'; + when "111010" => signal_out_i(3) <= '1'; + when "110110" => signal_out_i(3) <= '1'; + when "101110" => signal_out_i(3) <= '1'; + when "011110" => signal_out_i(3) <= '1'; + when "111001" => signal_out_i(3) <= '1'; + when "110101" => signal_out_i(3) <= '1'; + when "101101" => signal_out_i(3) <= '1'; + when "011101" => signal_out_i(3) <= '1'; + when "110011" => signal_out_i(3) <= '1'; + when "101011" => signal_out_i(3) <= '1'; + when "011011" => signal_out_i(3) <= '1'; + when "100111" => signal_out_i(3) <= '1'; + when "010111" => signal_out_i(3) <= '1'; + when "001111" => signal_out_i(3) <= '1'; + when others => signal_out_i(3) <= '0'; + end case; + end if; + end process MULT4; + + MULT5: process(CLK) + begin + if rising_edge(CLK) then + case SIGNAL_IN is + when "011111" => signal_out_i(4) <= '1'; + when "101111" => signal_out_i(4) <= '1'; + when "110111" => signal_out_i(4) <= '1'; + when "111011" => signal_out_i(4) <= '1'; + when "111101" => signal_out_i(4) <= '1'; + when "111110" => signal_out_i(4) <= '1'; + when others => signal_out_i(4) <= '0'; + end case; + end if; + end process MULT5; + + MULT6: process(CLK) + begin + if rising_edge(CLK) then + case SIGNAL_IN is + when "111111" => signal_out_i(5) <= '1'; + when others => signal_out_i(5) <= '0'; + end case; + end if; + end process MULT6; + + MULT2_NO_NEIGHBOUR: process(CLK) + begin + if rising_edge(CLK) then + case SIGNAL_IN is + when "101000" => signal_out_i(6) <= '1'; + when "100100" => signal_out_i(6) <= '1'; + when "100010" => signal_out_i(6) <= '1'; + when "010100" => signal_out_i(6) <= '1'; + when "010010" => signal_out_i(6) <= '1'; + when "010001" => signal_out_i(6) <= '1'; + when "001010" => signal_out_i(6) <= '1'; + when "001001" => signal_out_i(6) <= '1'; + when "000101" => signal_out_i(6) <= '1'; + when others => signal_out_i(6) <= '0'; + end case; + end if; + end process MULT2_NO_NEIGHBOUR; + + MULT3_NO_NEIGHBOUR: process(CLK) + begin + if rising_edge(CLK) then + case SIGNAL_IN is + when "101010" => signal_out_i(7) <= '1'; + when "010101" => signal_out_i(7) <= '1'; + when others => signal_out_i(7) <= '0'; + end case; + end if; + end process MULT3_NO_NEIGHBOUR; + +end multiplicyty; -- 2.43.0