From aa6c56b6cee0dd27a777eae4d0e9e24845110367 Mon Sep 17 00:00:00 2001 From: Cahit Date: Thu, 6 Aug 2015 17:25:36 +0200 Subject: [PATCH] added TDC to the design --- tdc_release | 2 +- template/config.vhd | 17 +- template/config_compile.pl | 2 +- template/config_compile_gsi.pl | 5 +- template/trb3sc_basic.prj | 32 ++ template/trb3sc_basic.vhd | 559 ++++++++++++++++++--------------- 6 files changed, 358 insertions(+), 259 deletions(-) diff --git a/tdc_release b/tdc_release index 4f793e3..e8932f5 120000 --- a/tdc_release +++ b/tdc_release @@ -1 +1 @@ -../tdc/releases/tdc_v2.1.3 \ No newline at end of file +../tdc/releases/tdc_v2.1.6 \ No newline at end of file diff --git a/template/config.vhd b/template/config.vhd index 2f2ec1f..7ccbb93 100644 --- a/template/config.vhd +++ b/template/config.vhd @@ -10,6 +10,21 @@ package config is --Begin of design configuration ------------------------------------------------------------------------------ +--TDC settings + constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement + constant NUM_TDC_CHANNELS : integer range 1 to 65 := 3; -- number of tdc channels per module + constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons + constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3 + -- 0: single edge only, + -- 1: same channel, + -- 2: alternating channels, + -- 3: same channel with stretcher + constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size: 0, 1, 2, 3, 7 --> change names in constraints file + --ring buffer size: 32,64,96,128,dyn + + constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 13; -- size of the event buffer, 2**N + constant EVENT_MAX_SIZE : integer := 4096; --maximum event size. Should not exceed EVENT_BUFFER_SIZE/2 + --Runs with 120 MHz instead of 100 MHz constant USE_120_MHZ : integer := c_NO; constant USE_EXTERNAL_CLOCK : integer := c_YES; --'no' not implemented. @@ -96,4 +111,4 @@ end function; constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures; -end package body; \ No newline at end of file +end package body; diff --git a/template/config_compile.pl b/template/config_compile.pl index 52cd2ef..67b86a0 120000 --- a/template/config_compile.pl +++ b/template/config_compile.pl @@ -1 +1 @@ -config_compile_frankfurt.pl \ No newline at end of file +config_compile_gsi.pl \ No newline at end of file diff --git a/template/config_compile_gsi.pl b/template/config_compile_gsi.pl index e931eda..2fa920e 100644 --- a/template/config_compile_gsi.pl +++ b/template/config_compile_gsi.pl @@ -3,11 +3,12 @@ lm_license_file_for_synplify => "27000\@lxcad01.gsi.de", lm_license_file_for_par => "1702\@hadeb05.gsi.de", lattice_path => '/opt/lattice/diamond/3.4_x64/', synplify_path => '/opt/synplicity/J-2014.09-SP2', -#synplify_command => "/opt/lattice/diamond/3.4_x64/bin/lin64/synpwrap -fg -options", +#synplify_command => "/opt/lattice/diamond/3.5_x64/bin/lin64/synpwrap -fg -options", synplify_command => "/opt/synplicity/J-2014.09-SP2/bin/synplify_premier_dp", nodelist_file => 'nodelist_gsi_template.txt', -firefox_open => 0, +include_TDC => 1, +firefox_open => 0, diff --git a/template/trb3sc_basic.prj b/template/trb3sc_basic.prj index 00d82b3..9c770cf 100644 --- a/template/trb3sc_basic.prj +++ b/template/trb3sc_basic.prj @@ -112,6 +112,7 @@ add_file -vhdl -lib work "../../trbnet/special/uart.vhd" add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd" add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd" add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" +add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd" #SlowControl files add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" @@ -174,6 +175,37 @@ add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd" add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd" +#TDC +add_file -vhdl -lib work "../tdc_release/tdc_version.vhd" +add_file -vhdl -lib work "../tdc_release/tdc_components.vhd" +add_file -vhdl -lib work "../tdc_release/bit_sync.vhd" +add_file -vhdl -lib work "../tdc_release/BusHandler.vhd" +add_file -vhdl -lib work "../tdc_release/BusHandler_record.vhd" +add_file -vhdl -lib work "../tdc_release/Channel_200.vhd" +add_file -vhdl -lib work "../tdc_release/Channel.vhd" +add_file -vhdl -lib work "../tdc_release/Encoder_304_Bit.vhd" +add_file -vhdl -lib work "../tdc_release/fallingEdgeDetect.vhd" +add_file -vhdl -lib work "../tdc_release/hit_mux.vhd" +add_file -vhdl -lib work "../tdc_release/LogicAnalyser.vhd" +add_file -vhdl -lib work "../tdc_release/Readout.vhd" +add_file -vhdl -lib work "../tdc_release/risingEdgeDetect.vhd" +add_file -vhdl -lib work "../tdc_release/ROM_encoder_ecp3.vhd" +add_file -vhdl -lib work "../tdc_release/ShiftRegisterSISO.vhd" +add_file -vhdl -lib work "../tdc_release/Stretcher_A.vhd" +add_file -vhdl -lib work "../tdc_release/Stretcher_B.vhd" +add_file -vhdl -lib work "../tdc_release/Stretcher.vhd" +add_file -vhdl -lib work "../tdc_release/TDC.vhd" +add_file -vhdl -lib work "../tdc_release/TDC_record.vhd" +add_file -vhdl -lib work "../tdc_release/TriggerHandler.vhd" +add_file -vhdl -lib work "../tdc_release/up_counter.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x128_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x64_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x32_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x128_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x64_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x32_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp3/PLL/pll_in125_out33.vhd" diff --git a/template/trb3sc_basic.vhd b/template/trb3sc_basic.vhd index 5f1afed..049ac43 100644 --- a/template/trb3sc_basic.vhd +++ b/template/trb3sc_basic.vhd @@ -8,6 +8,7 @@ use work.config.all; use work.trb_net_std.all; use work.trb_net_components.all; use work.trb3_components.all; +use work.tdc_components.all; use work.trb_net16_hub_func.all; use work.version.all; use work.trb_net_gbe_components.all; @@ -15,92 +16,92 @@ use work.med_sync_define.all; entity trb3sc_basic is port( - CLK_SUPPL_PCLK : in std_logic; --125 MHz for GbE - CLK_CORE_PCLK : in std_logic; --Main Oscillator - CLK_EXT_PLL_LEFT : in std_logic; --External Clock + CLK_SUPPL_PCLK : in std_logic; --125 MHz for GbE + CLK_CORE_PCLK : in std_logic; --Main Oscillator + CLK_EXT_PLL_LEFT : in std_logic; --External Clock --CLK_SUPPL_PLL_LEFT : in std_logic; --not used --CLK_SUPPL_PLL_RIGHT : in std_logic; --not used --CLK_CORE_PLL_LEFT : in std_logic; --not used --CLK_CORE_PLL_RIGHT : in std_logic; --not used --CLK_EXT_PCLK : in std_logic; --not used --CLK_EXT_PLL_RIGHT : in std_logic; --not used - - TRIG_LEFT : in std_logic; --Trigger Input + + TRIG_LEFT : in std_logic; --Trigger Input --TRIG_PLL : in std_logic; --not used --TRIG_RIGHT : in std_logic; --not used - + --Backplane, all lines - BACK_GPIO : inout std_logic_vector(15 downto 0); - BACK_LVDS : inout std_logic_vector( 1 downto 0); - BACK_3V3 : inout std_logic_vector( 3 downto 0); + BACK_GPIO : inout std_logic_vector(15 downto 0); + BACK_LVDS : inout std_logic_vector(1 downto 0); + BACK_3V3 : inout std_logic_vector(3 downto 0); --Backplane for slaves on trbv3scbp1 -- BACK_GPIO : inout std_logic_vector(3 downto 0); - + --AddOn Connector --to be added - + --KEL Connector --- KEL : inout std_logic_vector(40 downto 1); - + KEL : inout std_logic_vector(40 downto 1); + --Additional IO - HDR_IO : inout std_logic_vector(10 downto 1); - RJ_IO : inout std_logic_vector( 3 downto 0); - SPARE_IN : in std_logic_vector( 1 downto 0); - + HDR_IO : inout std_logic_vector(10 downto 1); + RJ_IO : inout std_logic_vector(3 downto 0); + SPARE_IN : in std_logic_vector(1 downto 0); + --LED - LED_GREEN : out std_logic; - LED_YELLOW : out std_logic; - LED_ORANGE : out std_logic; - LED_RED : out std_logic; - LED_RJ_GREEN : out std_logic_vector( 1 downto 0); - LED_RJ_RED : out std_logic_vector( 1 downto 0); - LED_WHITE : out std_logic_vector( 1 downto 0); - LED_SFP_GREEN : out std_logic_vector( 1 downto 0); - LED_SFP_RED : out std_logic_vector( 1 downto 0); - + LED_GREEN : out std_logic; + LED_YELLOW : out std_logic; + LED_ORANGE : out std_logic; + LED_RED : out std_logic; + LED_RJ_GREEN : out std_logic_vector(1 downto 0); + LED_RJ_RED : out std_logic_vector(1 downto 0); + LED_WHITE : out std_logic_vector(1 downto 0); + LED_SFP_GREEN : out std_logic_vector(1 downto 0); + LED_SFP_RED : out std_logic_vector(1 downto 0); + --SFP - SFP_LOS : in std_logic_vector( 1 downto 0); - SFP_MOD0 : in std_logic_vector( 1 downto 0); - SFP_MOD1 : inout std_logic_vector( 1 downto 0) := (others => 'Z'); - SFP_MOD2 : inout std_logic_vector( 1 downto 0) := (others => 'Z'); - SFP_TX_DIS : out std_logic_vector( 1 downto 0) := (others => '0'); - - SERDES_TX : out std_logic_vector(1 downto 0); - SERDES_RX : in std_logic_vector(1 downto 0); - + SFP_LOS : in std_logic_vector(1 downto 0); + SFP_MOD0 : in std_logic_vector(1 downto 0); + SFP_MOD1 : inout std_logic_vector(1 downto 0) := (others => 'Z'); + SFP_MOD2 : inout std_logic_vector(1 downto 0) := (others => 'Z'); + SFP_TX_DIS : out std_logic_vector(1 downto 0) := (others => '0'); + + SERDES_TX : out std_logic_vector(1 downto 0); + SERDES_RX : in std_logic_vector(1 downto 0); + --Serdes switch - PCSSW_ENSMB : out std_logic; - PCSSW_EQ : out std_logic_vector( 3 downto 0); - PCSSW_PE : out std_logic_vector( 3 downto 0); - PCSSW : out std_logic_vector( 7 downto 0); - + PCSSW_ENSMB : out std_logic; + PCSSW_EQ : out std_logic_vector(3 downto 0); + PCSSW_PE : out std_logic_vector(3 downto 0); + PCSSW : out std_logic_vector(7 downto 0); + --ADC - ADC_CLK : out std_logic; - ADC_CS : out std_logic; - ADC_DIN : out std_logic; - ADC_DOUT : in std_logic; + ADC_CLK : out std_logic; + ADC_CS : out std_logic; + ADC_DIN : out std_logic; + ADC_DOUT : in std_logic; --Flash, 1-wire, Reload - FLASH_CLK : out std_logic; - FLASH_CS : out std_logic; - FLASH_IN : out std_logic; - FLASH_OUT : in std_logic; - PROGRAMN : out std_logic; - ENPIRION_CLOCK : out std_logic; - TEMPSENS : inout std_logic; - + FLASH_CLK : out std_logic; + FLASH_CS : out std_logic; + FLASH_IN : out std_logic; + FLASH_OUT : in std_logic; + PROGRAMN : out std_logic; + ENPIRION_CLOCK : out std_logic; + TEMPSENS : inout std_logic; + --Test Connectors - TEST_LINE : out std_logic_vector(15 downto 0) + TEST_LINE : out std_logic_vector(15 downto 0) ); - attribute syn_useioff : boolean; - attribute syn_useioff of FLASH_CLK : signal is true; - attribute syn_useioff of FLASH_CS : signal is true; - attribute syn_useioff of FLASH_IN : signal is true; - attribute syn_useioff of FLASH_OUT : signal is true; + attribute syn_useioff : boolean; + attribute syn_useioff of FLASH_CLK : signal is true; + attribute syn_useioff of FLASH_CS : signal is true; + attribute syn_useioff of FLASH_IN : signal is true; + attribute syn_useioff of FLASH_OUT : signal is true; + - --Serdes: Backplane --Backplane A2,A3,A0,A1 Slave 3,4,1,2, A0: TrbNet from backplane --AddOn C2,C3,C0,C1,B0,B1,B2,D1(B3) Slave --,--,5,9,8,7,6,-- @@ -112,232 +113,243 @@ end entity; architecture trb3sc_arch of trb3sc_basic is attribute syn_keep : boolean; attribute syn_preserve : boolean; - - signal clk_sys, clk_full, clk_full_osc : std_logic; - signal GSR_N : std_logic; - signal reset_i : std_logic; - signal clear_i : std_logic; - + + signal clk_sys, clk_full, clk_full_osc, clk_cal : std_logic; + signal GSR_N : std_logic; + signal reset_i : std_logic; + signal clear_i : std_logic; + signal time_counter : unsigned(31 downto 0) := (others => '0'); signal led : std_logic_vector(1 downto 0); signal debug_clock_reset : std_logic_vector(31 downto 0); --Media Interface - signal med2int : med2int_array_t(0 to 0); - signal int2med : int2med_array_t(0 to 0); - signal med_stat_debug : std_logic_vector (1*64-1 downto 0); - + signal med2int : med2int_array_t(0 to 0); + signal int2med : int2med_array_t(0 to 0); + signal med_stat_debug : std_logic_vector (1*64-1 downto 0); + --READOUT - signal readout_rx : READOUT_RX; - signal readout_tx : readout_tx_array_t(0 to 0); + signal readout_rx : READOUT_RX; + signal readout_tx : readout_tx_array_t(0 to 0); + + signal ctrlbus_rx, bussci_rx, bustools_rx, bustc_rx, bustdc_rx : CTRLBUS_RX; + signal ctrlbus_tx, bussci_tx, bustools_tx, bustc_tx, bustdc_tx : CTRLBUS_TX; + + signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); + signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); + + signal sed_error_i : std_logic; + signal clock_select : std_logic; - signal ctrlbus_rx, bussci_rx, bustools_rx, bustc_rx : CTRLBUS_RX; - signal ctrlbus_tx, bussci_tx, bustools_tx, bustc_tx : CTRLBUS_TX; - - signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); - signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); - - signal sed_error_i : std_logic; - signal clock_select : std_logic; - signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0); - signal uart_tx, uart_rx : std_logic; + signal uart_tx, uart_rx : std_logic; - signal timer : TIMERS; - signal lcd_data : std_logic_vector(511 downto 0); - - attribute syn_keep of GSR_N : signal is true; - attribute syn_preserve of GSR_N : signal is true; - attribute syn_keep of bussci_rx : signal is true; - attribute syn_preserve of bussci_rx : signal is true; + signal timer : TIMERS; + signal lcd_data : std_logic_vector(511 downto 0); + + --TDC + signal hit_in_i : std_logic_vector(64 downto 1); + signal logic_analyser_i : std_logic_vector(15 downto 0); + + attribute syn_keep of GSR_N : signal is true; + attribute syn_preserve of GSR_N : signal is true; + attribute syn_keep of bussci_rx : signal is true; + attribute syn_preserve of bussci_rx : signal is true; attribute syn_keep of bustools_rx : signal is true; - attribute syn_preserve of bustools_rx : signal is true; - attribute syn_keep of bustc_rx : signal is true; - attribute syn_preserve of bustc_rx : signal is true; + attribute syn_preserve of bustools_rx : signal is true; + attribute syn_keep of bustc_rx : signal is true; + attribute syn_preserve of bustc_rx : signal is true; begin --------------------------------------------------------------------------- -- Clock & Reset Handling --------------------------------------------------------------------------- -THE_CLOCK_RESET : entity work.clock_reset_handler - port map( - INT_CLK_IN => CLK_CORE_PCLK, - EXT_CLK_IN => CLK_EXT_PLL_LEFT, - NET_CLK_FULL_IN => med2int(0).clk_full, - NET_CLK_HALF_IN => med2int(0).clk_half, - RESET_FROM_NET => med2int(0).stat_op(13), - - BUS_RX => bustc_rx, - BUS_TX => bustc_tx, - - RESET_OUT => reset_i, - CLEAR_OUT => clear_i, - GSR_OUT => GSR_N, - - FULL_CLK_OUT => clk_full, - SYS_CLK_OUT => clk_sys, - REF_CLK_OUT => clk_full_osc, - - ENPIRION_CLOCK => ENPIRION_CLOCK, - LED_RED_OUT => LED_RJ_RED, - LED_GREEN_OUT => LED_RJ_GREEN, - DEBUG_OUT => debug_clock_reset - ); + THE_CLOCK_RESET : entity work.clock_reset_handler + port map( + INT_CLK_IN => CLK_CORE_PCLK, + EXT_CLK_IN => CLK_EXT_PLL_LEFT, + NET_CLK_FULL_IN => med2int(0).clk_full, + NET_CLK_HALF_IN => med2int(0).clk_half, + RESET_FROM_NET => med2int(0).stat_op(13), + + BUS_RX => bustc_rx, + BUS_TX => bustc_tx, + + RESET_OUT => reset_i, + CLEAR_OUT => clear_i, + GSR_OUT => GSR_N, + + FULL_CLK_OUT => clk_full, + SYS_CLK_OUT => clk_sys, + REF_CLK_OUT => clk_full_osc, + + ENPIRION_CLOCK => ENPIRION_CLOCK, + LED_RED_OUT => LED_RJ_RED, + LED_GREEN_OUT => LED_RJ_GREEN, + DEBUG_OUT => debug_clock_reset + ); + pll_calibration : entity work.pll_in125_out33 + port map ( + CLK => CLK_SUPPL_PCLK, + CLKOP => clk_cal, + LOCK => open); --------------------------------------------------------------------------- -- TrbNet Uplink --------------------------------------------------------------------------- -THE_MEDIA_INTERFACE : entity work.med_ecp3_sfp_sync - generic map( - SERDES_NUM => 3, - IS_SYNC_SLAVE => c_YES - ) - port map( - CLK => clk_full_osc, - SYSCLK => clk_sys, - RESET => reset_i, - CLEAR => clear_i, - --Internal Connection - MEDIA_MED2INT => med2int(0), - MEDIA_INT2MED => int2med(0), - - --Sync operation - RX_DLM => open, - RX_DLM_WORD => open, - TX_DLM => open, - TX_DLM_WORD => open, - - --SFP Connection - SD_RXD_P_IN => SERDES_RX(0), - SD_RXD_N_IN => SERDES_RX(1), - SD_TXD_P_OUT => SERDES_TX(0), - SD_TXD_N_OUT => SERDES_TX(1), - SD_REFCLK_P_IN => '0', - SD_REFCLK_N_IN => '0', - SD_PRSNT_N_IN => SFP_MOD0(1), - SD_LOS_IN => SFP_LOS(1), - SD_TXDIS_OUT => SFP_TX_DIS(1), - --Control Interface - BUS_RX => bussci_rx, - BUS_TX => bussci_tx, - -- Status and control port - STAT_DEBUG => med_stat_debug(63 downto 0), - CTRL_DEBUG => open - ); - -SFP_TX_DIS(0) <= '1'; + THE_MEDIA_INTERFACE : entity work.med_ecp3_sfp_sync + generic map( + SERDES_NUM => 3, + IS_SYNC_SLAVE => c_YES + ) + port map( + CLK => clk_full_osc, + SYSCLK => clk_sys, + RESET => reset_i, + CLEAR => clear_i, + --Internal Connection + MEDIA_MED2INT => med2int(0), + MEDIA_INT2MED => int2med(0), + + --Sync operation + RX_DLM => open, + RX_DLM_WORD => open, + TX_DLM => open, + TX_DLM_WORD => open, + + --SFP Connection + SD_RXD_P_IN => SERDES_RX(0), + SD_RXD_N_IN => SERDES_RX(1), + SD_TXD_P_OUT => SERDES_TX(0), + SD_TXD_N_OUT => SERDES_TX(1), + SD_REFCLK_P_IN => '0', + SD_REFCLK_N_IN => '0', + SD_PRSNT_N_IN => SFP_MOD0(1), + SD_LOS_IN => SFP_LOS(1), + SD_TXDIS_OUT => SFP_TX_DIS(1), + --Control Interface + BUS_RX => bussci_rx, + BUS_TX => bussci_tx, + -- Status and control port + STAT_DEBUG => med_stat_debug(63 downto 0), + CTRL_DEBUG => open + ); + + SFP_TX_DIS(0) <= '1'; --------------------------------------------------------------------------- -- Endpoint --------------------------------------------------------------------------- -THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record - generic map ( - ADDRESS_MASK => x"FFFF", - BROADCAST_BITMASK => x"FF", - REGIO_INIT_ENDPOINT_ID => x"0001", - TIMING_TRIGGER_RAW => c_YES, - --Configure data handler - DATA_INTERFACE_NUMBER => 1, - DATA_BUFFER_DEPTH => 10, - DATA_BUFFER_WIDTH => 32, - DATA_BUFFER_FULL_THRESH => 2**8, - TRG_RELEASE_AFTER_DATA => c_YES, - HEADER_BUFFER_DEPTH => 9, - HEADER_BUFFER_FULL_THRESH => 2**8 - ) - - port map( - -- Misc - CLK => clk_sys, - RESET => reset_i, - CLK_EN => '1', - - -- Media direction port - MEDIA_MED2INT => med2int(0), - MEDIA_INT2MED => int2med(0), - - --Timing trigger in - TRG_TIMING_TRG_RECEIVED_IN => TRIG_LEFT, - - READOUT_RX => readout_rx, - READOUT_TX => readout_tx, - - --Slow Control Port - REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00 - REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 - BUS_RX => ctrlbus_rx, - BUS_TX => ctrlbus_tx, - ONEWIRE_INOUT => TEMPSENS, - --Timing registers - TIMERS_OUT => timer - ); + THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record + generic map ( + ADDRESS_MASK => x"FFFF", + BROADCAST_BITMASK => x"FF", + REGIO_INIT_ENDPOINT_ID => x"0001", + TIMING_TRIGGER_RAW => c_YES, + --Configure data handler + DATA_INTERFACE_NUMBER => 1, + DATA_BUFFER_DEPTH => 10, + DATA_BUFFER_WIDTH => 32, + DATA_BUFFER_FULL_THRESH => 2**8, + TRG_RELEASE_AFTER_DATA => c_YES, + HEADER_BUFFER_DEPTH => 9, + HEADER_BUFFER_FULL_THRESH => 2**8 + ) + + port map( + -- Misc + CLK => clk_sys, + RESET => reset_i, + CLK_EN => '1', + + -- Media direction port + MEDIA_MED2INT => med2int(0), + MEDIA_INT2MED => int2med(0), + + --Timing trigger in + TRG_TIMING_TRG_RECEIVED_IN => TRIG_LEFT, + + READOUT_RX => readout_rx, + READOUT_TX => readout_tx, + + --Slow Control Port + REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00 + REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 + BUS_RX => ctrlbus_rx, + BUS_TX => ctrlbus_tx, + ONEWIRE_INOUT => TEMPSENS, + --Timing registers + TIMERS_OUT => timer + ); --------------------------------------------------------------------------- -- Bus Handler --------------------------------------------------------------------------- THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record generic map( - PORT_NUMBER => 3, - PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", others => x"0000"), - PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, others => 0), + PORT_NUMBER => 4, + PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"c000", others => x"0000"), + PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 12, others => 0), PORT_MASK_ENABLE => 1 ) port map( CLK => clk_sys, RESET => reset_i, - REGIO_RX => ctrlbus_rx, - REGIO_TX => ctrlbus_tx, - - BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED - BUS_RX(1) => bussci_rx, --SCI Serdes - BUS_RX(2) => bustc_rx, --Clock switch + REGIO_RX => ctrlbus_rx, + REGIO_TX => ctrlbus_tx, + + BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED + BUS_RX(1) => bussci_rx, --SCI Serdes + BUS_RX(2) => bustc_rx, --Clock switch + BUS_RX(3) => bustdc_rx, --TDC config BUS_TX(0) => bustools_tx, BUS_TX(1) => bussci_tx, BUS_TX(2) => bustc_tx, - + BUS_TX(3) => bustdc_tx, + STAT_DEBUG => open ); --------------------------------------------------------------------------- -- Control Tools --------------------------------------------------------------------------- - THE_TOOLS: entity work.trb3sc_tools + THE_TOOLS : entity work.trb3sc_tools port map( - CLK => clk_sys, - RESET => reset_i, - + CLK => clk_sys, + RESET => reset_i, + --Flash & Reload - FLASH_CS => FLASH_CS, - FLASH_CLK => FLASH_CLK, - FLASH_IN => FLASH_OUT, - FLASH_OUT => FLASH_IN, - PROGRAMN => PROGRAMN, - REBOOT_IN => common_ctrl_reg(15), + FLASH_CS => FLASH_CS, + FLASH_CLK => FLASH_CLK, + FLASH_IN => FLASH_OUT, + FLASH_OUT => FLASH_IN, + PROGRAMN => PROGRAMN, + REBOOT_IN => common_ctrl_reg(15), --SPI - SPI_CS_OUT => spi_cs, - SPI_MOSI_OUT=> spi_mosi, - SPI_MISO_IN => spi_miso, - SPI_CLK_OUT => spi_clk, + SPI_CS_OUT => spi_cs, + SPI_MOSI_OUT => spi_mosi, + SPI_MISO_IN => spi_miso, + SPI_CLK_OUT => spi_clk, --Header - HEADER_IO => HDR_IO, + HEADER_IO => HDR_IO, --LCD - LCD_DATA_IN => lcd_data, + LCD_DATA_IN => lcd_data, --ADC - ADC_CS => ADC_CS, - ADC_MOSI => ADC_DIN, - ADC_MISO => ADC_DOUT, - ADC_CLK => ADC_CLK, + ADC_CS => ADC_CS, + ADC_MOSI => ADC_DIN, + ADC_MISO => ADC_DOUT, + ADC_CLK => ADC_CLK, --SED SED_ERROR_OUT => sed_error_i, --Slowcontrol - BUS_RX => bustools_rx, - BUS_TX => bustools_tx, - - DEBUG_OUT => open + BUS_RX => bustools_rx, + BUS_TX => bustools_tx, + + DEBUG_OUT => open ); --------------------------------------------------------------------------- @@ -347,53 +359,92 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record PCSSW_ENSMB <= '0'; PCSSW_EQ <= x"0"; PCSSW_PE <= x"F"; - PCSSW <= "01001110"; --SFP2 on B3, AddOn on D1 + PCSSW <= "01001110"; --SFP2 on B3, AddOn on D1 --------------------------------------------------------------------------- -- I/O --------------------------------------------------------------------------- - RJ_IO <= "0000"; - - BACK_GPIO <= (others => 'Z'); - BACK_LVDS <= (others => '0'); - BACK_3V3 <= (others => 'Z'); + RJ_IO <= "0000"; + + BACK_GPIO <= (others => 'Z'); + BACK_LVDS <= (others => '0'); + BACK_3V3 <= (others => 'Z'); + - --------------------------------------------------------------------------- -- LCD Data to display --------------------------------------------------------------------------- - lcd_data(15 downto 0) <= timer.network_address; - lcd_data(47 downto 16) <= timer.microsecond; - lcd_data(79 downto 48) <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)); - lcd_data(511 downto 80) <= (others => '0'); - + lcd_data(15 downto 0) <= timer.network_address; + lcd_data(47 downto 16) <= timer.microsecond; + lcd_data(79 downto 48) <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)); + lcd_data(511 downto 80) <= (others => '0'); + --------------------------------------------------------------------------- -- LED --------------------------------------------------------------------------- --LED are green, orange, red, yellow, white(2), rj_green(2), rj_red(2), sfp_green(2), sfp_red(2) - LED_GREEN <= debug_clock_reset(0); - LED_ORANGE <= debug_clock_reset(1); - LED_RED <= not sed_error_i; - LED_YELLOW <= debug_clock_reset(2); - LED_WHITE(0) <= time_counter(26) and time_counter(19); - LED_WHITE(1) <= time_counter(20); - LED_SFP_GREEN <= not med2int(0).stat_op(9) & '1'; --SFP Link Status - LED_SFP_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)) & '1'; --SFP RX/TX + LED_GREEN <= debug_clock_reset(0); + LED_ORANGE <= debug_clock_reset(1); + LED_RED <= not sed_error_i; + LED_YELLOW <= debug_clock_reset(2); + LED_WHITE(0) <= time_counter(26) and time_counter(19); + LED_WHITE(1) <= time_counter(20); + LED_SFP_GREEN <= not med2int(0).stat_op(9) & '1'; --SFP Link Status + LED_SFP_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)) & '1'; --SFP RX/TX --------------------------------------------------------------------------- -- Test Circuits --------------------------------------------------------------------------- - process begin + process + begin wait until rising_edge(clk_sys); - time_counter <= time_counter + 1; + time_counter <= time_counter + 1; if reset_i = '1' then time_counter <= (others => '0'); end if; - end process; + end process; + - -- TEST_LINE <= med_stat_debug(15 downto 0); + +------------------------------------------------------------------------------- +-- TDC +------------------------------------------------------------------------------- + THE_TDC : TDC_record + generic map ( + CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels per module + STATUS_REG_NR => 21, -- Number of status regs + DEBUG => c_YES, + SIMULATION => c_NO) + port map ( + RESET => reset_i, + CLK_TDC => CLK_EXT_PLL_LEFT, + CLK_READOUT => clk_sys, -- Clock for the readout + REFERENCE_TIME => TRIG_LEFT, -- Reference time input + HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals + HIT_CAL_IN => clk_cal, -- Hits for calibrating the TDC + -- Trigger signals from handler + READOUT_RX => readout_rx, + READOUT_TX => readout_tx(0), + -- + LOGIC_ANALYSER_OUT => logic_analyser_i, + BUS_RX => bustdc_rx, + BUS_TX => bustdc_tx); + + -- For single edge measurements + gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate + hit_in_i(40 downto 1) <= KEL(40 downto 1); + end generate; + + -- For ToT Measurements + gen_double : if DOUBLE_EDGE_TYPE = 2 generate + Gen_Hit_In_Signals : for i in 1 to 20 generate + hit_in_i(i*2-1) <= KEL(i); + hit_in_i(i*2) <= not KEL(i); + end generate Gen_Hit_In_Signals; + end generate; + end architecture; -- 2.43.0