From ab1a46cdec20eadeaa8a640e0cb7a91f5969522e Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Fri, 10 May 2013 14:47:12 +0200 Subject: [PATCH] added description of CTS AddOn --- trb3/CtsAddOn.tex | 59 ++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 58 insertions(+), 1 deletion(-) diff --git a/trb3/CtsAddOn.tex b/trb3/CtsAddOn.tex index fc1a65a..352efd2 100644 --- a/trb3/CtsAddOn.tex +++ b/trb3/CtsAddOn.tex @@ -1 +1,58 @@ -An AddOn for the central FPGA featuring some CTS I/O connections. Not yet designed. \ No newline at end of file +\begin{table} + \begin{center} + \begin{tabularx}{\textwidth}{|l|c|c|c|X|} \hline + \textbf{Name} & \textbf{I/O} & \textbf{Type} & \textbf{Cnt} & \textbf{Description}\\ + \hline + \netname{EclIn} & ECL In & RJ-45 & 4 & ECL Standard input. Routed as TTL signal on-board\\ + \netname{NimIn} & NIM In & LEMO & 2 & NIM Standard input. Routed as TTL signal on-board\\ + \netname{JIn1} & LVDS In & RJ-45 & 4 & \\ + \netname{JIn2} & LVDS In & RJ-45 & 4 & \\ + \netname{JInLvds} & TTL I/O & pinhead & 16 & first two and last two pins are GND.\\ + \hline + \netname{ComparatorIn} & Analog In & pinhead & 2 & See extra table for pin-out\\ + \netname{PwmOut} & TTL Out & pinhead & 2 & See extra table for pin-out\\ + \hline + \netname{JOut1} & LVDS Out & RJ-45 & 4 & \\ + \netname{JOut2} & LVDS Out & RJ-45 & 4 & \\ + \netname{JOutLvds} & LVDS Out & pinhead & 8 & first and last two pins are GND\\ + \netname{JTtl} & TTL I/O & pinhead & 16 & first and last two pins are GND\\ + \netname{TrgFanoutAddOn} & LVDS Out & -- & 4+8 & trigger signal to fan-out chip. Available on RJ-45 and pinhead \\ + \hline + \netname{LedBank} & & & 8 & 8 yellow LED in a row\\ + \netname{LedFan*} & & & 4 & 4 colorful LED next to fan-out chip\\ + \netname{LedRj} & & & 2x6 & red and green LED for each RJ-45 connector. Order is JIn1, JIn2, JOut1, JOut2, JFan2, EclIn\\ + \hline + \end{tabularx} + \caption[CTS AddOn I/O]{I/O connectors and devices on CTS AddOn} + \label{tab:cts_addon_io} + \end{center} +\end{table} + +\begin{table} + \begin{center} + \begin{tabular}{|l|l|} \hline + \textbf{Pin} & \textbf{Signal}\\ + \hline + 1 & Input 0\\ + 2 & Filtered DAC 0\\ + 3 & GND\\ + 4 & Raw DAC 0\\ + 5 & GND\\ + 6 & Raw DAC 1\\ + 7 & Input 1\\ + 8 & Filtered DAC 1\\ + \hline + \end{tabular} + \caption[CTS AddOn Discriminator Input]{Pinout of the discriminator input of the CTS AddOn} + \label{tab:cts_addon_comp} + \end{center} +\end{table} + +An AddOn for the central FPGA featuring some CTS I/O connections. Since it was not forseen to actually use such an AddOn when the TRB3 was designed, there are several possible issues with the design: +\begin{itemize*} +\item All LVDS outputs from the FPGA to the AddOn do not use standard LVDS-outputs, but emulated signals (FPGA produces differential TTL signals which are sent through three resistors to adjust signal heights and impedance. The performance might be somewhat lower than on dedicated LVDS lines (e.g. on the two RJ-45 connectors on the TRB3 itself) +\item Most of the differential lines on the AddOn are not routed differentially on the TRB3 which might have an influence on the signal quality +\item The connector \netname{JInLvds} can not be used as LVDS input - during layout the signals have been mixed up. Only TTL signals are available, despite on the last two pairs which might be used as LVDS but are not configured as LVDS by default. +\item The board has two analog discriminator inputs, using a reference produced by the FPGA. The pin-out of the connector is as shown in table \ref{tab:cts_addon_comp}. + +\end{itemize*} \ No newline at end of file -- 2.43.0