From ac3e3bdc0d07a0d4442cc54748351d0b2f1d450c Mon Sep 17 00:00:00 2001 From: Adrian Weber Date: Fri, 18 Sep 2020 13:22:24 +0200 Subject: [PATCH] Included MBS, TDC and a online calib entity for MBS-TDC; TDC and calib not used. Still problems with Placing! --- combiner_cts/combiner.lpf | 11 +- combiner_cts/combiner.prj | 42 +++++-- combiner_cts/combiner.vhd | 162 +++++++++++++++++++++---- combiner_cts/config.vhd | 17 ++- combiner_cts/config_compile_giessen.pl | 5 +- combiner_cts/tdc_release | 1 + 6 files changed, 193 insertions(+), 45 deletions(-) create mode 120000 combiner_cts/tdc_release diff --git a/combiner_cts/combiner.lpf b/combiner_cts/combiner.lpf index 6d5a39d..32290f0 100644 --- a/combiner_cts/combiner.lpf +++ b/combiner_cts/combiner.lpf @@ -12,17 +12,18 @@ FREQUENCY PORT CLOCK_PCLK 200 MHz; FREQUENCY NET "THE_MEDIA*/clk_rx_full" 200 MHz; # HOLD_MARGIN 500 ps FREQUENCY NET "THE_MEDIA*/clk_tx_full" 200 MHz; # HOLD_MARGIN 500 ps - +#BLOCK PATH FROM CELL THE_TDC/calibration_o*; +BLOCK PATH FROM CELL THE_CTS/TIME_REFERENCE_OUT TO CELL THE_TDC/ReferenceChannel/Channel200/SimAdderNo.FC/FF*; LOCATE COMP "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/PCSD_INST" SITE "PCSC" ; LOCATE COMP "THE_MEDIA_4_DOWN_A/THE_SERDES/PCSD_INST" SITE "PCSA" ; LOCATE COMP "THE_MEDIA_4_DOWN_B/THE_SERDES/PCSD_INST" SITE "PCSB" ; LOCATE COMP "THE_MEDIA_4_DOWN_D/THE_SERDES/PCSD_INST" SITE "PCSD" ; -REGION "MEDIA_A" "R80C91D" 35 36; -REGION "MEDIA_B" "R80C55D" 35 36; -REGION "MEDIA_C" "R80C127D" 35 36; -REGION "MEDIA_D" "R80C19D" 35 36; +REGION "MEDIA_A" "R85C91D" 35 36; +REGION "MEDIA_B" "R85C55D" 35 36; +REGION "MEDIA_C" "R85C127D" 35 36; +REGION "MEDIA_D" "R85C19D" 35 36; #REGION "MEDIA_DOWN1" "R93C10D" 22 160; diff --git a/combiner_cts/combiner.prj b/combiner_cts/combiner.prj index fa8d943..d9e973a 100644 --- a/combiner_cts/combiner.prj +++ b/combiner_cts/combiner.prj @@ -82,6 +82,7 @@ add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd" add_file -vhdl -lib work "../../trb3/base/code/sedcheck.vhd" add_file -vhdl -lib work "../../trbnet/basics/priority_arbiter.vhd" +add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd" #Fifos @@ -227,18 +228,37 @@ add_file -vhdl -lib work "../../cri/src/cri_data_sender.vhd" add_file -vhdl -lib work "../../trb3/cts/source/mbs_master.vhd" add_file -vhdl -lib work "../../trb3sc/hub_cts/code/mbs_vulom_recv.vhd" -#TDC Calibration -#add_file -vhdl -lib work "./code/Calibration.vhd" -#add_file -vhdl -lib work "./code/Cal_Limits_v2.vhd" -#add_file -vhdl -lib work "./code/cnt_val.vhd" -#add_file -vhdl -lib work "./code/default_val.vhd" -#add_file -vhdl -lib work "./code/LUT.vhd" -#add_file -vhdl -lib work "./code/Memory.vhd" -#add_file -vhdl -lib work "./code/Memory_curr.vhd" -#add_file -vhdl -lib work "./code/read_cnt.vhd" -#add_file -vhdl -lib work "./code/compare_old.vhd" -#add_file -vhdl -lib work "./code/Calc_output.vhd" +#TDC +add_file -vhdl -lib work "../../trb3sc/tdc_release/tdc_version.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/tdc_components.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/bit_sync.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/BusHandler_record.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/Channel_200.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/Channel.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/Encoder_288_Bit.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/fallingEdgeDetect.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/hit_mux.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/LogicAnalyser.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/Readout_record.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/risingEdgeDetect.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/ROM_encoder_ecp3.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/ShiftRegisterSISO.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/Stretcher_A.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/Stretcher_B.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/Stretcher.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/TDC_record.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/TriggerHandler.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/up_counter.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x128_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x64_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x32_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x128_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x64_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x32_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp3/PLL/pll_in125_out33.vhd" +#TDC Calibration add_file -vhdl -lib work "./code_EBR/Calibration.vhd" add_file -vhdl -lib work "./code_EBR/Cal_Limits_v2.vhd" add_file -vhdl -lib work "./code_EBR/cnt_val.vhd" diff --git a/combiner_cts/combiner.vhd b/combiner_cts/combiner.vhd index d531d74..777b429 100644 --- a/combiner_cts/combiner.vhd +++ b/combiner_cts/combiner.vhd @@ -1,6 +1,7 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; +use ieee.std_logic_UNSIGNED.ALL; library work; use work.version.all; @@ -115,8 +116,8 @@ architecture arch of combiner is signal int2med : int2med_array_t(0 to INTERFACE_NUM); -- 1 more due to uplink signal med_stat_debug : std_logic_vector (1*64-1 downto 0); - signal ctrlbus_rx, bustools_rx, bustc_rx, bus_master_out, handlerbus_rx, busdebug_rx, bustdccal_rx, bus_mbs_rx, buscts_rx, buscrireg_rx, busCriDatadbgReg_rx : CTRLBUS_RX; - signal ctrlbus_tx, bustools_tx, bustc_tx, bus_master_in , busdebug_tx , bustdccal_tx, buscts_tx, bus_mbs_tx, buscrireg_tx, busCriDatadbgReg_tx : CTRLBUS_TX; + signal ctrlbus_rx, bustools_rx, bustc_rx, bus_master_out, handlerbus_rx, busdebug_rx, bustdc_rx ,bustdccal_rx, bus_mbs_rx, buscts_rx, buscrireg_rx, busCriDatadbgReg_rx : CTRLBUS_RX; + signal ctrlbus_tx, bustools_tx, bustc_tx, bus_master_in , busdebug_tx , bustdc_tx, bustdccal_tx, bus_mbs_tx, buscts_tx, buscrireg_tx, busCriDatadbgReg_tx : CTRLBUS_TX; signal bussci_tx : ctrlbus_tx_array_t(0 to 3); signal bussci_rx : ctrlbus_rx_array_t(0 to 3); @@ -193,7 +194,8 @@ architecture arch of combiner is signal cts_rdo_trg_status_bits_additional : std_logic_vector(32*cts_rdo_additional_ports-1 downto 0) := (others => '0'); signal cts_rdo_additional : readout_tx_array_t(0 to cts_rdo_additional_ports-1); - signal cts_rdo_rx : READOUT_RX; + signal cts_rdo_rx : READOUT_RX; + signal cts_rdo_additional_TDCcal : READOUT_TX; signal cts_addon_triggers_in : std_logic_vector(ADDON_LINE_COUNT-1 downto 0); -- signal cts_addon_activity_i, @@ -225,6 +227,11 @@ architecture arch of combiner is signal mbs_local_trigger_num_in : std_logic_vector(15 downto 0); signal mbs_local_trigger_in : std_logic; + + signal dlm_rx_word : std_logic_vector(7 downto 0); + signal dlm_rx_i : std_logic; + + signal hit_in_i : std_logic_vector(NUM_TDC_CHANNELS-1 downto 1); -- new signal io_dataready_out : std_logic_vector(7 downto 0); @@ -369,8 +376,8 @@ THE_MEDIA_INTERFACE : entity work.med_ecp3_sfp_sync MEDIA_INT2MED => int2med(INTERFACE_NUM), --Sync operation - RX_DLM => open, - RX_DLM_WORD => open, + RX_DLM => dlm_rx_i, + RX_DLM_WORD => dlm_rx_word, TX_DLM => open, TX_DLM_WORD => open, @@ -859,19 +866,26 @@ THE_CRI_INTERFACE : entity work.trb_net16_cri_interface -- MBS --------------------------------------------------------------------------- THE_LOCAL_MBS_CREATE : process - variable cnt : unsigned(16 downto 0) := (others => '0'); + variable cnt : unsigned(17 downto 0) := (others => '0'); begin -- wait until rising_edge(clk_sys); - wait until rising_edge(med2int(INTERFACE_NUM).clk_half); + wait until rising_edge(med2int(INTERFACE_NUM).clk_full); mbs_local_trigger_in <= '0'; if (reset_i = '1') then cnt := 0; mbs_local_trigger_num_in <= (others => '0'); + elsif (dlm_rx_i = '1') then + mbs_local_trigger_in <= '1'; + mbs_local_trigger_num_in <= (others => '0'); + cnt := 20479;--(10240*2)-1; else cnt := cnt + 1; - if (cnt = 10240) then + if (cnt = 20479) then --(10240*2)-1; mbs_local_trigger_in <= '1'; mbs_local_trigger_num_in <= std_logic_vector(unsigned(mbs_local_trigger_num_in) + 1); + end if; + if (cnt = (10240*2)) then + mbs_local_trigger_in <= '1'; cnt := 0; end if; end if; @@ -880,7 +894,7 @@ THE_CRI_INTERFACE : entity work.trb_net16_cri_interface THE_MBS_MASTER : entity work.mbs_master port map ( - CLK => clk_sys, + CLK => med2int(INTERFACE_NUM).clk_half, RESET_IN => reset_i, MBS_CLOCK_OUT => open, @@ -936,11 +950,11 @@ THE_CRI_INTERFACE : entity work.trb_net16_cri_interface --------------------------------------------------------------------------- THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record generic map( - PORT_NUMBER => 12, - PORT_ADDRESSES => (0 => x"d000", 1 => x"d300", 2 => x"b000", 3 => x"b200", 4 => x"b400", 5 => x"b600", 6 => x"e000", - 7 => x"ef00", 8 => x"a000", 9 => x"8300", 10 => x"e100", 11 => x"e400", others => x"0000"), - PORT_ADDR_MASK => (0 => 12, 1 => 1, 2 => 9, 3 => 9, 4 => 9, 5 => 9, 6 => 4, - 7 => 8 , 8 => 11, 9 => 8, 10 => 8, 11 => 2, others => 0), + PORT_NUMBER => 13, + PORT_ADDRESSES => (0 => x"d000", 1 => x"d300", 2 => x"b000", 3 => x"b200", 4 => x"b400", 5 => x"b600", 6 => x"c000", + 7 => x"e000", 8 => x"ef00", 9 => x"a000", 10 => x"8300", 11 => x"e100", 12 => x"e400", others => x"0000"), + PORT_ADDR_MASK => (0 => 12, 1 => 1, 2 => 9, 3 => 9, 4 => 9, 5 => 9, 6 => 12, + 7 => 4, 8 => 8, 9 => 11, 10 => 8, 11 => 8, 12 => 2, others => 0), PORT_MASK_ENABLE => 1 ) port map( @@ -956,24 +970,26 @@ THE_CRI_INTERFACE : entity work.trb_net16_cri_interface BUS_RX(3) => bussci_rx(1), BUS_RX(4) => bussci_rx(2), BUS_RX(5) => bussci_rx(3), - BUS_RX(6) => bustdccal_rx, - BUS_RX(7) => busdebug_rx, - BUS_RX(8) => buscts_rx, - BUS_RX(9) => buscrireg_rx, - BUS_RX(10)=> busCriDatadbgReg_rx, - BUS_RX(11)=> bus_mbs_rx, + BUS_RX(6) => bustdc_rx, + BUS_RX(7) => bustdccal_rx, + BUS_RX(8) => busdebug_rx, + BUS_RX(9) => buscts_rx, + BUS_RX(10) => buscrireg_rx, + BUS_RX(11)=> busCriDatadbgReg_rx, + BUS_RX(12)=> bus_mbs_rx, BUS_TX(0) => bustools_tx, BUS_TX(1) => bustc_tx, BUS_TX(2) => bussci_tx(0), BUS_TX(3) => bussci_tx(1), BUS_TX(4) => bussci_tx(2), BUS_TX(5) => bussci_tx(3), - BUS_TX(6) => bustdccal_tx, - BUS_TX(7) => busdebug_tx, - BUS_TX(8) => buscts_tx, - BUS_TX(9) => buscrireg_tx, - BUS_TX(10)=> busCriDatadbgReg_tx, - BUS_TX(11)=> bus_mbs_tx, + BUS_TX(6) => bustdc_tx, + BUS_TX(7) => bustdccal_tx, + BUS_TX(8) => busdebug_tx, + BUS_TX(9) => buscts_tx, + BUS_TX(10) => buscrireg_tx, + BUS_TX(11)=> busCriDatadbgReg_tx, + BUS_TX(12)=> bus_mbs_tx, STAT_DEBUG => open ); @@ -1106,6 +1122,100 @@ THE_CRI_INTERFACE : entity work.trb_net16_cri_interface monitor_inputs_i(25 downto 24) <= trig_gen_out_i(1 downto 0); +------------------------------------------------------------------------------- +-- TDC +------------------------------------------------------------------------------- + --gen_TDC: if (INCLUDE_TDC = c_YES) generate +-- THE_TDC : entity work.TDC_record +-- generic map ( +-- CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels per module +-- STATUS_REG_NR => 21, -- Number of status regs +-- DEBUG => c_YES, +-- SIMULATION => c_NO) +-- port map ( +-- RESET => reset_i, +-- CLK_TDC => clk_full_osc, +-- CLK_READOUT => clk_sys, -- Clock for the readout +-- REFERENCE_TIME => cts_trigger_out, -- Reference time input +-- HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals +-- HIT_CAL_IN => clk_full_osc,--clk_cal, -- Hits for calibrating the TDC --FIXME: here we need a good cal clock! +-- -- Trigger signals from handler +-- BUSRDO_RX => cts_rdo_rx, +-- BUSRDO_TX => cts_rdo_additional_TDCcal,--_TDCcal +-- -- Slow control bus +-- BUS_RX => bustdc_rx, +-- BUS_TX => bustdc_tx, +-- -- Dubug signals +-- INFO_IN => timer, +-- LOGIC_ANALYSER_OUT => open +-- ); + + + gen_onlineCal: if (INCLUDE_CALIBRATION = c_YES) generate + THE_TDC_CAL : entity work.TDC_Calibration + generic map( + IS_COMBINER => c_NO, + USE_STAT_BITS => c_YES, + USE_DATA_WRITE => c_YES, + USE_DATA_FINISHED => c_YES, + USE_BUSY_RELEASE => c_YES + ) + port map ( + CLK => clk_sys, + RESET => reset_i, + DIN => cts_rdo_additional_TDCcal.data, + DIN_TYPE => x"4", + DIN_info(31 downto 0) => cts_rdo_additional_TDCcal.statusbits, + DIN_info(32) => cts_rdo_additional_TDCcal.busy_release, + DIN_info(33) => cts_rdo_additional_TDCcal.data_write, + DIN_info(34) => cts_rdo_additional_TDCcal.data_finished, + DIN_READY => '1', + DIN_STAT => (others=>'0'), + FPGA_in => timer.network_address, + TRIGG_TYPE => cts_rdo_rx.trg_type, + DOUT => cts_rdo_additional(INCLUDE_ETM).data, + DOUT_info(31 downto 0) => cts_rdo_additional(INCLUDE_ETM).statusbits, + DOUT_info(32) => cts_rdo_additional(INCLUDE_ETM).busy_release, + DOUT_info(33) => cts_rdo_additional(INCLUDE_ETM).data_write, + DOUT_info(34) => cts_rdo_additional(INCLUDE_ETM).data_finished, + DOUT_TYPE => open, + DOUT_READY => open, + DOUT_STAT => open, + BUS_RX => bustdccal_rx, + BUS_TX => bustdccal_tx + ); + end generate; + + gen_no_onlineCal: if (INCLUDE_CALIBRATION = c_NO) generate + + cts_rdo_additional(INCLUDE_ETM).data <= cts_rdo_additional_TDCcal.data; + cts_rdo_additional(INCLUDE_ETM).statusbits <= cts_rdo_additional_TDCcal.statusbits; + cts_rdo_additional(INCLUDE_ETM).busy_release <= cts_rdo_additional_TDCcal.busy_release; + cts_rdo_additional(INCLUDE_ETM).data_write <= cts_rdo_additional_TDCcal.data_write; + cts_rdo_additional(INCLUDE_ETM).data_finished <= cts_rdo_additional_TDCcal.data_finished; + + bustdccal_tx.ack <= '0'; + bustdccal_tx.nack <= '1'; + bustdccal_tx.unknown <= '1'; + + end generate; -- Calib + + -- For single edge measurements + gen_single : if (DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 ) and (INCLUDE_ETM = c_NO) generate + hit_in_i(NUM_TDC_CHANNELS-1 downto 1) <= (others => '0'); + end generate; + + gen_single : if (DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3) and ((ETM_CHOICE = ETM_CHOICE_MBS_VULOM) and (INCLUDE_ETM = c_YES)) generate + hit_in_i(1) <= RJ45_SIG_1;--'0'; + hit_in_i(2) <= RJ45_SIG_1;--async_ext_trig; + hit_in_i(3) <= RJ45_SIG_1;--cts_ext_trigger; + hit_in_i(4) <= RJ45_SIG_1;--'0'; + end generate; + + -- end generate;--TDC + + + --------------------------------------------------------------------------- -- Test Circuits --------------------------------------------------------------------------- diff --git a/combiner_cts/config.vhd b/combiner_cts/config.vhd index c1c2221..55b4d54 100644 --- a/combiner_cts/config.vhd +++ b/combiner_cts/config.vhd @@ -29,7 +29,22 @@ package config is constant INCLUDE_LCD : integer := c_NO; constant INCLUDE_DEBUG_INTERFACE: integer := c_YES; +--TDC + constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement + constant NUM_TDC_CHANNELS : integer range 1 to 65 := 6; -- number of tdc channels per module + constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 4; --the nearest power of two, for convenience reasons + constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 0; --double edge type: 0, 1, 2, 3 + -- 0: single edge only, + -- 1: same channel, + -- 2: alternating channels, + -- 3: same channel with stretcher + constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size: 0, 1, 2, 3, 7 --> change names in constraints file + --ring buffer size: 32,64,96,128,dyn + constant TDC_DATA_FORMAT : integer := 0; + + --input monitor and trigger generation logic + constant INCLUDE_TDC : integer := c_YES; constant INCLUDE_TRIGGER_LOGIC : integer := c_YES; constant INCLUDE_STATISTICS : integer := c_YES; constant TRIG_GEN_INPUT_NUM : integer := 24; @@ -38,6 +53,7 @@ package config is constant INCLUDE_GBE : integer := c_NO; constant INCLUDE_CALIBRATION : integer := c_NO; + constant GEN_BUSY_OUTPUT : integer := c_NO; @@ -52,7 +68,6 @@ package config is -- constant FPGA_SIZE : string := "149KUM"; constant FPGA_TYPE : integer := 3; --3: ECP3, 5: ECP5 - constant INCLUDE_TDC : integer := c_NO; constant INCLUDE_TIMESTAMP_GENERATOR : integer := c_NO; constant INCLUDE_ETM : integer range c_NO to c_YES := c_YES; diff --git a/combiner_cts/config_compile_giessen.pl b/combiner_cts/config_compile_giessen.pl index 63e9a0e..263440d 100644 --- a/combiner_cts/config_compile_giessen.pl +++ b/combiner_cts/config_compile_giessen.pl @@ -4,13 +4,14 @@ lm_license_file_for_par => "7788\@fb07pc-u102325", lattice_path => '/usr/local/diamond/3.11_x64/', synplify_path => '/usr/local/diamond/3.11_x64/synpbase', synplify_command => "synpwrap -fg -options", +#synplify_command => "ssh adrian\@jspc37.x-matter.uni-frankfurt.de \"cd /local/adrian/git/dirich/combiner_cts/; LM_LICENSE_FILE=27020\@jspc29 /d/jspc29/lattice/synplify/O-2018.09-SP1/bin/synplify_premier -batch combiner.prj\"", nodelist_file => '../nodes_lxhadeb07.txt', - +par_options => '../par.p2t', #Include only necessary lpf files pinout_file => 'combiner', #name of pin-out file, if not equal TOPNAME -include_TDC => 0, +include_TDC => 1, include_GBE => 0, #Report settings diff --git a/combiner_cts/tdc_release b/combiner_cts/tdc_release new file mode 120000 index 0000000..6a654d0 --- /dev/null +++ b/combiner_cts/tdc_release @@ -0,0 +1 @@ +../../tdc/releases/tdc_v2.3 \ No newline at end of file -- 2.43.0