From aeaacae43370ce71d6385562a08f5f30b00fff59 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Fri, 18 Jan 2008 14:47:37 +0000 Subject: [PATCH] startup with unplugged cable included, Jan --- trb_net16_med_tlk.vhd | 92 +++++++++++++++++++++++++++---------------- 1 file changed, 59 insertions(+), 33 deletions(-) diff --git a/trb_net16_med_tlk.vhd b/trb_net16_med_tlk.vhd index e45bb5c..62672d4 100644 --- a/trb_net16_med_tlk.vhd +++ b/trb_net16_med_tlk.vhd @@ -96,14 +96,14 @@ architecture trb_net16_med_tlk_arch of trb_net16_med_tlk is signal CLK_Out, CLK_FB_Out, FB_CLK : std_logic; signal buf_STAT : std_logic_vector(33 downto 32); - type tlk_state_t is (RESETTING, WAIT_FOR_RX_LOCK, WAIT_FOR_RX_ALLOW, WAIT_FOR_TX_ALLOW, WORKING); + type tlk_state_t is (RESETTING, WAIT_FOR_RX_LOCK, WAIT_FOR_TX_ALLOW, WORKING); signal current_state, next_state : tlk_state_t; signal next_tx_allow, next_rx_allow : std_logic; - signal counter, next_counter : std_logic_vector(22 downto 0); + signal counter, next_counter : std_logic_vector(27 downto 0); signal next_internal_reset : std_logic; signal buf_MED_ERROR_OUT, next_MED_ERROR_OUT : std_logic_vector(2 downto 0); - - + signal state_bits : std_logic_vector(2 downto 0); + signal counter_reset : std_logic; begin TLK_ENABLE <= not RESET; @@ -173,9 +173,10 @@ begin STAT(31 downto 16) <= reg_RXD; STAT(32) <= buf_STAT(32); STAT(33) <= buf_STAT(33); - STAT(39 downto 36) <= fifo_status_a; - STAT(43 downto 40) <= fifo_status_m; - + STAT(36 downto 34) <= state_bits; + STAT(40 downto 37) <= fifo_status_a; + STAT(44 downto 41) <= fifo_status_m; + STAT(63 downto 45) <= counter(22 downto 4); process(CLK) begin @@ -282,6 +283,8 @@ U1_BUFG: BUFG port map (I => CLK_FB_Out, O => FB_CLK); --fifo_din_m <= "00" & MED_DATA_IN; TLK_TX_ER <= '0'; + TLK_TX_EN <= reg_TX_EN; + TLK_TXD <= reg_TXD; process(CLK) begin @@ -326,81 +329,104 @@ U1_BUFG: BUFG port map (I => CLK_FB_Out, O => FB_CLK); ------------- medium_states : process(current_state, tx_allow, rx_allow, internal_reset, counter, - TLK_RX_ER, TLK_RX_DV, TLK_RXD, buf_MED_ERROR_OUT) + reg_RX_ER, reg_RX_DV, buf_MED_ERROR_OUT) begin next_state <= current_state; next_tx_allow <= tx_allow; next_rx_allow <= rx_allow; next_internal_reset <= internal_reset; next_counter <= counter + 1; + counter_reset <= reg_RX_ER; next_MED_ERROR_OUT <= buf_MED_ERROR_OUT; + case current_state is when RESETTING => next_MED_ERROR_OUT <= ERROR_NC; next_internal_reset <= '1'; - if counter(16) = '1' then - next_counter <= (others => '0'); + counter_reset <= '0'; + if counter(16) = '1' then --16 + counter_reset <= '1'; next_state <= WAIT_FOR_RX_LOCK; next_internal_reset <= '0'; end if; when WAIT_FOR_RX_LOCK => - if TLK_RX_ER = '0' then - next_counter <= (others => '0'); - next_state <= WAIT_FOR_RX_ALLOW; - end if; - when WAIT_FOR_RX_ALLOW => - next_MED_ERROR_OUT <= ERROR_WAIT; - if counter(22) = '1' then + if counter(27) = '1' then + counter_reset <= '1'; next_rx_allow <= '1'; - next_counter <= (others => '0'); next_state <= WAIT_FOR_TX_ALLOW; end if; - if TLK_RX_ER = '1' then - next_counter <= (others => '0'); - end if; +-- when WAIT_FOR_RX_ALLOW => +-- next_MED_ERROR_OUT <= ERROR_WAIT; +-- if counter(22) = '1' then --22 +-- next_rx_allow <= '1'; +-- counter_reset <= '1'; +-- next_state <= WAIT_FOR_TX_ALLOW; +-- end if; when WAIT_FOR_TX_ALLOW => next_MED_ERROR_OUT <= ERROR_WAIT; - if counter(20) = '1' then + if counter(27) = '1' then --20 next_tx_allow <= '1'; next_state <= WORKING; end if; when WORKING => next_MED_ERROR_OUT <= ERROR_OK; - if TLK_RX_ER = '1' then - next_state <= WAIT_FOR_RX_LOCK; - next_MED_ERROR_OUT <= ERROR_WAIT; - next_rx_allow <= '0'; - next_tx_allow <= '0'; - next_counter <= (others => '0'); - end if; + end case; + if reg_RX_ER = '1' and internal_reset = '0' then + next_rx_allow <= '0'; + next_tx_allow <= '0'; + next_state <= WAIT_FOR_RX_LOCK; + next_MED_ERROR_OUT <= ERROR_WAIT; + end if; + end process; + + process(current_state) + begin + case current_state is + when RESETTING => state_bits <= "000"; + when WAIT_FOR_RX_LOCK => state_bits <= "001"; +-- when WAIT_FOR_RX_ALLOW => state_bits <= "010"; + when WAIT_FOR_TX_ALLOW => state_bits <= "011"; + when WORKING => state_bits <= "100"; + when others => state_bits <= "111"; end case; end process; + + states_reg : process(CLK) begin if rising_edge(CLK) then if internal_reset = '1' then - current_state <= RESETTING; tx_allow <= '0'; rx_allow <= '0'; else - current_state <= next_state; tx_allow <= next_tx_allow; rx_allow <= next_rx_allow; end if; end if; end process; + states_reg_counter : process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' or counter_reset = '1' then + counter <= (others => '0'); + else + counter <= next_counter; + end if; + end if; + end process; + states_reg_2 : process(CLK) begin if rising_edge(CLK) then if RESET = '1' then + current_state <= RESETTING; internal_reset <= '1'; - counter <= (others => '0'); buf_MED_ERROR_OUT <= ERROR_NC; else + current_state <= next_state; internal_reset <= next_internal_reset; - counter <= next_counter; buf_MED_ERROR_OUT <= next_MED_ERROR_OUT; end if; end if; -- 2.43.0