From afe073cf1a2c0132e5fa4a26a926a60ef52f4624 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Mon, 20 May 2019 16:45:25 +0200 Subject: [PATCH] add logic for RPC test signals to TDC --- tdctemplate/trb3sc_tdctemplate.prj | 1 + tdctemplate/trb3sc_tdctemplate.vhd | 58 ++++++++++++++++++++++++++---- 2 files changed, 52 insertions(+), 7 deletions(-) diff --git a/tdctemplate/trb3sc_tdctemplate.prj b/tdctemplate/trb3sc_tdctemplate.prj index cb9ca7b..ff3bb8d 100644 --- a/tdctemplate/trb3sc_tdctemplate.prj +++ b/tdctemplate/trb3sc_tdctemplate.prj @@ -171,6 +171,7 @@ add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd" add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd" add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd" add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd" +add_file -vhdl -lib work "../../trb3sc/code/fee_signals.vhd" #SlowControl files add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" diff --git a/tdctemplate/trb3sc_tdctemplate.vhd b/tdctemplate/trb3sc_tdctemplate.vhd index 6b8b743..d86fba6 100644 --- a/tdctemplate/trb3sc_tdctemplate.vhd +++ b/tdctemplate/trb3sc_tdctemplate.vhd @@ -37,10 +37,13 @@ entity trb3sc_tdctemplate is DAC_OUT_CS : out std_logic_vector(6 downto 1); DAC_IN_SDI : in std_logic_vector(6 downto 1); + TEST_SIG_OUT : out std_logic_vector(7 downto 0); + FEETEMP : inout std_logic_vector(3 downto 0); + --Additional IO HDR_IO : inout std_logic_vector(10 downto 1); RJ_IO : inout std_logic_vector(3 downto 0); - SPARE_IN : in std_logic_vector(1 downto 0); +-- SPARE_IN : in std_logic_vector(1 downto 0); --LED LED_GREEN : out std_logic; @@ -126,8 +129,8 @@ architecture trb3sc_arch of trb3sc_tdctemplate is signal readout_rx : READOUT_RX; signal readout_tx : readout_tx_array_t(0 to 0); - signal ctrlbus_rx, bussci_rx, bustools_rx, bustc_rx, bustdc_rx, bus_master_out : CTRLBUS_RX; - signal ctrlbus_tx, bussci_tx, bustools_tx, bustc_tx, bustdc_tx, bus_master_in : CTRLBUS_TX; + signal ctrlbus_rx, bussci_rx, bustools_rx, bustc_rx, bustdc_rx, bus_master_out, busfee_rx : CTRLBUS_RX; + signal ctrlbus_tx, bussci_tx, bustools_tx, bustc_tx, bustdc_tx, bus_master_in, busfee_tx : CTRLBUS_TX; signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); @@ -306,9 +309,9 @@ end generate; --------------------------------------------------------------------------- THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record generic map( - PORT_NUMBER => 4, - PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"c000", others => x"0000"), - PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 12, others => 0), + PORT_NUMBER => 5, + PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"c000", 4 => x"b000", others => x"0000"), + PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 12, 4 => 5, others => 0), PORT_MASK_ENABLE => 1 ) port map( @@ -322,10 +325,12 @@ end generate; BUS_RX(1) => bussci_rx, --SCI Serdes BUS_RX(2) => bustc_rx, --Clock switch BUS_RX(3) => bustdc_rx, --TDC config + BUS_RX(4) => busfee_rx, --FEE test, temperature BUS_TX(0) => bustools_tx, BUS_TX(1) => bussci_tx, BUS_TX(2) => bustc_tx, BUS_TX(3) => bustdc_tx, + BUS_TX(4) => busfee_tx, STAT_DEBUG => open ); @@ -435,8 +440,47 @@ gen_kel : if PINOUT = 2 generate DAC_OUT_SDO(6 downto 5) <= spi_mosi(5 downto 4); end generate; +gen_ada : if PINOUT = 3 generate + inputs(47 downto 0) <= INP(47 downto 0); + + spi_miso(1 downto 0) <= DAC_IN_SDI(2 downto 1); + DAC_OUT_SCK(2 downto 1) <= spi_clk(1 downto 0); + DAC_OUT_CS(2 downto 1) <= spi_cs(1 downto 0); + DAC_OUT_SDO(2 downto 1) <= spi_mosi(1 downto 0); + + + spi_miso(5 downto 4) <= DAC_IN_SDI(6 downto 5); + DAC_OUT_SCK(6 downto 5) <= spi_clk(5 downto 4); + DAC_OUT_CS(6 downto 5) <= spi_cs(5 downto 4); + DAC_OUT_SDO(6 downto 5) <= spi_mosi(5 downto 4); + +end generate; + + +--------------------------------------------------------------------------- +-- FEE test signals and temperature sensors +--------------------------------------------------------------------------- +gen_fee_test : if PINOUT = 3 generate + THE_FEE_TEST : entity work.fee_signals + port map( + CLK => clk_sys, + RESET => reset_i, + BUS_RX => busfee_rx, + BUS_TX => busfee_tx, + + TEST_SIG_OUT => TEST_SIG_OUT, + FEETEMP => FEETEMP + ); +end generate; + +gen_no_fee_test : if PINOUT /= 3 generate + busfee_tx.unknown <= busfee_rx.write or busfee_rx.read; + busfee_tx.ack <= '0'; + busfee_tx.nack <= '0'; +end generate; + --------------------------------------------------------------------------- -- LCD Data to display --------------------------------------------------------------------------- @@ -527,7 +571,7 @@ end generate; end generate; gen_montrg_inputs_normal : if TRIG_GEN_FAST_CHANNELS = c_NO generate - monitor_inputs_i <= inputs(MONITOR_INPUT_NUM-1 downto 0); + monitor_inputs_i <= trig_gen_out_i & inputs(MONITOR_INPUT_NUM-TRIG_GEN_OUTPUT_NUM -1 downto 0); trigger_inputs_i <= inputs(TRIG_GEN_INPUT_NUM-1 downto 0); end generate; -- 2.43.0