From b06af2d190a6519e6e2422da2b8c979940c37c4b Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Tue, 27 Nov 2007 14:37:01 +0000 Subject: [PATCH] created regIO, Jan --- trb_net16_hub_base.vhd | 14 +++--- trb_net16_hub_control.vhd | 46 ++++++++++++++++++ trb_net16_regIO.vhd | 100 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 152 insertions(+), 8 deletions(-) create mode 100644 trb_net16_hub_control.vhd create mode 100644 trb_net16_regIO.vhd diff --git a/trb_net16_hub_base.vhd b/trb_net16_hub_base.vhd index f3828e2..682eb2f 100644 --- a/trb_net16_hub_base.vhd +++ b/trb_net16_hub_base.vhd @@ -59,8 +59,6 @@ entity trb_net16_hub_base is API_CHANNELS : hub_api_config_t := (3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3); --channel, each api is connected to API_TYPE : hub_api_config_t := (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0); - API_INIT_DEPTH : hub_api_config_t := (1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1); - API_REPLY_DEPTH : hub_api_config_t := (1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1); API_FIFO_TO_INT_DEPTH : hub_api_config_t := (1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1); API_FIFO_TO_APL_DEPTH : hub_api_config_t := (1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1); --trigger reading interfaces @@ -436,8 +434,8 @@ begin begin IOBUF: trb_net16_iobuf generic map ( - INIT_DEPTH => calc_depth(i,MII_INIT_DEPTH, API_INIT_DEPTH, MII_NUMBER, API_NUMBER, MUX_WIDTH, HUB_CTRL_DEPTH), - REPLY_DEPTH => calc_depth(i,MII_REPLY_DEPTH, API_REPLY_DEPTH, MII_NUMBER, API_NUMBER, MUX_WIDTH, HUB_CTRL_DEPTH) + INIT_DEPTH => calc_depth(i,MII_INIT_DEPTH, API_FIFO_TO_APL_DEPTH, MII_NUMBER, API_NUMBER, MUX_WIDTH, HUB_CTRL_DEPTH), + REPLY_DEPTH => calc_depth(i,MII_REPLY_DEPTH, API_FIFO_TO_INT_DEPTH, MII_NUMBER, API_NUMBER, MUX_WIDTH, HUB_CTRL_DEPTH) ) port map ( -- Misc @@ -569,8 +567,8 @@ begin PAS_API : trb_net16_api_base generic map( API_TYPE => API_TYPE(aploffset), - FIFO_TO_INT_DEPTH => API_INIT_DEPTH(aploffset), - FIFO_TO_APL_DEPTH => API_REPLY_DEPTH(aploffset), + FIFO_TO_INT_DEPTH => API_FIFO_TO_INT_DEPTH(aploffset), + FIFO_TO_APL_DEPTH => API_FIFO_TO_APL_DEPTH(aploffset), FIFO_TERM_BUFFER_DEPTH => 0 ) port map( @@ -625,8 +623,8 @@ begin ACT_API : trb_net16_api_base generic map( API_TYPE => API_TYPE(aploffset), - FIFO_TO_INT_DEPTH => API_INIT_DEPTH(aploffset), - FIFO_TO_APL_DEPTH => API_REPLY_DEPTH(aploffset), + FIFO_TO_INT_DEPTH => API_FIFO_TO_INT_DEPTH(aploffset), + FIFO_TO_APL_DEPTH => API_FIFO_TO_APL_DEPTH(aploffset), FIFO_TERM_BUFFER_DEPTH => 0 ) port map( diff --git a/trb_net16_hub_control.vhd b/trb_net16_hub_control.vhd new file mode 100644 index 0000000..dcfc7aa --- /dev/null +++ b/trb_net16_hub_control.vhd @@ -0,0 +1,46 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.std_logic_ARITH.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +use work.trb_net_std.all; + + +entity trb_net16_hub_control is + generic ( + MY_ADDRESS : std_logic_vector(15 downto 0) + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- APL Transmitter port + APL_DATA_OUT: out std_logic_vector (15 downto 0); + APL_PACKET_NUM_OUT: out std_logic_vector (1 downto 0); + APL_WRITE_OUT: out std_logic; + APL_FIFO_FULL_IN: in std_logic; + APL_SHORT_TRANSFER_OUT: out std_logic; + APL_DTYPE_OUT: out std_logic_vector (3 downto 0); + APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0); + APL_SEND_OUT: out std_logic; + APL_TARGET_ADDRESS_OUT: out std_logic_vector (15 downto 0); + -- Receiver port + APL_DATA_IN: in std_logic_vector (15 downto 0); + APL_PACKET_NUM_IN:in std_logic_vector (1 downto 0); + APL_TYP_IN: in std_logic_vector (2 downto 0); + APL_DATAREADY_IN: in std_logic; + APL_READ_OUT: out std_logic; + -- APL Control port + APL_RUN_IN: in std_logic; + APL_MY_ADDRESS_OUT: in std_logic_vector (15 downto 0); + APL_SEQNR_IN: in std_logic_vector (7 downto 0) + ); +end entity; + +architecture trb_net16_hub_control_arch of trb_net16_hub_control is + +begin + + +end architecture; \ No newline at end of file diff --git a/trb_net16_regIO.vhd b/trb_net16_regIO.vhd new file mode 100644 index 0000000..ac0dae3 --- /dev/null +++ b/trb_net16_regIO.vhd @@ -0,0 +1,100 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.std_logic_ARITH.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; +use work.trb_net_std.all; + + +--REGISTERS within 0..REGISTER_COUNT are handled internally, while all other r/w requests are offered to the parent +--REGISTERS with Bit 7 set are writeable (CTRL), with Bit 7 unset are readonly (STAT) from outside and vice versa from inside + +entity trb_net16_regIO is + generic ( + MY_ADDRESS : std_logic_vector(15 downto 0); + REGISTER_WIDTH : integer range 32 to 32 := 32; + ADDRESS_WIDTH : integer range 8 to 16 := 16; + REGISTER_COUNT : integer range 255 to 255 := 255; + REGISTER_WRITEABLE : std_logic_vector(255 downto 0) := "1111111111111111" & "1111111111111111" & + "1111111111111111" & "1111111111111111" & + "1111111111111111" & "1111111111111111" & + "1111111111111111" & "1111111111111111" & + "0000000000000000" & "0000000000000000" & + "0000000000000000" & "0000000000000000" & + "0000000000000000" & "0000000000000000" & + "0000000000000000" & "0000000000000000"; + --no data / address out? + NO_DAT_PORT : std_logic := '0'; + --no APL out? + NO_APL_PORT : std_logic := '0'; + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + -- Port to API + API_DATA_OUT: out std_logic_vector (15 downto 0); + API_PACKET_NUM_OUT: out std_logic_vector (1 downto 0); + API_WRITE_OUT: out std_logic; + API_FIFO_FULL_IN: in std_logic; + API_SHORT_TRANSFER_OUT: out std_logic; + API_DTYPE_OUT: out std_logic_vector (3 downto 0); + API_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0); + API_SEND_OUT: out std_logic; + API_TARGET_ADDRESS_OUT: out std_logic_vector (15 downto 0); + -- Receiver port + API_DATA_IN: in std_logic_vector (15 downto 0); + API_PACKET_NUM_IN:in std_logic_vector (1 downto 0); + API_TYP_IN: in std_logic_vector (2 downto 0); + API_DATAREADY_IN: in std_logic; + API_READ_OUT: out std_logic; + -- APL Control port + API_RUN_IN: in std_logic; + API_MY_ADDRESS_OUT: in std_logic_vector (15 downto 0); + API_SEQNR_IN: in std_logic_vector (7 downto 0) + + --Register in / outside + REGISTERS_IN : in std_logic_vector(REGISTER_WIDTH*REGISTER_COUNT-1 downto 0); + REGISTERS_OUT : out std_logic_vector(REGISTER_WIDTH*REGISTER_COUNT-1 downto 0); + + --following ports only used when no internal register is accessed + DAT_ADDR_OUT : out std_logic_vector(ADDRESS_WIDTH-1 downto 0); + DAT_READ_ENABLE_OUT : out std_logic; + DAT_WRITE_ENABLE_OUT: out std_logic; + --Data output is only used when writing + DAT_DATA_OUT : out std_logic_vector(REGISTER_WIDTH-1 downto 0); + --Data input can only be used as reaction on read or write access. write operation should return data + --if successful + DAT_DATA_IN : in std_logic_vector(REGISTER_WIDTH-1 downto 0); + DAT_DATAREADY_IN : in std_logic; + + --all other dtype beside register read/write are directly passed to APL + -- APL Transmitter port + APL_DATA_IN : in std_logic_vector (15 downto 0); + APL_PACKET_NUM_IN : in std_logic_vector (1 downto 0); + APL_WRITE_IN : in std_logic; + APL_FIFO_FULL_OUT : out std_logic; + APL_SHORT_TRANSFER_IN : in std_logic; + APL_DTYPE_IN : in std_logic_vector (3 downto 0); + APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); + APL_SEND_IN : in std_logic; + APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0); + -- Receiver port + APL_DATA_OUT : out std_logic_vector (15 downto 0); + APL_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); + APL_TYP_OUT : out std_logic_vector (2 downto 0); + APL_DATAREADY_OUT : out std_logic; + APL_READ_IN : in std_logic; + -- APL Control port + APL_RUN_OUT : out std_logic; + APL_SEQNR_OUT : out std_logic_vector (7 downto 0) + ); +end entity; + +architecture trb_net16_regIO_arch of trb_net16_regIO is + +begin + +end architecture; + -- 2.43.0