From b0acd200dadc61ad49a062ef71e2b11a695d702f Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Wed, 24 Jan 2007 14:59:37 +0000 Subject: [PATCH] arbiter ready, Ingo --- testbench/in_priority_arbiter.txt | 17 +++ testbench/priority_arbiter_settings.sav | 14 +++ testbench/priority_arbiter_testsim.tcl | 4 + .../trb_net_priority_arbiter_testbench.vhd | 107 ++++++++++++++++++ ...trb_net_priority_arbiter_testbench_beh.prj | 4 + trb_net_io_multiplexer.vhd | 2 +- trb_net_priority_arbiter.vhd | 104 ++++++++++++++--- trb_net_priority_encoder.vhd | 8 +- 8 files changed, 238 insertions(+), 22 deletions(-) create mode 100644 testbench/in_priority_arbiter.txt create mode 100644 testbench/priority_arbiter_settings.sav create mode 100644 testbench/priority_arbiter_testsim.tcl create mode 100644 testbench/trb_net_priority_arbiter_testbench.vhd create mode 100644 testbench/trb_net_priority_arbiter_testbench_beh.prj diff --git a/testbench/in_priority_arbiter.txt b/testbench/in_priority_arbiter.txt new file mode 100644 index 0000000..f4eb0b9 --- /dev/null +++ b/testbench/in_priority_arbiter.txt @@ -0,0 +1,17 @@ +00000000:0 +00000000:0 +00000000:0 +00000010:1 +00000100:1 +00001010:1 +01010000:1 +00100100:1 +00111100:1 +11111111:1 +11111111:1 +11111111:1 +11111111:1 +11111111:1 +11111111:1 +11111111:1 +00000000:1 diff --git a/testbench/priority_arbiter_settings.sav b/testbench/priority_arbiter_settings.sav new file mode 100644 index 0000000..9e40f8d --- /dev/null +++ b/testbench/priority_arbiter_settings.sav @@ -0,0 +1,14 @@ +[size] 1272 937 +[pos] -1 -1 +*-26.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +@28 +#input_in[7:0] trb_net_priority_arbiter_testbench.UUT.input_in[7] trb_net_priority_arbiter_testbench.UUT.input_in[6] trb_net_priority_arbiter_testbench.UUT.input_in[5] trb_net_priority_arbiter_testbench.UUT.input_in[4] trb_net_priority_arbiter_testbench.UUT.input_in[3] trb_net_priority_arbiter_testbench.UUT.input_in[2] trb_net_priority_arbiter_testbench.UUT.input_in[1] trb_net_priority_arbiter_testbench.UUT.input_in[0] +#next_fixed_pattern[7:0] trb_net_priority_arbiter_testbench.UUT.next_fixed_pattern[7] trb_net_priority_arbiter_testbench.UUT.next_fixed_pattern[6] trb_net_priority_arbiter_testbench.UUT.next_fixed_pattern[5] trb_net_priority_arbiter_testbench.UUT.next_fixed_pattern[4] trb_net_priority_arbiter_testbench.UUT.next_fixed_pattern[3] trb_net_priority_arbiter_testbench.UUT.next_fixed_pattern[2] trb_net_priority_arbiter_testbench.UUT.next_fixed_pattern[1] trb_net_priority_arbiter_testbench.UUT.next_fixed_pattern[0] +@22 +#current_rr_mask[7:0] trb_net_priority_arbiter_testbench.UUT.current_rr_mask[7] trb_net_priority_arbiter_testbench.UUT.current_rr_mask[6] trb_net_priority_arbiter_testbench.UUT.current_rr_mask[5] trb_net_priority_arbiter_testbench.UUT.current_rr_mask[4] trb_net_priority_arbiter_testbench.UUT.current_rr_mask[3] trb_net_priority_arbiter_testbench.UUT.current_rr_mask[2] trb_net_priority_arbiter_testbench.UUT.current_rr_mask[1] trb_net_priority_arbiter_testbench.UUT.current_rr_mask[0] +@28 +trb_net_priority_arbiter_testbench.UUT.use_rr +#current_p1_pattern[7:0] trb_net_priority_arbiter_testbench.UUT.current_p1_pattern[7] trb_net_priority_arbiter_testbench.UUT.current_p1_pattern[6] trb_net_priority_arbiter_testbench.UUT.current_p1_pattern[5] trb_net_priority_arbiter_testbench.UUT.current_p1_pattern[4] trb_net_priority_arbiter_testbench.UUT.current_p1_pattern[3] trb_net_priority_arbiter_testbench.UUT.current_p1_pattern[2] trb_net_priority_arbiter_testbench.UUT.current_p1_pattern[1] trb_net_priority_arbiter_testbench.UUT.current_p1_pattern[0] +#current_p2_pattern[7:0] trb_net_priority_arbiter_testbench.UUT.current_p2_pattern[7] trb_net_priority_arbiter_testbench.UUT.current_p2_pattern[6] trb_net_priority_arbiter_testbench.UUT.current_p2_pattern[5] trb_net_priority_arbiter_testbench.UUT.current_p2_pattern[4] trb_net_priority_arbiter_testbench.UUT.current_p2_pattern[3] trb_net_priority_arbiter_testbench.UUT.current_p2_pattern[2] trb_net_priority_arbiter_testbench.UUT.current_p2_pattern[1] trb_net_priority_arbiter_testbench.UUT.current_p2_pattern[0] +#next_rr_pattern[7:0] trb_net_priority_arbiter_testbench.UUT.next_rr_pattern[7] trb_net_priority_arbiter_testbench.UUT.next_rr_pattern[6] trb_net_priority_arbiter_testbench.UUT.next_rr_pattern[5] trb_net_priority_arbiter_testbench.UUT.next_rr_pattern[4] trb_net_priority_arbiter_testbench.UUT.next_rr_pattern[3] trb_net_priority_arbiter_testbench.UUT.next_rr_pattern[2] trb_net_priority_arbiter_testbench.UUT.next_rr_pattern[1] trb_net_priority_arbiter_testbench.UUT.next_rr_pattern[0] +#result_out[7:0] trb_net_priority_arbiter_testbench.UUT.result_out[7] trb_net_priority_arbiter_testbench.UUT.result_out[6] trb_net_priority_arbiter_testbench.UUT.result_out[5] trb_net_priority_arbiter_testbench.UUT.result_out[4] trb_net_priority_arbiter_testbench.UUT.result_out[3] trb_net_priority_arbiter_testbench.UUT.result_out[2] trb_net_priority_arbiter_testbench.UUT.result_out[1] trb_net_priority_arbiter_testbench.UUT.result_out[0] diff --git a/testbench/priority_arbiter_testsim.tcl b/testbench/priority_arbiter_testsim.tcl new file mode 100644 index 0000000..f9eb6ef --- /dev/null +++ b/testbench/priority_arbiter_testsim.tcl @@ -0,0 +1,4 @@ +vcd dumpfile vcdfile.vcd +vcd dumpvars -m /UUT/ +run 1000 ns +quit \ No newline at end of file diff --git a/testbench/trb_net_priority_arbiter_testbench.vhd b/testbench/trb_net_priority_arbiter_testbench.vhd new file mode 100644 index 0000000..c83339f --- /dev/null +++ b/testbench/trb_net_priority_arbiter_testbench.vhd @@ -0,0 +1,107 @@ +library ieee; + +use ieee.std_logic_1164.all; + +USE ieee.std_logic_signed.ALL; + +USE ieee.std_logic_arith.ALL; + +USE std.textio.ALL; +USE ieee.std_logic_textio.ALL; + +entity trb_net_priority_arbiter_testbench is + +end trb_net_priority_arbiter_testbench; + +architecture trb_net_priority_arbiter_testbench_arch of trb_net_priority_arbiter_testbench is + + signal clk : std_logic := '0'; + signal reset : std_logic := '1'; + + signal read_type : std_logic_vector(2 downto 0) := (others => '0'); + signal read_f2 : std_logic_vector(3 downto 0) := (others => '0'); + signal read_f1 : std_logic_vector(7 downto 0) := (others => '0'); + signal rol_mask : std_logic := '0'; + signal ctrl: std_logic_vector(31 downto 0) := (others => '0'); + component trb_net_priority_arbiter is + + generic (WIDTH : integer := 32); + + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + INPUT_IN : in STD_LOGIC_VECTOR (WIDTH-1 downto 0); + RESULT_OUT: out STD_LOGIC_VECTOR (WIDTH-1 downto 0); + + CTRL: in STD_LOGIC_VECTOR (31 downto 0) + ); +END component; + + +begin + + UUT: trb_net_priority_arbiter + generic map ( + WIDTH => 8 + ) + port map ( + CLK =>clk, + RESET => reset, + CLK_EN => '1', + + INPUT_IN => read_f1, + + CTRL => ctrl + ); + + clk <= not clk after 10ns; + ctrl(9) <= rol_mask; + + DO_RESET : process + begin + reset <= '1'; + wait for 30ns; + reset <= '0'; +-- ctrl(8 downto 0) <= "100000000"; --only fixed +-- ctrl(8 downto 0) <= "111111111"; --only rr + ctrl(8 downto 0) <= "101010101"; --mixed + wait for 20ns; + ctrl(8 downto 0) <= "000000000"; + wait; + end process DO_RESET; + + STIMULI: process (clk) + file protokoll : text open read_mode is "in_priority_arbiter.txt"; + variable myoutline : line; + variable leer : character; + variable var1, var2 : std_logic; + variable varx1 : std_logic_vector(2 downto 0); + variable varx2, varx3 : std_logic_vector(7 downto 0); + begin + if falling_edge(CLK) then + if (not endfile(protokoll)) then + readline(protokoll,myoutline); + + read(myoutline,varx2); + read_f1 <= varx2; + read(myoutline,leer); + + read(myoutline,var1); + rol_mask <= var1; + + end if; + end if; + end process STIMULI; + + +end trb_net_priority_arbiter_testbench_arch; + +-- fuse -prj trb_net_priority_arbiter_testbench_beh.prj -top trb_net_priority_arbiter_testbench -o trb_net_priority_arbiter_testbench + +-- trb_net_priority_arbiter_testbench -tclbatch priority_arbiter_testsim.tcl + +-- isimwave isimwavedata.xwv + diff --git a/testbench/trb_net_priority_arbiter_testbench_beh.prj b/testbench/trb_net_priority_arbiter_testbench_beh.prj new file mode 100644 index 0000000..e7fa260 --- /dev/null +++ b/testbench/trb_net_priority_arbiter_testbench_beh.prj @@ -0,0 +1,4 @@ +vhdl work "../trb_net_std.vhd" +vhdl work "../trb_net_priority_encoder.vhd" +vhdl work "../trb_net_priority_arbiter.vhd" +vhdl work "trb_net_priority_arbiter_testbench.vhd" diff --git a/trb_net_io_multiplexer.vhd b/trb_net_io_multiplexer.vhd index 1ed7330..d696579 100644 --- a/trb_net_io_multiplexer.vhd +++ b/trb_net_io_multiplexer.vhd @@ -80,7 +80,7 @@ architecture trb_net_io_multiplexer_arch of trb_net_io_multiplexer is ------------------------------------------------------------------------------ -- the simpler part is the demux - demux_read <= (current_demux_dr and INT_READ_IN) + demux_read <= (current_demux_dr and INT_READ_IN); comb_demux : process (current_demux_empty, demux_read, current_demux_buffer, current_demux_READ, MED_DATAREADY_IN, current_demux_dr, diff --git a/trb_net_priority_arbiter.vhd b/trb_net_priority_arbiter.vhd index 51a6c8f..cbfbeb2 100755 --- a/trb_net_priority_arbiter.vhd +++ b/trb_net_priority_arbiter.vhd @@ -7,11 +7,18 @@ use work.trb_net_std.all; entity trb_net_priority_arbiter is - generic (WIDTH : integer := 8); + generic (WIDTH : integer := 32); - port( + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + INPUT_IN : in STD_LOGIC_VECTOR (WIDTH-1 downto 0); - RESULT_OUT: out STD_LOGIC_VECTOR (WIDTH-1 downto 0) + RESULT_OUT: out STD_LOGIC_VECTOR (WIDTH-1 downto 0); + + CTRL: in STD_LOGIC_VECTOR (31 downto 0) ); END trb_net_priority_arbiter; @@ -29,10 +36,17 @@ architecture trb_net_priority_arbiter_arch of trb_net_priority_arbiter is END component; signal next_fixed_pattern: STD_LOGIC_VECTOR (WIDTH-1 downto 0); - signal next_rr_pattern, current_rr_pattern: STD_LOGIC_VECTOR (WIDTH-1 downto 0); + signal next_rr_pattern: STD_LOGIC_VECTOR (WIDTH-1 downto 0); signal next_p1_pattern, current_p1_pattern: STD_LOGIC_VECTOR (WIDTH-1 downto 0); signal next_p2_pattern, current_p2_pattern: STD_LOGIC_VECTOR (WIDTH-1 downto 0); signal sampled_rr_pattern1, sampled_rr_pattern2: STD_LOGIC_VECTOR (WIDTH-1 downto 0); + signal proposed_rr_pattern1, proposed_rr_pattern2: STD_LOGIC_VECTOR (WIDTH-1 downto 0); + signal leading_rr_pattern1, leading_rr_pattern2: STD_LOGIC_VECTOR (WIDTH-1 downto 0); + signal next_final_pattern, current_final_pattern: STD_LOGIC_VECTOR (WIDTH-1 downto 0); + signal current_rr_mask, next_rr_mask: STD_LOGIC_VECTOR (7 downto 0); + + signal use_rr: STD_LOGIC; + begin @@ -60,7 +74,7 @@ architecture trb_net_priority_arbiter_arch of trb_net_priority_arbiter is port map( INPUT_IN => sampled_rr_pattern1, RESULT_OUT => proposed_rr_pattern1, - PATTERN_OUT => leading_rr_pattern2 + PATTERN_OUT => leading_rr_pattern1 ); ENC3: trb_net_priority_encoder @@ -73,27 +87,83 @@ architecture trb_net_priority_arbiter_arch of trb_net_priority_arbiter is sampled_rr_pattern1 <= INPUT_IN and current_p1_pattern; sampled_rr_pattern2 <= INPUT_IN and current_p2_pattern; - - comb_rr : process(CLK) + + use_rr <= current_rr_mask(0) and CTRL(9); --rol_mask is on + RESULT_OUT <= current_final_pattern; + + comb_rr : process(current_p1_pattern, current_p2_pattern,use_rr, + sampled_rr_pattern1, sampled_rr_pattern2, proposed_rr_pattern1, + proposed_rr_pattern2, leading_rr_pattern1, leading_rr_pattern2, + current_rr_mask, CTRL, next_fixed_pattern, next_rr_pattern) begin - next_rr_pattern <= current_rr_pattern; + next_rr_pattern <= (others => '0'); next_p1_pattern <= current_p1_pattern; next_p2_pattern <= current_p2_pattern; - + next_rr_mask <= current_rr_mask; + next_final_pattern <= (others => '0'); + if use_rr = '1' then - -- without using the rr, nothing will happen - if or_all(sampled_rr_pattern1) then + -- when _using_ the rr, overwrite the current pattern with a new one ( + -- this means do the "round" of the robin + if or_all(sampled_rr_pattern1) = '1' then -- pattern 1 has higher priority - next_rr_pattern <= proposed_rr_pattern; - next_p1_pattern <= leading_rr_pattern1 xor proposed_rr_pattern; - next_p2_pattern <= not leading_rr_pattern1; - elsif or_all(sampled_rr_pattern2) then - else + next_p1_pattern <= leading_rr_pattern1 xor proposed_rr_pattern1; + next_p2_pattern <= not leading_rr_pattern1 or proposed_rr_pattern1; + elsif or_all(sampled_rr_pattern2) = '1' then + next_p1_pattern <= leading_rr_pattern2 xor proposed_rr_pattern2; + next_p2_pattern <= not leading_rr_pattern2 or proposed_rr_pattern2; end if; end if; + + if or_all(sampled_rr_pattern1) = '1' then + next_rr_pattern <= proposed_rr_pattern1; + elsif or_all(sampled_rr_pattern2) = '1' then + next_rr_pattern <= proposed_rr_pattern2; + end if; + + if (CTRL(9) = '1') and (CTRL(8) = '0') then -- rol + next_rr_mask(6 downto 0) <= current_rr_mask(7 downto 1); + next_rr_mask(7) <= current_rr_mask(0); + elsif (CTRL(8) = '1') then --overwrite + next_rr_mask(7 downto 0) <= CTRL(7 downto 0); + end if; + + -- finally make the pattern + if current_rr_mask(0) = '0' then + next_final_pattern <= next_fixed_pattern; + else + next_final_pattern <= next_rr_pattern; + end if; end process; + + sync_rr : process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + current_p1_pattern <= (others => '1'); + current_p2_pattern <= (others => '0'); + current_rr_mask <= (others => '0'); + current_final_pattern <= (others => '0'); + current_rr_mask <= (others => '0'); + elsif CLK_EN = '1' then + current_p1_pattern <= next_p1_pattern; + current_p2_pattern <= next_p2_pattern; + current_rr_mask <= next_rr_mask; + current_final_pattern <= next_final_pattern; + current_rr_mask <= next_rr_mask; + else + current_p1_pattern <= current_p1_pattern; + current_p2_pattern <= current_p2_pattern; + current_rr_mask <= current_rr_mask; + current_final_pattern <= current_final_pattern; + current_rr_mask <= current_rr_mask; + end if; + end if; + end process; + + -end trb_net_riority_arbiter_arch; +end trb_net_priority_arbiter_arch; diff --git a/trb_net_priority_encoder.vhd b/trb_net_priority_encoder.vhd index dfe6349..4487760 100755 --- a/trb_net_priority_encoder.vhd +++ b/trb_net_priority_encoder.vhd @@ -7,7 +7,7 @@ use work.trb_net_std.all; entity trb_net_priority_encoder is - generic (WIDTH : integer := 8); + generic (WIDTH : integer := 4); port( INPUT_IN : in STD_LOGIC_VECTOR (WIDTH-1 downto 0); @@ -30,11 +30,11 @@ architecture trb_net_priority_encoder_arch of trb_net_priority_encoder is leading_pattern(0) <= INPUT_IN(0); end generate; G3: if i > 0 generate - comb : process (INPUT_IN) + comb : process (INPUT_IN, leading_pattern) begin fixed_pattern(i) <= '0'; leading_pattern(i) <= leading_pattern(i-1); - if INPUT_IN = '1' and leading_pattern(i-1) = '0' then + if (INPUT_IN(i) = '1') and (leading_pattern(i-1) = '0') then fixed_pattern(i) <= '1'; leading_pattern(i) <= '1'; end if; @@ -46,5 +46,5 @@ architecture trb_net_priority_encoder_arch of trb_net_priority_encoder is PATTERN_OUT <= leading_pattern; -end trb_net_riority_encoder_arch; +end trb_net_priority_encoder_arch; -- 2.43.0