From b19f989d8096a44eb79d444a20800fd92f5ab9da Mon Sep 17 00:00:00 2001
From: hadaq <hadaq>
Date: Tue, 17 Jan 2012 10:01:31 +0000
Subject: [PATCH] new file

---
 cts_fpga1_test_set_width.vhd | 102 +++++++++++++++++++++++++++++++++++
 1 file changed, 102 insertions(+)
 create mode 100644 cts_fpga1_test_set_width.vhd

diff --git a/cts_fpga1_test_set_width.vhd b/cts_fpga1_test_set_width.vhd
new file mode 100644
index 0000000..a684eec
--- /dev/null
+++ b/cts_fpga1_test_set_width.vhd
@@ -0,0 +1,102 @@
+library IEEE;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.all;
+use ieee.std_logic_arith.all;
+
+entity cts_fpga1_test_set_width is
+
+   port (
+    RESET                      : in  std_logic;
+    CLK                        : in  std_logic;
+    SIGNAL_WIDTH               : in  std_logic_vector(7 downto 0);
+    SIGNAL_IN                  : in  std_logic;
+    SIGNAL_OUT                  : out  std_logic
+  );
+end cts_fpga1_test_set_width;
+
+architecture cts_fpga1_test_set_width of cts_fpga1_test_set_width is
+  component up_down_counter
+    generic (
+      NUMBER_OF_BITS : positive);
+    port (
+      CLK       : in  std_logic;
+      RESET     : in  std_logic;
+      COUNT_OUT : out std_logic_vector(NUMBER_OF_BITS-1 downto 0);
+      UP_IN     : in  std_logic;
+      DOWN_IN   : in  std_logic);
+  end component;
+  
+  type WIDTH is (IDLE, WIDTH_A, WIDTH_B, WIDTH_C);
+  signal WIDTH_CURRENT, WIDTH_NEXT : WIDTH;
+  signal width_cntr : std_logic_vector(7 downto 0);
+  signal width_cntr_rst, width_cntr_rst_fsm, width_cntr_up, width_cntr_up_fsm, signal_out_buf, signal_out_fsm  : std_logic;
+  
+begin
+
+  COUNTER_FOR_WIDTH : up_down_counter
+    generic map (
+      NUMBER_OF_BITS => 8)
+    port map (
+      CLK       => CLK,
+      RESET     => width_cntr_rst,
+      COUNT_OUT => width_cntr,
+      UP_IN     => width_cntr_up,
+      DOWN_IN   => '0');
+
+
+  WIDTH_CLK : process (CLK, RESET)
+  begin
+    if rising_edge(CLK) then
+      if RESET = '1' then
+        WIDTH_CURRENT  <= IDLE;
+        width_cntr_rst <= '1';
+        width_cntr_up  <= '0';
+        signal_out_buf <= '0';
+      else
+        width_cntr_rst <= width_cntr_rst_fsm;
+        width_cntr_up  <= width_cntr_up_fsm;
+        signal_out_buf <= signal_out_fsm;
+
+        WIDTH_CURRENT <= WIDTH_NEXT;
+      end if;
+    end if;
+  end process WIDTH_CLK;
+
+
+  SIGNAL_OUT <= signal_out_buf;
+
+  WIDTH_PROC : process (CLK)
+  begin
+    width_cntr_up_fsm  <= '0';
+    width_cntr_rst_fsm <= '1';
+    signal_out_fsm     <= '0';
+
+    case (WIDTH_CURRENT) is
+      when IDLE =>
+        if SIGNAL_IN = '1' and SIGNAL_WIDTH > 0 then
+          WIDTH_NEXT <= WIDTH_A;
+        elsif SIGNAL_IN = '1' and SIGNAL_WIDTH = 0 then
+          signal_out_fsm <= SIGNAL_IN;
+          WIDTH_NEXT     <= IDLE;
+        else
+          WIDTH_NEXT <= IDLE;
+        end if;
+      when WIDTH_A =>
+        signal_out_fsm     <= '1';
+        width_cntr_rst_fsm <= '0';
+        width_cntr_up_fsm <= '1';
+        if width_cntr = SIGNAL_WIDTH - 1 then
+          WIDTH_NEXT <= IDLE;
+        else
+          WIDTH_NEXT <= WIDTH_A;
+        end if;
+      when others =>
+        WIDTH_NEXT <= IDLE;
+    end case;
+  end process WIDTH_PROC;
+
+end cts_fpga1_test_set_width;
-- 
2.43.0