From b21c2f4d10be93e5612448c25ed69c7b1ce0bba4 Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Thu, 25 Jun 2020 12:55:04 +0200 Subject: [PATCH] ECP5 cleanup, sync TRBnet preperations --- media_interfaces/med_ecp5_sfp_sync.vhd | 131 ++++++++--------- media_interfaces/sync/med_sync_control.vhd | 152 +++++++++++-------- media_interfaces/sync/rx_reset_fsm.vhd | 127 ++++++++-------- media_interfaces/sync/tx_reset_fsm.vhd | 161 ++++++++++----------- special/trb_net_reset_handler.vhd | 16 +- 5 files changed, 301 insertions(+), 286 deletions(-) diff --git a/media_interfaces/med_ecp5_sfp_sync.vhd b/media_interfaces/med_ecp5_sfp_sync.vhd index 79e0a92..cdd207d 100644 --- a/media_interfaces/med_ecp5_sfp_sync.vhd +++ b/media_interfaces/med_ecp5_sfp_sync.vhd @@ -49,46 +49,45 @@ end entity; architecture med_ecp5_sfp_sync_arch of med_ecp5_sfp_sync is - -- Placer Directives - attribute HGROUP : string; - -- for whole architecture - attribute HGROUP of med_ecp5_sfp_sync_arch : architecture is "media_interface_group"; - attribute syn_sharing : string; - attribute syn_sharing of med_ecp5_sfp_sync_arch : architecture is "off"; - attribute syn_hier : string; - attribute syn_hier of med_ecp5_sfp_sync_arch : architecture is "hard"; - --- signal clk_200_i : std_logic; -signal clk_200_ref : std_logic; -signal clk_rx_full : std_logic; -signal clk_tx_full : std_logic; -signal reset_n : std_logic; - -signal tx_data : std_logic_vector(7 downto 0); -signal tx_k : std_logic; -signal rx_data : std_logic_vector(7 downto 0); -signal rx_k : std_logic; -signal rx_error : std_logic; - -signal rst_n : std_logic; -signal rx_serdes_rst : std_logic; -signal tx_serdes_rst : std_logic; -signal tx_pcs_rst : std_logic; -signal rx_pcs_rst : std_logic; -signal rst_qd : std_logic; -signal serdes_rst_qd : std_logic; - -signal rx_los_low : std_logic; -signal lsm_status : std_logic; -signal rx_cdr_lol : std_logic; -signal tx_pll_lol : std_logic; - -signal sci_ch_i : std_logic_vector(4 downto 0); -signal sci_addr_i : std_logic_vector(5 downto 0); -signal sci_data_in_i : std_logic_vector(7 downto 0); -signal sci_data_out_i : std_logic_vector(7 downto 0); -signal sci_read_i : std_logic; -signal sci_write_i : std_logic; +-- Placer Directives +attribute HGROUP : string; +-- for whole architecture +attribute HGROUP of med_ecp5_sfp_sync_arch : architecture is "media_interface_group"; +attribute syn_sharing : string; +attribute syn_sharing of med_ecp5_sfp_sync_arch : architecture is "off"; +attribute syn_hier : string; +attribute syn_hier of med_ecp5_sfp_sync_arch : architecture is "hard"; + +signal clk_200_ref : std_logic; +signal clk_rx_full : std_logic; +signal clk_tx_full : std_logic; +signal reset_n : std_logic; + +signal tx_data : std_logic_vector(7 downto 0); +signal tx_k : std_logic; +signal rx_data : std_logic_vector(7 downto 0); +signal rx_k : std_logic; +signal rx_error : std_logic; + +signal rst_n : std_logic; +signal rx_serdes_rst : std_logic; +signal tx_serdes_rst : std_logic; +signal tx_pcs_rst : std_logic; +signal rx_pcs_rst : std_logic; +signal rst_qd : std_logic; +signal serdes_rst_qd : std_logic; + +signal rx_los_low : std_logic; +signal lsm_status : std_logic; +signal rx_cdr_lol : std_logic; +signal tx_pll_lol : std_logic; + +signal sci_ch_i : std_logic_vector(4 downto 0); +signal sci_addr_i : std_logic_vector(5 downto 0); +signal sci_data_in_i : std_logic_vector(7 downto 0); +signal sci_data_out_i : std_logic_vector(7 downto 0); +signal sci_read_i : std_logic; +signal sci_write_i : std_logic; signal wa_position : std_logic_vector(15 downto 0) := x"FFFF"; signal wa_position_sel : std_logic_vector(3 downto 0); @@ -99,12 +98,16 @@ signal debug_rx_control_i : std_logic_vector(31 downto 0); signal debug_tx_control_i : std_logic_vector(31 downto 0); signal stat_fsm_reset_i : std_logic_vector(31 downto 0); signal debug_med_sync_control_i : std_logic_vector(31 downto 0); -signal rx_ready, tx_ready : std_logic; -signal hdinp, hdinn, hdoutp, hdoutn : std_logic; +signal rx_ready : std_logic; +signal tx_ready : std_logic; +signal hdinp : std_logic; +signal hdinn : std_logic; +signal hdoutp : std_logic; +signal hdoutn : std_logic; attribute nopad : string; attribute nopad of hdinp, hdinn, hdoutp, hdoutn : signal is "true"; -signal stat_med : std_logic_vector(31 downto 0); +signal stat_med : std_logic_vector(31 downto 0); begin @@ -112,7 +115,6 @@ reset_n <= not RESET; clk_200_ref <= CLK_REF_FULL; SD_TXDIS_OUT <= not rx_ready when IS_SYNC_SLAVE = 1 else '0'; --slave only switches on when RX is ready --- SD_TXDIS_OUT <= RESET; -- gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate -- clk_200_i <= clk_rx_full; @@ -122,7 +124,6 @@ SD_TXDIS_OUT <= not rx_ready when IS_SYNC_SLAVE = 1 else '0'; --slave only swi -- clk_200_i <= clk_200_internal; -- end generate; - ------------------------------------------------- -- Serdes ------------------------------------------------- @@ -147,7 +148,7 @@ gen_pcs0 : if SERDES_NUM = SERDES_NUM generate -- same entity in any case serdes_sync_0_rx_cv_err(0) => rx_error, serdes_sync_0_tx_idle_c => '0', - serdes_sync_0_signal_detect_c => '0', --?force enable + serdes_sync_0_signal_detect_c => '0', serdes_sync_0_rx_los_low_s => rx_los_low, serdes_sync_0_lsm_status_s => lsm_status, serdes_sync_0_rx_cdr_lol_s => rx_cdr_lol, @@ -159,9 +160,9 @@ gen_pcs0 : if SERDES_NUM = SERDES_NUM generate -- same entity in any case serdes_sync_0_sci_wrdata => sci_data_in_i, serdes_sync_0_sci_rddata => sci_data_out_i, serdes_sync_0_sci_addr => sci_addr_i, - serdes_sync_0_sci_en_dual => reset_n, --sci_ch_i(4), --? + serdes_sync_0_sci_en_dual => reset_n, serdes_sync_0_sci_sel_dual => sci_ch_i(4), - serdes_sync_0_sci_en => reset_n, --sci_ch_i(0), --? + serdes_sync_0_sci_en => reset_n, serdes_sync_0_sci_sel => sci_ch_i(0), serdes_sync_0_sci_rd => sci_read_i, serdes_sync_0_sci_wrn => sci_write_i, @@ -176,20 +177,19 @@ gen_pcs0 : if SERDES_NUM = SERDES_NUM generate -- same entity in any case serdes_sync_0_tx_serdes_rst_c => tx_serdes_rst, serdes_sync_0_pll_refclki => CLK_REF_FULL, --- sli_rst => '0', serdes_sync_0_pll_lol => tx_pll_lol, serdes_sync_0_rsl_disable => '1', - serdes_sync_0_rsl_rst => '0', --CLEAR, + serdes_sync_0_rsl_rst => '0', serdes_sync_0_rsl_rx_rdy => rx_ready, serdes_sync_0_rsl_tx_rdy => tx_ready ); end generate; - tx_serdes_rst <= '0'; --SD_LOS_IN; --no function - serdes_rst_qd <= '0'; --included in rst_qd - wa_position_sel <= x"0"; --- wa_position_sel <= wa_position(3 downto 0) when SERDES_NUM = 0 --- else wa_position(15 downto 12) when SERDES_NUM = 3; + tx_serdes_rst <= '0'; + serdes_rst_qd <= '0'; +-- wa_position_sel <= x"0"; + wa_position_sel <= wa_position(3 downto 0) when SERDES_NUM = 0 + else wa_position(15 downto 12) when SERDES_NUM = 3; THE_MED_CONTROL : entity work.med_sync_control generic map( @@ -198,9 +198,9 @@ THE_MED_CONTROL : entity work.med_sync_control ) port map( CLK_SYS => SYSCLK, - CLK_RXI => clk_rx_full, --clk_rx_full, + CLK_RXI => clk_rx_full, CLK_RXHALF => '0', - CLK_TXI => clk_tx_full, --clk_200_ref, --clk_200_internal, --clk_tx_full, JM150706 + CLK_TXI => clk_tx_full, CLK_REF => CLK_INTERNAL_FULL, RESET => RESET, CLEAR => CLEAR, @@ -267,18 +267,10 @@ THE_SCI_READER : entity work.sci_reader DEBUG_OUT => open ); --- STAT_DEBUG(4 downto 0) <= debug_rx_control_i(4 downto 0); --- STAT_DEBUG(6 downto 5) <= stat_fsm_reset_i(9 downto 8); --- STAT_DEBUG(7) <= '0'; --- STAT_DEBUG(15 downto 8) <= stat_fsm_reset_i(7 downto 0); --- STAT_DEBUG(15 downto 0) <= debug_tx_control_i(31 downto 16); --- STAT_DEBUG(31 downto 0) <= debug_rx_control_i(31 downto 0); - STAT_DEBUG(3 downto 0) <= debug_med_sync_control_i(3 downto 0); - STAT_DEBUG(7 downto 4) <= rx_los_low & lsm_status & rx_cdr_lol & tx_pll_lol; --- STAT_DEBUG(9) <= CLK_REF_FULL; --- STAT_DEBUG(10) <= clk_rx_full; --- STAT_DEBUG(11) <= clk_tx_full; - +STAT_DEBUG(11 downto 0) <= debug_med_sync_control_i(11 downto 0); +STAT_DEBUG(15 downto 12) <= (others => '0'); +STAT_DEBUG(31 downto 16) <= wa_position; +STAT_DEBUG(63 downto 32) <= (others => '0'); stat_med(0) <= rst_qd; stat_med(1) <= rx_pcs_rst; @@ -292,6 +284,5 @@ stat_med(8) <= tx_ready; stat_med(9) <= lsm_status; stat_med(31 downto 10) <= (others => '0'); - end architecture; diff --git a/media_interfaces/sync/med_sync_control.vhd b/media_interfaces/sync/med_sync_control.vhd index bda484b..279ee7d 100644 --- a/media_interfaces/sync/med_sync_control.vhd +++ b/media_interfaces/sync/med_sync_control.vhd @@ -13,10 +13,10 @@ entity med_sync_control is IS_TX_RESET : integer := 1 ); port( - CLK_SYS : in std_logic; - CLK_RXI : in std_logic; + CLK_SYS : in std_logic; -- 100MHz system clock + CLK_RXI : in std_logic; -- recovered RX clock, 200MHz CLK_RXHALF : in std_logic; - CLK_TXI : in std_logic; + CLK_TXI : in std_logic; -- TX clock, 200MHz CLK_REF : in std_logic; RESET : in std_logic; CLEAR : in std_logic; @@ -89,104 +89,133 @@ signal make_link_reset_sys_i : std_logic := '0'; signal send_link_reset_real_i : std_logic := '0'; signal send_link_reset_sys_i : std_logic := '0'; -signal reset_i, rst_n, rst_n_tx : std_logic; +signal reset_i : std_logic; +signal rst_n : std_logic; +signal rst_n_tx : std_logic; +signal finished_reset_rx : std_logic; +signal finished_reset_rx_q : std_logic; +signal finished_reset_tx : std_logic; +signal finished_reset_tx_q : std_logic; + signal media_med2int_i : MED2INT; -signal finished_reset_rx, finished_reset_rx_q : std_logic; -signal finished_reset_tx, finished_reset_tx_q : std_logic; + +signal rx_serdes_rst_i : std_logic; +signal rx_pcs_rst_i : std_logic; + +signal rx_serdes_rst_i_q : std_logic_vector(2 downto 0); +signal rx_pcs_rst_i_q : std_logic_vector(2 downto 0); + +signal tx_pcs_rst_i : std_logic; +signal quad_rst_i : std_logic; begin rst_n_tx <= not (CLEAR or sd_los_i or make_link_reset_real_i or RESET) when (IS_SYNC_SLAVE = 1 and IS_TX_RESET = 1) else not (CLEAR or make_link_reset_real_i or RESET); - - rst_n <= not (CLEAR or sd_los_i or make_link_reset_real_i or RESET); reset_i <= (RESET or sd_los_i or make_link_reset_real_i); - media_med2int_i.clk_half <= CLK_RXHALF; media_med2int_i.clk_full <= CLK_RXI; ------------------------------------------------- --- Reset FSM & Link states +-- Reset RX FSM ------------------------------------------------- THE_RX_FSM : rx_reset_fsm port map( RST_N => rst_n, RX_REFCLK => CLK_REF, TX_PLL_LOL_QD_S => TX_LOL, - RX_SERDES_RST_CH_C => RX_SERDES_RST, + RX_SERDES_RST_CH_C => rx_serdes_rst_i, RX_CDR_LOL_CH_S => RX_CDR_LOL, RX_LOS_LOW_CH_S => RX_LOS, - RX_PCS_RST_CH_C => RX_PCS_RST, + RX_PCS_RST_CH_C => rx_pcs_rst_i, WA_POSITION => wa_position_rx, NORMAL_OPERATION_OUT => finished_reset_rx, STATE_OUT => rx_fsm_state ); + +-- crossing the abbyss +THE_ABBYSS_PROC: process( CLK_RXI ) +begin + if( rising_edge(CLK_RXI) ) then + rx_serdes_rst_i_q <= rx_serdes_rst_i_q(1 downto 0) & rx_serdes_rst_i; + rx_pcs_rst_i_q <= rx_pcs_rst_i_q(1 downto 0) & rx_pcs_rst_i; + end if; +end process THE_ABBYSS_PROC; + +RX_SERDES_RST <= rx_serdes_rst_i_q(2); +RX_PCS_RST <= rx_pcs_rst_i_q(2); +------------------------------------------------- +-- Reset TX FSM +------------------------------------------------- THE_TX_FSM : tx_reset_fsm port map( RST_N => rst_n_tx, TX_REFCLK => CLK_REF, TX_PLL_LOL_QD_S => TX_LOL, - RST_QD_C => QUAD_RST, - TX_PCS_RST_CH_C => TX_PCS_RST, + RST_QD_C => quad_rst_i, + TX_PCS_RST_CH_C => tx_pcs_rst_i, NORMAL_OPERATION_OUT => finished_reset_tx, STATE_OUT => tx_fsm_state ); - -SYNC_WA_POSITION : process begin - wait until rising_edge(CLK_REF); - if IS_SYNC_SLAVE = 1 then - wa_position_rx <= WA_POSITION; - else - wa_position_rx <= x"0"; +-- may also need sync? +TX_PCS_RST <= tx_pcs_rst_i; +QUAD_RST <= quad_rst_i; + +SYNC_WA_POSITION_PROC: process( CLK_REF ) +begin + if( rising_edge(CLK_REF) ) then + if IS_SYNC_SLAVE = 1 then + wa_position_rx <= WA_POSITION; + else + wa_position_rx <= x"0"; + end if; end if; -end process; +end process SYNC_WA_POSITION_PROC; ------------------------------------------------- -- RX & TX allow ------------------------------------------------- ---Slave enables RX/TX when sync is done, Master waits additional time to make sure link is stable +-- Slave enables RX/TX when sync is done, Master waits additional time to make sure link is stable PROC_ALLOW : process begin wait until rising_edge(CLK_SYS); - if finished_reset_rx_q = '1' --SERDES_RX_READY_IN= '1' --and - and (IS_SYNC_SLAVE = 1 or start_timer(start_timer'left) = '1') then + if( (finished_reset_rx_q = '1') + and (IS_SYNC_SLAVE = 1 or start_timer(start_timer'left) = '1') ) then rx_allow <= '1'; else rx_allow <= '0'; end if; - if --SERDES_RX_READY_IN = '1' and SERDES_TX_READY_IN = '1' - finished_reset_tx_q = '1' and finished_reset_rx_q = '1' - and (IS_SYNC_SLAVE = 1 or start_timer(start_timer'left) = '1') then + if( (finished_reset_tx_q = '1' and finished_reset_rx_q = '1') + and (IS_SYNC_SLAVE = 1 or start_timer(start_timer'left) = '1') ) then tx_allow <= '1'; else tx_allow <= '0'; end if; end process; - - link_reset_fin_tx : signal_sync port map(RESET => '0',CLK0 => CLK_SYS, CLK1 => CLK_SYS, +LINK_RESET_FIN_TX : signal_sync port map(RESET => '0',CLK0 => CLK_SYS, CLK1 => CLK_SYS, D_IN(0) => finished_reset_tx, D_OUT(0) => finished_reset_tx_q); - link_reset_fin_rx : signal_sync port map(RESET => '0',CLK0 => CLK_SYS, CLK1 => CLK_SYS, +LINK_RESET_FIN_RX : signal_sync port map(RESET => '0',CLK0 => CLK_SYS, CLK1 => CLK_SYS, D_IN(0) => finished_reset_rx, D_OUT(0) => finished_reset_rx_q); - -PROC_START_TIMER : process begin - wait until rising_edge(CLK_SYS); - -- if got_link_ready_i = '1' then - if finished_reset_tx_q = '1' and finished_reset_rx_q = '1' then - if start_timer(start_timer'left) = '0' then - start_timer <= start_timer + 1; - end if; - else - start_timer <= (others => '0'); +START_TIMER_PROC : process( CLK_SYS ) +begin + if( rising_edge(CLK_SYS) ) then + if( (finished_reset_tx_q = '1') and (finished_reset_rx_q = '1') ) then + if start_timer(start_timer'left) = '0' then + start_timer <= start_timer + 1; + end if; + else + start_timer <= (others => '0'); + end if; end if; -end process; +end process START_TIMER_PROC; ------------------------------------------------- -- TX Data @@ -269,21 +298,21 @@ MEDIA_MED2INT <= media_med2int_i; ------------------------------------------------- led_ok <= rx_allow and tx_allow when rising_edge(CLK_SYS); led_rx <= (media_med2int_i.dataready or led_rx) and not timer(20) when rising_edge(CLK_SYS); --- led_tx <= '1' when DEBUG_TX_CONTROL(13 downto 10) = x"c" else '0'; -- led_tx <= (MEDIA_INT2MED.dataready or led_tx or sd_los_i) and not timer(20) when rising_edge(CLK_SYS); led_dlm <= (led_dlm or rx_dlm_i) and not timer(20) when rising_edge(CLK_SYS); --- led_dlm <= '1' when DEBUG_RX_CONTROL(3 downto 0) = x"f" else '0'; -ROC_TIMER : process begin - wait until rising_edge(CLK_SYS); - timer <= timer + 1 ; - if timer(20) = '1' then - timer <= (others => '0'); - last_led_rx <= led_rx ; - last_led_tx <= led_tx; - last_led_dlm <= led_dlm; +ROC_TIMER_PROC: process( CLK_SYS ) +begin + if( rising_edge(CLK_SYS) ) then + timer <= timer + 1 ; + if timer(20) = '1' then + timer <= (others => '0'); + last_led_rx <= led_rx ; + last_led_tx <= led_tx; + last_led_dlm <= led_dlm; + end if; end if; -end process; +end process ROC_TIMER_PROC; ------------------------------------------------- -- Status signals @@ -332,9 +361,18 @@ media_med2int_i.stat_op(8 downto 5) <= (others => '0'); media_med2int_i.stat_op(4) <= rx_allow; media_med2int_i.stat_op(3 downto 0) <= x"0" when rx_allow = '1' and tx_allow = '1' else x"7"; -DEBUG_OUT(0) <= tx_allow; -DEBUG_OUT(1) <= rx_allow; -DEBUG_OUT(2) <= sd_los_i; -DEBUG_OUT(3) <= '0'; --DEBUG_RX_CONTROL(4); +DEBUG_OUT(0) <= TX_LOL; +DEBUG_OUT(1) <= RX_CDR_LOL; +DEBUG_OUT(2) <= RX_LOS; +DEBUG_OUT(3) <= rst_n; +DEBUG_OUT(4) <= rst_n_tx; +DEBUG_OUT(5) <= quad_rst_i; +DEBUG_OUT(6) <= rx_pcs_rst_i; +DEBUG_OUT(7) <= tx_pcs_rst_i; +DEBUG_OUT(8) <= rx_serdes_rst_i; +DEBUG_OUT(9) <= finished_reset_rx; +DEBUG_OUT(10) <= finished_reset_tx; +DEBUG_OUT(11) <= reset_i; +DEBUG_OUT(31 downto 12) <= (others => '0'); end architecture; diff --git a/media_interfaces/sync/rx_reset_fsm.vhd b/media_interfaces/sync/rx_reset_fsm.vhd index 7fc3aec..9d016e3 100644 --- a/media_interfaces/sync/rx_reset_fsm.vhd +++ b/media_interfaces/sync/rx_reset_fsm.vhd @@ -1,11 +1,9 @@ --Media interface RX state machine - LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.numeric_std.all; - entity rx_reset_fsm is port ( RST_N : in std_logic; @@ -25,34 +23,65 @@ end entity ; architecture rx_reset_fsm_arch of rx_reset_fsm is constant count_index : integer := 19; -type statetype is (WAIT_FOR_PLOL, RX_SERDES_RESET, WAIT_FOR_timer1, CHECK_LOL_LOS, WAIT_FOR_timer2, NORMAL); +type statetype is ( WAIT_FOR_PLOL, RX_SERDES_RESET, WAIT_FOR_TIMER1, CHECK_LOL_LOS, WAIT_FOR_TIMER2, NORMAL ); -signal cs: statetype; -- current state of lsm -signal ns: statetype; -- next state of lsm +signal cs : statetype; -- current state of lsm +signal ns : statetype; -- next state of lsm -signal tx_pll_lol_qd_q: std_logic; -signal rx_cdr_lol_ch_q: std_logic; -signal rx_los_low_ch_q: std_logic; -signal rx_lol_los : std_logic; -signal rx_lol_los_int: std_logic; -signal rx_lol_los_del: std_logic; -signal rx_pcs_rst_ch_c_int: std_logic; -signal rx_serdes_rst_ch_c_int: std_logic; +signal tx_pll_lol_qd_q : std_logic; +signal rx_cdr_lol_ch_q : std_logic; +signal rx_los_low_ch_q : std_logic; +signal rx_lol_los : std_logic; +signal rx_lol_los_int : std_logic; +signal rx_lol_los_del : std_logic; +signal rx_pcs_rst_ch_c_int : std_logic; +signal rx_serdes_rst_ch_c_int : std_logic; -signal reset_timer1: std_logic; -signal reset_timer2: std_logic; +signal reset_timer1 : std_logic; +signal reset_timer2 : std_logic; -signal counter1: unsigned(1 downto 0); -signal timer1: std_logic; +signal counter1 : unsigned(1 downto 0); +signal timer1 : std_logic; -signal counter2: unsigned(19 downto 0); -signal timer2 : std_logic; +signal counter2 : unsigned(19 downto 0); +signal timer2 : std_logic; begin rx_lol_los <= rx_cdr_lol_ch_q or rx_los_low_ch_q ; -process(RX_REFCLK) +sync_sfp_sigs : entity work.signal_sync + generic map(WIDTH => 3) + port map(RESET => '0',CLK0 => RX_REFCLK, CLK1 => RX_REFCLK, + D_IN(0) => TX_PLL_LOL_QD_S, + D_IN(1) => RX_CDR_LOL_CH_S, + D_IN(2) => RX_LOS_LOW_CH_S, + D_OUT(0) => tx_pll_lol_qd_q, + D_OUT(1) => rx_cdr_lol_ch_q, + D_OUT(2) => rx_los_low_ch_q + ); + + +--timer2 = 400,000 Refclk cycles or 200,000 REFCLKDIV2 cycles +--An 18 bit counter ([17:0]) counts 262144 cycles, so a 19 bit ([18:0]) counter will do if we set timer2 = bit[18] + +THE_TIMER2_PROC: process( RX_REFCLK ) +begin + if reset_timer2 = '1' then + counter2 <= (others => '0'); + timer2 <= '0'; + else + if counter2(count_index) = '1' then + timer2 <= '1'; + else + timer2 <= '0'; + counter2 <= counter2 + 1 ; + end if; + end if; +end process THE_TIMER2_PROC; + +-- State machine clocked process +THE_FSM_PROC: process( RX_REFCLK ) begin if rising_edge(RX_REFCLK) then if RST_N = '0' then @@ -70,38 +99,8 @@ begin end if; end if; end process; - - sync_sfp_sigs : entity work.signal_sync - generic map(WIDTH => 3) - port map(RESET => '0',CLK0 => RX_REFCLK, CLK1 => RX_REFCLK, - D_IN(0) => TX_PLL_LOL_QD_S, - D_IN(1) => RX_CDR_LOL_CH_S, - D_IN(2) => RX_LOS_LOW_CH_S, - D_OUT(0) => tx_pll_lol_qd_q, - D_OUT(1) => rx_cdr_lol_ch_q, - D_OUT(2) => rx_los_low_ch_q - ); - ---timer2 = 400,000 Refclk cycles or 200,000 REFCLKDIV2 cycles ---An 18 bit counter ([17:0]) counts 262144 cycles, so a 19 bit ([18:0]) counter will do if we set timer2 = bit[18] - process begin - wait until rising_edge(RX_REFCLK); - if reset_timer2 = '1' then - counter2 <= "00000000000000000000"; - timer2 <= '0'; - else - if counter2(count_index) = '1' then - timer2 <='1'; - else - timer2 <='0'; - counter2 <= counter2 + 1 ; - end if; - end if; - end process; - - -process(cs, tx_pll_lol_qd_q, rx_los_low_ch_q, timer1, rx_lol_los_int, timer2, wa_position, rx_lol_los_del) +THE_FSM_DECODE_PROC: process( cs, tx_pll_lol_qd_q, rx_los_low_ch_q, timer1, rx_lol_los_int, timer2, wa_position, rx_lol_los_del ) begin reset_timer2 <= '0'; STATE_OUT <= x"F"; @@ -111,22 +110,20 @@ begin when WAIT_FOR_PLOL => rx_pcs_rst_ch_c_int <= '1'; rx_serdes_rst_ch_c_int <= '0'; - if (tx_pll_lol_qd_q = '1' or rx_los_low_ch_q = '1') then --Also make sure A Signal - ns <= WAIT_FOR_PLOL; --is Present prior to moving to the next + if( (tx_pll_lol_qd_q = '1') or (rx_los_low_ch_q = '1') ) then -- also make sure a Signal + ns <= WAIT_FOR_PLOL; -- is present prior to moving to the next else - ns <= RX_SERDES_RESET; + ns <= RX_SERDES_RESET; end if; STATE_OUT <= x"1"; when RX_SERDES_RESET => rx_pcs_rst_ch_c_int <= '1'; rx_serdes_rst_ch_c_int <= '1'; --- reset_timer1 <= '1'; ns <= WAIT_FOR_timer1; STATE_OUT <= x"2"; - - - when WAIT_FOR_timer1 => + + when WAIT_FOR_TIMER1 => rx_pcs_rst_ch_c_int <= '1'; rx_serdes_rst_ch_c_int <= '1'; ns <= CHECK_LOL_LOS; @@ -136,10 +133,10 @@ begin rx_pcs_rst_ch_c_int <= '1'; rx_serdes_rst_ch_c_int <= '0'; reset_timer2 <= '1'; - ns <= WAIT_FOR_timer2; + ns <= WAIT_FOR_TIMER2; STATE_OUT <= x"4"; - when WAIT_FOR_timer2 => + when WAIT_FOR_TIMER2 => rx_pcs_rst_ch_c_int <= '1'; rx_serdes_rst_ch_c_int <= '0'; if rx_lol_los_int = rx_lol_los_del then --NO RISING OR FALLING EDGES @@ -150,14 +147,13 @@ begin ns <= NORMAL; end if; else - ns <= WAIT_FOR_timer2; + ns <= WAIT_FOR_TIMER2; end if; else ns <= CHECK_LOL_LOS; --RESET timer2 end if; STATE_OUT <= x"5"; - when NORMAL => rx_pcs_rst_ch_c_int <= '0'; rx_serdes_rst_ch_c_int <= '0'; @@ -174,9 +170,6 @@ begin end case; -end process; - - - - +end process THE_FSM_DECODE_PROC; + end architecture; diff --git a/media_interfaces/sync/tx_reset_fsm.vhd b/media_interfaces/sync/tx_reset_fsm.vhd index b10d8e1..0bc22d3 100644 --- a/media_interfaces/sync/tx_reset_fsm.vhd +++ b/media_interfaces/sync/tx_reset_fsm.vhd @@ -1,88 +1,71 @@ --Media interface TX state machine - LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.numeric_std.all; - entity tx_reset_fsm is port ( - RST_N : in std_logic; - TX_REFCLK : in std_logic; - TX_PLL_LOL_QD_S : in std_logic; - RST_QD_C : out std_logic; - TX_PCS_RST_CH_C : out std_logic; + RST_N : in std_logic; + TX_REFCLK : in std_logic; + TX_PLL_LOL_QD_S : in std_logic; + RST_QD_C : out std_logic; + TX_PCS_RST_CH_C : out std_logic; NORMAL_OPERATION_OUT : out std_logic; - STATE_OUT : out std_logic_vector(3 downto 0) - + STATE_OUT : out std_logic_vector(3 downto 0) ); end entity; architecture tx_reset_fsm_arch of tx_reset_fsm is -constant count_index : integer := 19; -type statetype is (QUAD_RESET, WAIT_FOR_TIMER1, CHECK_PLOL, WAIT_FOR_TIMER2, NORMAL); - -signal cs: statetype; -- current state of lsm -signal ns: statetype; -- next state of lsm +constant count_index : integer := 19; -- end of timer2 + +type statetype is ( QUAD_RESET, WAIT_FOR_TIMER1, CHECK_PLOL, WAIT_FOR_TIMER2, NORMAL ); + +signal cs : statetype; -- current state of lsm +signal ns : statetype; -- next state of lsm -signal tx_pll_lol_qd_s_int : std_logic; -signal tx_pcs_rst_ch_c_int : std_logic; -signal RST_QD_C_int : std_logic; +signal tx_pll_lol_qd_s_int : std_logic; +signal tx_pcs_rst_ch_c_int : std_logic; +signal rst_qd_c_int : std_logic; -signal reset_timer1: std_logic; -signal reset_timer2: std_logic; +signal reset_timer1 : std_logic; +signal reset_timer2 : std_logic; -signal counter1: unsigned(2 downto 0); -signal TIMER1: std_logic; +signal counter1 : unsigned(2 downto 0); +signal timer1 : std_logic; -signal counter2: unsigned(19 downto 0); -signal TIMER2: std_logic; +signal counter2 : unsigned(19 downto 0); +signal timer2 : std_logic; begin -process (TX_REFCLK, RST_N) -begin - if RST_N = '0' then - cs <= QUAD_RESET; - tx_pcs_rst_ch_c <= '1'; - RST_QD_C <= '1'; - else if rising_edge(TX_REFCLK) then - cs <= ns; - tx_pcs_rst_ch_c <= tx_pcs_rst_ch_c_int; - RST_QD_C <= RST_QD_C_int; - end if; - end if; -end process; - - sync_sfp_sigs : entity work.signal_sync port map(RESET => '0',CLK0 => TX_REFCLK, CLK1 => TX_REFCLK, - D_IN(0) => TX_PLL_LOL_QD_S, - D_OUT(0) => tx_pll_lol_qd_s_int); +sync_sfp_sigs : entity work.signal_sync port map(RESET => '0',CLK0 => TX_REFCLK, CLK1 => TX_REFCLK, + D_IN(0) => TX_PLL_LOL_QD_S, + D_OUT(0) => tx_pll_lol_qd_s_int); --TIMER1 = 20ns; --Fastest REFLCK =312 MHZ, or 3 ns. We need 8 REFCLK cycles or 4 REFCLKDIV2 cycles -- A 2 bit counter ([1:0]) counts 4 cycles, so a 3 bit ([2:0]) counter will do if we set TIMER1 = bit[2] - -process (TX_REFCLK) +-- Timer 1 +THE_TIMER1_PROC: process( TX_REFCLK ) begin if rising_edge(TX_REFCLK) then - if reset_timer1 = '1' then - counter1 <= "000"; - TIMER1 <= '0'; + if reset_timer1 = '1' then + counter1 <= (others => '0'); + timer1 <= '0'; + else + if counter1(2) = '1' then + timer1 <= '1'; else - if counter1(2) = '1' then - TIMER1 <= '1'; - else - TIMER1 <='0'; - counter1 <= counter1 + 1 ; - end if; + timer1 <='0'; + counter1 <= counter1 + 1 ; end if; + end if; end if; -end process; - +end process THE_TIMER1_PROC; --TIMER2 = 1,400,000 UI; --WORST CASE CYCLES is with smallest multipier factor. @@ -90,26 +73,41 @@ end process; -- IN this casse, 1 UI = 2/8 REFCLK CYCLES = 1/8 REFCLKDIV2 CYCLES -- SO 1,400,000 UI =1,400,000/8 = 175,000 REFCLKDIV2 CYCLES -- An 18 bit counter ([17:0]) counts 262144 cycles, so a 19 bit ([18:0]) counter will do if we set TIMER2 = bit[18] - - -process(TX_REFCLK, reset_timer2) + +THE_TIMER2_PROC: process( TX_REFCLK ) begin if rising_edge(TX_REFCLK) then - if reset_timer2 = '1' then - counter2 <= "00000000000000000000"; - TIMER2 <= '0'; + if reset_timer2 = '1' then + counter2 <= (others => '0'); + timer2 <= '0'; + else + if counter2(count_index) = '1' then + timer2 <='1'; else - if counter2(count_index) = '1' then - TIMER2 <='1'; - else - TIMER2 <='0'; - counter2 <= counter2 + 1 ; - end if; + timer2 <='0'; + counter2 <= counter2 + 1 ; end if; + end if; end if; -end process; - -process(cs, TIMER1, TIMER2, tx_pll_lol_qd_s_int) +end process THE_TIMER2_PROC; + +-- State machine clocked process +THE_FSM_PROC: process( TX_REFCLK, RST_N ) +begin + if RST_N = '0' then + cs <= QUAD_RESET; + tx_pcs_rst_ch_c <= '1'; + RST_QD_C <= '1'; + else + if rising_edge(TX_REFCLK) then + cs <= ns; + tx_pcs_rst_ch_c <= tx_pcs_rst_ch_c_int; + RST_QD_C <= rst_qd_c_int; + end if; + end if; +end process THE_FSM_PROC; + +THE_FSM_DECODE_PROC: process( cs, timer1, timer2, tx_pll_lol_qd_s_int ) begin reset_timer1 <= '0'; reset_timer2 <= '0'; @@ -121,15 +119,15 @@ begin when QUAD_RESET => STATE_OUT <= x"1"; tx_pcs_rst_ch_c_int <= '1'; - RST_QD_C_int <= '1'; + rst_qd_c_int <= '1'; reset_timer1 <= '1'; - ns <= WAIT_FOR_TIMER1; + ns <= WAIT_FOR_TIMER1; when WAIT_FOR_TIMER1 => STATE_OUT <= x"2"; tx_pcs_rst_ch_c_int <= '1'; - RST_QD_C_int <= '1'; - if TIMER1 = '1' then + rst_qd_c_int <= '1'; + if timer1 = '1' then ns <= CHECK_PLOL; else ns <= WAIT_FOR_TIMER1; @@ -138,19 +136,19 @@ begin when CHECK_PLOL => STATE_OUT <= x"3"; tx_pcs_rst_ch_c_int <= '1'; - RST_QD_C_int <= '0'; + rst_qd_c_int <= '0'; reset_timer2 <= '1'; - ns <= WAIT_FOR_TIMER2; + ns <= WAIT_FOR_TIMER2; when WAIT_FOR_TIMER2 => STATE_OUT <= x"4"; tx_pcs_rst_ch_c_int <= '1'; - RST_QD_C_int <= '0'; - if TIMER2 = '1' then + rst_qd_c_int <= '0'; + if timer2 = '1' then if tx_pll_lol_qd_s_int = '1' then - ns <= QUAD_RESET; + ns <= QUAD_RESET; else - ns <= NORMAL; + ns <= NORMAL; end if; else ns <= WAIT_FOR_TIMER2; @@ -159,7 +157,7 @@ begin when NORMAL => STATE_OUT <= x"5"; tx_pcs_rst_ch_c_int <= '0'; - RST_QD_C_int <= '0'; + rst_qd_c_int <= '0'; if tx_pll_lol_qd_s_int = '1' then ns <= QUAD_RESET; else @@ -170,8 +168,7 @@ begin when others => ns <= QUAD_RESET; - end case; - -end process; + end case; +end process THE_FSM_DECODE_PROC; end architecture; diff --git a/special/trb_net_reset_handler.vhd b/special/trb_net_reset_handler.vhd index 7c75cab..fcb8524 100644 --- a/special/trb_net_reset_handler.vhd +++ b/special/trb_net_reset_handler.vhd @@ -85,8 +85,8 @@ comb_async_pulse <= '1' when ( async_sampler(7 downto 2) = b"0000_00" ) else '0' THE_SYNC_PROC: process( sysclk_in ) begin if( rising_edge(sysclk_in) ) then - reset_buffer <= reset_in; -- not really needed, but relaxes timing - trb_reset_buffer <= trb_reset_in; -- not really needed, but relaxes timing + reset_buffer <= RESET_IN; -- not really needed, but relaxes timing + trb_reset_buffer <= TRB_RESET_IN; -- not really needed, but relaxes timing final_reset <= final_reset(0) & reset; end if; end process THE_SYNC_PROC; @@ -119,7 +119,6 @@ begin end if; end process THE_GLOBAL_RESET_PROC; - ---------------------------------------------------------------- -- Debug signals ---------------------------------------------------------------- @@ -128,16 +127,13 @@ debug(10) <= reset; debug(9) <= '0'; debug(8 downto 7) <= final_reset; debug(6) <= async_pulse; --- debug(5 downto 0) <= reset_cnt(5 downto 0); ---debug(15) <= comb_async_pulse; ---debug(14 downto 8) <= (others => '0'); ---debug(7 downto 0) <= async_sampler; +debug(5 downto 0) <= reset_cnt(5 downto 0); ---------------------------------------------------------------- -- Output signals ---------------------------------------------------------------- -debug_out <= debug; -clear_out <= not comb_async_rst_n; -reset_out <= final_reset(1); +DEBUG_OUT <= debug; +CLEAR_OUT <= not comb_async_rst_n; +RESET_OUT <= final_reset(1); end behavioral; -- 2.43.0