From b21c4373e3403f30125deefd1ffe80e46e3a9a04 Mon Sep 17 00:00:00 2001 From: hadaq Date: Mon, 5 Jul 2010 13:29:17 +0000 Subject: [PATCH] *** empty log message *** --- cts_fpga1.prj | 107 +++++++++++++++++++------------------------------- cts_fpga1.vhd | 56 +++++++++++++++++++++++++- 2 files changed, 95 insertions(+), 68 deletions(-) diff --git a/cts_fpga1.prj b/cts_fpga1.prj index 1e3f7eb..73cb5a8 100644 --- a/cts_fpga1.prj +++ b/cts_fpga1.prj @@ -1,23 +1,19 @@ -#-- Synplicity, Inc. -#-- Version 9.0 -#-- Project file ../ctsaddon/cts_fpga1.prj - - #add_file options add_file -vhdl -lib work "version.vhd" add_file -vhdl -lib work "../trbnet/trb_net_std.vhd" add_file -vhdl -lib work "../trbnet/trb_net_components.vhd" - -add_file -vhdl -lib work "../trbnet/trb_net16_term_buf.vhd" -add_file -vhdl -lib work "../trbnet/trb_net_CRC.vhd" -add_file -vhdl -lib work "../trbnet/trb_net_onewire.vhd" +add_file -vhdl -lib work "../trbnet/basics/signal_sync.vhd" +add_file -vhdl -lib work "../trbnet/basics/ram_dp_rw.vhd" add_file -vhdl -lib work "../trbnet/basics/rom_16x8.vhd" add_file -vhdl -lib work "../trbnet/basics/ram.vhd" add_file -vhdl -lib work "../trbnet/basics/ram_16x8_dp.vhd" add_file -vhdl -lib work "../trbnet/basics/ram_16x16_dp.vhd" -add_file -vhdl -lib work "../trbnet/trb_net16_addresses.vhd" add_file -vhdl -lib work "../trbnet/basics/ram_dp.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_term_buf.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_CRC.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_onewire.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_addresses.vhd" add_file -vhdl -lib work "../trbnet/trb_net16_term.vhd" add_file -vhdl -lib work "../trbnet/trb_net_sbuf.vhd" add_file -vhdl -lib work "../trbnet/trb_net16_sbuf.vhd" @@ -39,107 +35,84 @@ add_file -vhdl -lib work "../trbnet/trb_net16_trigger.vhd" add_file -vhdl -lib work "../trbnet/trb_net16_ipudata.vhd" add_file -vhdl -lib work "../trbnet/trb_net16_endpoint_hades_full.vhd" add_file -vhdl -lib work "../trbnet/trb_net_onewire_listener.vhd" -add_file -vhdl -lib work "../trbnet/basics/signal_sync.vhd" -add_file -vhdl -lib work "../trbnet/basics/ram_dp_rw.vhd" add_file -vhdl -lib work "../trbnet/special/spi_master.vhd" add_file -vhdl -lib work "../trbnet/special/spi_slim.vhd" add_file -vhdl -lib work "../trbnet/special/spi_databus_memory.vhd" -add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" - - add_file -vhdl -lib work "../trbnet/special/handler_data.vhd" add_file -vhdl -lib work "../trbnet/special/handler_ipu.vhd" add_file -vhdl -lib work "../trbnet/special/handler_trigger_and_data.vhd" +add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" add_file -vhdl -lib work "../trbnet/trb_net16_endpoint_hades_full_handler.vhd" - - #Lattice SCM files add_file -vhdl -lib work "../trbnet/lattice/scm/pll_in200_out100.vhd" add_file -vhdl -lib work "../trbnet/lattice/scm/lattice_ecp2m_fifo.vhd" -#Wrong filename, but hard to change now... +############################# +add_file -vhdl -lib work "../trbnet/lattice/scm/spi_dpram_32_to_8.vhd" +add_file -vhdl -lib work "../trbnet/lattice/scm/lattice_scm_fifo_18x1k.vhd" +add_file -vhdl -lib work "../trbnet/lattice/scm/trb_net16_fifo_arch.vhd" +add_file -vhdl -lib work "../trbnet/special/trb_net_reset_handler.vhd" +add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_36x256_oreg.vhd" +add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_36x512_oreg.vhd" +add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_36x1k_oreg.vhd" +add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_36x2k_oreg.vhd" +add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_36x4k_oreg.vhd" +add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_36x8k_oreg.vhd" +add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_36x16k_oreg.vhd" +add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_36x32k_oreg.vhd" +add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_18x256_oreg.vhd" +add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_18x512_oreg.vhd" +add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_18x1k_oreg.vhd" +add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_18x2k_oreg.vhd" +add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_var_oreg.vhd" +add file -vhdl -lib work "../trbnet/lattice/media_interfaces/trb_net16_med_scm_sfp_gbe.vhd" +############################# add_file -vhdl -lib work "cts_fpga1.vhd" -#Some of these files have to be regenerated -# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd" -# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd" - -#Dualported fifo -# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd" -# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd" - - -#SPI Fifo -# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd" - -#Media Interface -# add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd" -# add_file -vhdl -lib work "../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_0.vhd" +#################### -#Collection of fifos for data and trigger handler. fifo_var_oreg is a wrapper around all fifos, lattice_ecp2m_fifo is the library with all component declarations. -# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_36x256_oreg.vhd" -# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_36x512_oreg.vhd" -# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_36x1k_oreg.vhd" -# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_36x2k_oreg.vhd" -# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_36x4k_oreg.vhd" -# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_36x8k_oreg.vhd" -# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_36x16k_oreg.vhd" -# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_36x32k_oreg.vhd" -# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_18x256_oreg.vhd" -# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_18x512_oreg.vhd" -# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_18x1k_oreg.vhd" -# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_18x2k_oreg.vhd" -# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" -add_file -vhdl -lib work "../trbnet/lattice/scm/lattice_ecp2m_fifo.vhd" #Name has to be kept with scp2m unfortunately. - - - - -#implementation: "workdir" +# implementation: "workdir" impl -add workdir -type fpga -#device options +# device options set_option -technology LATTICE-SCM set_option -part LFSCM3GA40EP1 set_option -package FF1020C set_option -speed_grade -5 set_option -part_companion "" -#compilation/mapping options +# compilation/mapping options set_option -default_enum_encoding sequential set_option -symbolic_fsm_compiler 1 -#set_option -resource_sharing 0 set_option -top_module "cts_fpga1" -#map options -set_option -frequency auto +# map options +set_option -frequency 100 set_option -fanout_limit 100 set_option -disable_io_insertion 0 set_option -retiming 0 set_option -pipe 0 -set_option -force_gsr auto +# set_option -force_gsr auto +set_option -force_gsr false set_option -fixgatedclocks 3 set_option -fixgeneratedclocks 3 - - -#simulation options +# simulation options set_option -write_verilog 0 -set_option -write_vhdl 0 +set_option -write_vhdl 1 -#automatic place and route (vendor) options +# automatic place and route (vendor) options set_option -write_apr_constraint 0 -#set result format/file last +# set result format/file last project -result_format "edif" project -result_file "workdir/cts_fpga1.edf" - -# #implementation attributes set_option -vlog_std v2001 set_option -project_relative_includes 1 impl -active "workdir" + diff --git a/cts_fpga1.vhd b/cts_fpga1.vhd index 4cd4e28..1030535 100644 --- a/cts_fpga1.vhd +++ b/cts_fpga1.vhd @@ -111,7 +111,7 @@ architecture cts_fpga1_arch of cts_fpga1 is --Clock & Reset signal clk_100 : std_logic; - signal clk_200 : std_logic; +-- signal clk_200 : std_logic; signal clk_en : std_logic; signal make_reset_via_network : std_logic; signal pll_locked : std_logic; @@ -244,6 +244,60 @@ begin -- Media Interface --------------------------------------------------------------------------- +THE_MEDIA_INTERFACE_0: trb_net16_med_scm_sfp_gbe +generic map( + SERDES_NUM => 0, + EXT_CLOCK => c_NO, + USE_200_MHZ => c_YES +) +port map( + CLK => CLK_200_IN, -- raw 200MHz clock + SYSCLK => clk_100, -- 100MHz from PLL + RESET => reset_i_100, + CLEAR => reset_async, + CLK_EN => clk_en, + --Internal Connection + MED_DATA_IN => med_data_out, + MED_PACKET_NUM_IN => med_packet_num_out, + MED_DATAREADY_IN => med_dataready_out, + MED_READ_OUT => med_read_in, + MED_DATA_OUT => med_data_in, + MED_PACKET_NUM_OUT => med_packet_num_in, + MED_DATAREADY_OUT => med_dataready_in, + MED_READ_IN => med_read_out, + REFCLK2CORE_OUT => open, + --SFP Connection + SD_RXD_P_IN => FAKE_SERDES_RXD_P_IN, -- ignore + SD_RXD_N_IN => FAKE_SERDES_RXD_N_IN, -- ignore + SD_TXD_P_OUT => FAKE_SERDES_TXD_P_OUT, -- ignore + SD_TXD_N_OUT => FAKE_SERDES_TXD_N_OUT, -- ignore + SD_REFCLK_P_IN => FAKE_SERDES_REFCLK_P_IN, -- ignore + SD_REFCLK_N_IN => FAKE_SERDES_REFCLK_N_IN, -- ignore + SD_PRSNT_N_IN => '0', -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) + SD_LOS_IN => '0', -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + SD_TXDIS_OUT => open, -- SFP disable + -- Status and control port + STAT_OP => med_stat_op, + CTRL_OP => med_ctrl_op, + STAT_DEBUG => open, + CTRL_DEBUG => open + ); + +-- --SFP Connection +-- SD_RXD_P_IN => F3_RXP, +-- SD_RXD_N_IN => F3_RXN, +-- SD_TXD_P_OUT => F3_TXP, +-- SD_TXD_N_OUT => F3_TXN, +-- SD_REFCLK_P_IN => open, +-- SD_REFCLK_N_IN => open, +-- SD_PRSNT_N_IN => '0', +-- SD_LOS_IN => '0', +-- -- Status and control port +-- STAT_OP => med_stat_op, +-- CTRL_OP => med_ctrl_op, +-- STAT_DEBUG => med_stat_debug, +-- CTRL_DEBUG => (others => '0') +-- ); --------------------------------------------------------------------------- -- TrbNet Endpoint -- 2.43.0