From b3bf51255ed225b15ce33b7168da306f32aa3ee1 Mon Sep 17 00:00:00 2001 From: Cahit Date: Mon, 27 Apr 2015 12:18:44 +0200 Subject: [PATCH] various changes in version 2.1.2 --- base/cores/ecp3/PLL/generate_core.tcl | 100 +++++++++++ base/cores/ecp3/PLL/generate_ngd.tcl | 115 ++++++++++++ base/cores/ecp3/PLL/msg_file.log | 29 +++ base/cores/ecp3/PLL/pll_in125_out100.edn | 167 ++++++++++++++++++ base/cores/ecp3/PLL/pll_in125_out100.ipx | 8 + base/cores/ecp3/PLL/pll_in125_out100.jhd | 0 base/cores/ecp3/PLL/pll_in125_out100.lpc | 69 ++++++++ base/cores/ecp3/PLL/pll_in125_out100.sort | 1 + base/cores/ecp3/PLL/pll_in125_out100.srp | 26 +++ base/cores/ecp3/PLL/pll_in125_out100.vhd | 99 +++++++++++ .../ecp3/PLL/pll_in125_out100_generate.log | 44 +++++ base/cores/ecp3/PLL/pll_in125_out100_tmpl.vhd | 12 ++ releases/ReleaseNotes.org | 7 + releases/tdc_v2.1.2/BusHandler.vhd | 14 -- releases/tdc_v2.1.2/Channel.vhd | 74 ++------ releases/tdc_v2.1.2/Channel_200.vhd | 140 ++++++--------- releases/tdc_v2.1.2/LogicAnalyser.vhd | 5 +- releases/tdc_v2.1.2/Readout.vhd | 19 +- releases/tdc_v2.1.2/Stretcher.vhd | 4 +- releases/tdc_v2.1.2/TDC.vhd | 48 ++--- releases/tdc_v2.1.2/TriggerHandler.vhd | 3 +- releases/tdc_v2.1.2/cbmtof.vhd | 24 --- releases/tdc_v2.1.2/tdc_components.vhd | 30 ++-- releases/tdc_v2.1.2/tdc_constraints_64.lpf | 153 +++++----------- releases/tdc_v2.1.2/trb3_periph_ADA.vhd | 164 +++++------------ releases/tdc_v2.1.2/trbnet_constraints.lpf | 4 +- .../unimportant_lines_constraints.lpf | 86 +++++++-- 27 files changed, 949 insertions(+), 496 deletions(-) create mode 100644 base/cores/ecp3/PLL/generate_core.tcl create mode 100644 base/cores/ecp3/PLL/generate_ngd.tcl create mode 100644 base/cores/ecp3/PLL/msg_file.log create mode 100644 base/cores/ecp3/PLL/pll_in125_out100.edn create mode 100644 base/cores/ecp3/PLL/pll_in125_out100.ipx create mode 100644 base/cores/ecp3/PLL/pll_in125_out100.jhd create mode 100644 base/cores/ecp3/PLL/pll_in125_out100.lpc create mode 100644 base/cores/ecp3/PLL/pll_in125_out100.sort create mode 100644 base/cores/ecp3/PLL/pll_in125_out100.srp create mode 100644 base/cores/ecp3/PLL/pll_in125_out100.vhd create mode 100644 base/cores/ecp3/PLL/pll_in125_out100_generate.log create mode 100644 base/cores/ecp3/PLL/pll_in125_out100_tmpl.vhd diff --git a/base/cores/ecp3/PLL/generate_core.tcl b/base/cores/ecp3/PLL/generate_core.tcl new file mode 100644 index 0000000..1f59381 --- /dev/null +++ b/base/cores/ecp3/PLL/generate_core.tcl @@ -0,0 +1,100 @@ +#!/usr/local/bin/wish + +proc GetPlatform {} { + global tcl_platform + + set cpu $tcl_platform(machine) + + switch $cpu { + intel - + i*86* { + set cpu ix86 + } + x86_64 { + if {$tcl_platform(wordSize) == 4} { + set cpu ix86 + } + } + } + + switch $tcl_platform(platform) { + windows { + if {$cpu == "amd64"} { + # Do not check wordSize, win32-x64 is an IL32P64 platform. + set cpu x86_64 + } + if {$cpu == "x86_64"} { + return "nt64" + } else { + return "nt" + } + } + unix { + if {$tcl_platform(os) == "Linux"} { + if {$cpu == "x86_64"} { + return "lin64" + } else { + return "lin" + } + } else { + return "sol" + } + } + } + return "nt" +} + +proc GetCmdLine {lpcfile} { + global Para + + if [catch {open $lpcfile r} fileid] { + puts "Cannot open $para_file file!" + exit -1 + } + + seek $fileid 0 start + set default_match 0 + while {[gets $fileid line] >= 0} { + if {[string first "\[Command\]" $line] == 0} { + set default_match 1 + continue + } + if {[string first "\[" $line] == 0} { + set default_match 0 + } + if {$default_match == 1} { + if [regexp {([^=]*)=(.*)} $line match parameter value] { + if [regexp {([ |\t]*;)} $parameter match] {continue} + if [regexp {(.*)[ |\t]*;} $value match temp] { + set Para($parameter) $temp + } else { + set Para($parameter) $value + } + } + } + } + set default_match 0 + close $fileid + + return $Para(cmd_line) +} + +set platformpath [GetPlatform] +set Para(sbp_path) [file dirname [info script]] +set Para(install_dir) $env(TOOLRTF) +set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]" + +set scuba "$Para(FPGAPath)/scuba" +set modulename "pll_in125_out100" +set lang "vhdl" +set lpcfile "$Para(sbp_path)/$modulename.lpc" +set arch "ep5c00" +set cmd_line [GetCmdLine $lpcfile] +set fdcfile "$Para(sbp_path)/$modulename.fdc" +if {[file exists $fdcfile] == 0} { + append scuba " " $cmd_line +} else { + append scuba " " $cmd_line " " -fdc " " $fdcfile +} +set Para(result) [catch {eval exec "$scuba"} msg] +#puts $msg diff --git a/base/cores/ecp3/PLL/generate_ngd.tcl b/base/cores/ecp3/PLL/generate_ngd.tcl new file mode 100644 index 0000000..2321601 --- /dev/null +++ b/base/cores/ecp3/PLL/generate_ngd.tcl @@ -0,0 +1,115 @@ +#!/usr/local/bin/wish + +proc GetPlatform {} { + global tcl_platform + + set cpu $tcl_platform(machine) + + switch $cpu { + intel - + i*86* { + set cpu ix86 + } + x86_64 { + if {$tcl_platform(wordSize) == 4} { + set cpu ix86 + } + } + } + + switch $tcl_platform(platform) { + windows { + if {$cpu == "amd64"} { + # Do not check wordSize, win32-x64 is an IL32P64 platform. + set cpu x86_64 + } + if {$cpu == "x86_64"} { + return "nt64" + } else { + return "nt" + } + } + unix { + if {$tcl_platform(os) == "Linux"} { + if {$cpu == "x86_64"} { + return "lin64" + } else { + return "lin" + } + } else { + return "sol" + } + } + } + return "nt" +} + +set platformpath [GetPlatform] +set Para(sbp_path) [file dirname [info script]] +set Para(install_dir) $env(TOOLRTF) +set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]" +set Para(bin_dir) "[file join $Para(install_dir) bin $platformpath]" + +set Para(ModuleName) "pll_in125_out100" +set Para(Module) "PLL" +set Para(libname) latticeecp3 +set Para(arch_name) ep5c00 +set Para(PartType) "LFE3-150EA" + +set Para(tech_syn) latticeecp3 +set Para(tech_cae) latticeecp3 +set Para(Package) "FPBGA672" +set Para(SpeedGrade) "8" +set Para(FMax) "100" +set fdcfile "$Para(sbp_path)/$Para(ModuleName).fdc" + +#create response file(*.cmd) for Synpwrap +proc CreateCmdFile {} { + global Para + + file mkdir "$Para(sbp_path)/syn_results" + if [catch {open $Para(ModuleName).cmd w} rspFile] { + puts "Cannot create response file $Para(ModuleName).cmd." + exit -1 + } else { + puts $rspFile "PROJECT: $Para(ModuleName) + working_path: \"$Para(sbp_path)/syn_results\" + module: $Para(ModuleName) + verilog_file_list: \"$Para(sbp_path)/$Para(ModuleName).vhd\" + vlog_std_v2001: true + constraint_file_name: \"$Para(sbp_path)/$Para(ModuleName).fdc\" + suffix_name: edn + output_file_name: $Para(ModuleName) + write_prf: true + disable_io_insertion: true + force_gsr: false + frequency: $Para(FMax) + fanout_limit: 50 + retiming: false + pipe: false + part: $Para(PartType) + speed_grade: $Para(SpeedGrade) + " + close $rspFile + } +} + +#synpwrap +CreateCmdFile +set synpwrap "$Para(bin_dir)/synpwrap" +if {[file exists $fdcfile] == 0} { + set Para(result) [catch {eval exec $synpwrap -rem -e $Para(ModuleName) -target $Para(tech_syn)} msg] +} else { + set Para(result) [catch {eval exec $synpwrap -rem -e $Para(ModuleName) -target $Para(tech_syn) -fdc $fdcfile} msg] +} +#puts $msg + +#edif2ngd +set edif2ngd "$Para(FPGAPath)/edif2ngd" +set Para(result) [catch {eval exec $edif2ngd -l $Para(libname) -d $Para(PartType) -nopropwarn \"syn_results/$Para(ModuleName).edn\" $Para(ModuleName).ngo} msg] +#puts $msg + +#ngdbuild +set ngdbuild "$Para(FPGAPath)/ngdbuild" +set Para(result) [catch {eval exec $ngdbuild -addiobuf -dt -a $Para(arch_name) $Para(ModuleName).ngo $Para(ModuleName).ngd} msg] +#puts $msg diff --git a/base/cores/ecp3/PLL/msg_file.log b/base/cores/ecp3/PLL/msg_file.log new file mode 100644 index 0000000..db2ac06 --- /dev/null +++ b/base/cores/ecp3/PLL/msg_file.log @@ -0,0 +1,29 @@ +SCUBA, Version Diamond (64-bit) 3.4.0.80 +Fri Apr 24 12:22:35 2015 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved. + +BEGIN SCUBA Module Synthesis + + Issued command : /opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n pll_in125_out100 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 125 -phase_cntl STATIC -fclkop 100 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw + Circuit name : pll_in125_out100 + Module type : pll + Module Version : 5.7 + Ports : + Inputs : CLK + Outputs : CLKOP, LOCK + I/O buffer : not inserted + EDIF output : pll_in125_out100.edn + VHDL output : pll_in125_out100.vhd + VHDL template : pll_in125_out100_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : not used + Report output : pll_in125_out100.srp + Estimated Resource Usage: + +END SCUBA Module Synthesis + diff --git a/base/cores/ecp3/PLL/pll_in125_out100.edn b/base/cores/ecp3/PLL/pll_in125_out100.edn new file mode 100644 index 0000000..ef12830 --- /dev/null +++ b/base/cores/ecp3/PLL/pll_in125_out100.edn @@ -0,0 +1,167 @@ +(edif pll_in125_out100 + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2015 4 24 12 22 35) + (program "SCUBA" (version "Diamond (64-bit) 3.4.0.80")))) + (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n pll_in125_out100 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 125 -phase_cntl STATIC -fclkop 100 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell EHXPLLF + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port CLKI + (direction INPUT)) + (port CLKFB + (direction INPUT)) + (port RST + (direction INPUT)) + (port RSTK + (direction INPUT)) + (port WRDEL + (direction INPUT)) + (port DRPAI3 + (direction INPUT)) + (port DRPAI2 + (direction INPUT)) + (port DRPAI1 + (direction INPUT)) + (port DRPAI0 + (direction INPUT)) + (port DFPAI3 + (direction INPUT)) + (port DFPAI2 + (direction INPUT)) + (port DFPAI1 + (direction INPUT)) + (port DFPAI0 + (direction INPUT)) + (port FDA3 + (direction INPUT)) + (port FDA2 + (direction INPUT)) + (port FDA1 + (direction INPUT)) + (port FDA0 + (direction INPUT)) + (port CLKOP + (direction OUTPUT)) + (port CLKOS + (direction OUTPUT)) + (port CLKOK + (direction OUTPUT)) + (port CLKOK2 + (direction OUTPUT)) + (port LOCK + (direction OUTPUT)) + (port CLKINTFB + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell pll_in125_out100 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port CLK + (direction INPUT)) + (port CLKOP + (direction OUTPUT)) + (port LOCK + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance scuba_vlo_inst + (viewRef view1 + (cellRef VLO))) + (instance PLLInst_0 + (viewRef view1 + (cellRef EHXPLLF)) + (property FEEDBK_PATH + (string "CLKOP")) + (property CLKOK_BYPASS + (string "DISABLED")) + (property CLKOS_BYPASS + (string "DISABLED")) + (property FREQUENCY_PIN_CLKOP + (string "100.000000")) + (property CLKOP_BYPASS + (string "DISABLED")) + (property CLKOK_INPUT + (string "CLKOP")) + (property DELAY_PWD + (string "DISABLED")) + (property DELAY_VAL + (string "0")) + (property CLKOS_TRIM_DELAY + (string "0")) + (property CLKOS_TRIM_POL + (string "RISING")) + (property CLKOP_TRIM_DELAY + (string "0")) + (property CLKOP_TRIM_POL + (string "RISING")) + (property PHASE_DELAY_CNTL + (string "STATIC")) + (property DUTY + (string "8")) + (property PHASEADJ + (string "0.0")) + (property FREQUENCY_PIN_CLKI + (string "125.000000")) + (property CLKOK_DIV + (string "2")) + (property CLKOP_DIV + (string "8")) + (property CLKFB_DIV + (string "4")) + (property CLKI_DIV + (string "5")) + (property FIN + (string "125.000000"))) + (net scuba_vlo + (joined + (portRef Z (instanceRef scuba_vlo_inst)) + (portRef FDA3 (instanceRef PLLInst_0)) + (portRef FDA2 (instanceRef PLLInst_0)) + (portRef FDA1 (instanceRef PLLInst_0)) + (portRef FDA0 (instanceRef PLLInst_0)) + (portRef WRDEL (instanceRef PLLInst_0)) + (portRef DFPAI3 (instanceRef PLLInst_0)) + (portRef DFPAI2 (instanceRef PLLInst_0)) + (portRef DFPAI1 (instanceRef PLLInst_0)) + (portRef DFPAI0 (instanceRef PLLInst_0)) + (portRef DRPAI3 (instanceRef PLLInst_0)) + (portRef DRPAI2 (instanceRef PLLInst_0)) + (portRef DRPAI1 (instanceRef PLLInst_0)) + (portRef DRPAI0 (instanceRef PLLInst_0)) + (portRef RSTK (instanceRef PLLInst_0)) + (portRef RST (instanceRef PLLInst_0)))) + (net LOCK + (joined + (portRef LOCK) + (portRef LOCK (instanceRef PLLInst_0)))) + (net CLKOP + (joined + (portRef CLKOP) + (portRef CLKFB (instanceRef PLLInst_0)) + (portRef CLKOP (instanceRef PLLInst_0)))) + (net CLK + (joined + (portRef CLK) + (portRef CLKI (instanceRef PLLInst_0)))))))) + (design pll_in125_out100 + (cellRef pll_in125_out100 + (libraryRef ORCLIB))) +) diff --git a/base/cores/ecp3/PLL/pll_in125_out100.ipx b/base/cores/ecp3/PLL/pll_in125_out100.ipx new file mode 100644 index 0000000..5f84e73 --- /dev/null +++ b/base/cores/ecp3/PLL/pll_in125_out100.ipx @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/base/cores/ecp3/PLL/pll_in125_out100.jhd b/base/cores/ecp3/PLL/pll_in125_out100.jhd new file mode 100644 index 0000000..e69de29 diff --git a/base/cores/ecp3/PLL/pll_in125_out100.lpc b/base/cores/ecp3/PLL/pll_in125_out100.lpc new file mode 100644 index 0000000..dddc782 --- /dev/null +++ b/base/cores/ecp3/PLL/pll_in125_out100.lpc @@ -0,0 +1,69 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN672C +SpeedGrade=8 +Package=FPBGA672 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PLL +CoreRevision=5.7 +ModuleName=pll_in125_out100 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=04/24/2015 +Time=12:22:34 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=None +Order=None +IO=0 +Type=ehxpllb +mode=normal +IFrq=125 +Div=5 +ClkOPBp=0 +Post=8 +U_OFrq=100 +OP_Tol=0.0 +OFrq=100.000000 +DutyTrimP=Rising +DelayMultP=0 +fb_mode=CLKOP +Mult=4 +Phase=0.0 +Duty=8 +DelayMultS=0 +DPD=50% Duty +DutyTrimS=Rising +DelayMultD=0 +ClkOSDelay=0 +PhaseDuty=Static +CLKOK_INPUT=CLKOP +SecD=2 +U_KFrq=50 +OK_Tol=0.0 +KFrq= +ClkRst=0 +PCDR=0 +FINDELA=0 +VcoRate= +Bandwidth=3.424318 +;DelayControl=No +EnCLKOS=0 +ClkOSBp=0 +EnCLKOK=0 +ClkOKBp=0 +enClkOK2=0 + +[Command] +cmd_line= -w -n pll_in125_out100 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 125 -phase_cntl STATIC -fclkop 100 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw diff --git a/base/cores/ecp3/PLL/pll_in125_out100.sort b/base/cores/ecp3/PLL/pll_in125_out100.sort new file mode 100644 index 0000000..ad4d4e0 --- /dev/null +++ b/base/cores/ecp3/PLL/pll_in125_out100.sort @@ -0,0 +1 @@ +pll_in125_out100.vhd diff --git a/base/cores/ecp3/PLL/pll_in125_out100.srp b/base/cores/ecp3/PLL/pll_in125_out100.srp new file mode 100644 index 0000000..ddedf83 --- /dev/null +++ b/base/cores/ecp3/PLL/pll_in125_out100.srp @@ -0,0 +1,26 @@ +SCUBA, Version Diamond (64-bit) 3.4.0.80 +Fri Apr 24 12:22:35 2015 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved. + + Issued command : /opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n pll_in125_out100 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 125 -phase_cntl STATIC -fclkop 100 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw + Circuit name : pll_in125_out100 + Module type : pll + Module Version : 5.7 + Ports : + Inputs : CLK + Outputs : CLKOP, LOCK + I/O buffer : not inserted + EDIF output : pll_in125_out100.edn + VHDL output : pll_in125_out100.vhd + VHDL template : pll_in125_out100_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : not used + Report output : pll_in125_out100.srp + Element Usage : + EHXPLLF : 1 + Estimated Resource Usage: diff --git a/base/cores/ecp3/PLL/pll_in125_out100.vhd b/base/cores/ecp3/PLL/pll_in125_out100.vhd new file mode 100644 index 0000000..468e91a --- /dev/null +++ b/base/cores/ecp3/PLL/pll_in125_out100.vhd @@ -0,0 +1,99 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80 +-- Module Version: 5.7 +--/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n pll_in125_out100 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 125 -phase_cntl STATIC -fclkop 100 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw + +-- Fri Apr 24 12:22:35 2015 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity pll_in125_out100 is + port ( + CLK: in std_logic; + CLKOP: out std_logic; + LOCK: out std_logic); + attribute dont_touch : boolean; + attribute dont_touch of pll_in125_out100 : entity is true; +end pll_in125_out100; + +architecture Structure of pll_in125_out100 is + + -- internal signal declarations + signal CLKOP_t: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component EHXPLLF + generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String; + DELAY_PWD : in String; DELAY_VAL : in Integer; + CLKOS_TRIM_DELAY : in Integer; + CLKOS_TRIM_POL : in String; + CLKOP_TRIM_DELAY : in Integer; + CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String; + CLKOS_BYPASS : in String; CLKOP_BYPASS : in String; + PHASE_DELAY_CNTL : in String; DUTY : in Integer; + PHASEADJ : in String; CLKOK_DIV : in Integer; + CLKOP_DIV : in Integer; CLKFB_DIV : in Integer; + CLKI_DIV : in Integer; FIN : in String); + port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic; + RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic; + DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic; + DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic; + DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic; + FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic; + CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic; + LOCK: out std_logic; CLKINTFB: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + attribute FREQUENCY_PIN_CLKOP : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "100.000000"; + attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "125.000000"; + attribute syn_keep : boolean; + attribute syn_noprune : boolean; + attribute syn_noprune of Structure : architecture is true; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + PLLInst_0: EHXPLLF + generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED", + CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED", + CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=> 0, + CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING", + CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING", + PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0", + CLKOK_DIV=> 2, CLKOP_DIV=> 8, CLKFB_DIV=> 4, CLKI_DIV=> 5, + FIN=> "125.000000") + port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>scuba_vlo, + RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, + DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, + DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, + DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo, + FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t, + CLKOS=>open, CLKOK=>open, CLKOK2=>open, LOCK=>LOCK, + CLKINTFB=>open); + + CLKOP <= CLKOP_t; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of pll_in125_out100 is + for Structure + for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/base/cores/ecp3/PLL/pll_in125_out100_generate.log b/base/cores/ecp3/PLL/pll_in125_out100_generate.log new file mode 100644 index 0000000..d80c65e --- /dev/null +++ b/base/cores/ecp3/PLL/pll_in125_out100_generate.log @@ -0,0 +1,44 @@ +Starting process: Module + +Starting process: + +SCUBA, Version Diamond (64-bit) 3.4.0.80 +Fri Apr 24 12:22:35 2015 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved. + +BEGIN SCUBA Module Synthesis + + Issued command : /opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n pll_in125_out100 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 125 -phase_cntl STATIC -fclkop 100 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw + Circuit name : pll_in125_out100 + Module type : pll + Module Version : 5.7 + Ports : + Inputs : CLK + Outputs : CLKOP, LOCK + I/O buffer : not inserted + EDIF output : pll_in125_out100.edn + VHDL output : pll_in125_out100.vhd + VHDL template : pll_in125_out100_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : not used + Report output : pll_in125_out100.srp + Estimated Resource Usage: + +END SCUBA Module Synthesis + +File: pll_in125_out100.lpc created. + + +End process: completed successfully. + + +Total Warnings: 0 + +Total Errors: 0 + + diff --git a/base/cores/ecp3/PLL/pll_in125_out100_tmpl.vhd b/base/cores/ecp3/PLL/pll_in125_out100_tmpl.vhd new file mode 100644 index 0000000..2edf74f --- /dev/null +++ b/base/cores/ecp3/PLL/pll_in125_out100_tmpl.vhd @@ -0,0 +1,12 @@ +-- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.4.0.80 +-- Module Version: 5.7 +-- Fri Apr 24 12:22:35 2015 + +-- parameterized module component declaration +component pll_in125_out100 + port (CLK: in std_logic; CLKOP: out std_logic; LOCK: out std_logic); +end component; + +-- parameterized module component instance +__ : pll_in125_out100 + port map (CLK=>__, CLKOP=>__, LOCK=>__); diff --git a/releases/ReleaseNotes.org b/releases/ReleaseNotes.org index 38ebebc..c9cb073 100644 --- a/releases/ReleaseNotes.org +++ b/releases/ReleaseNotes.org @@ -8,10 +8,17 @@ |-------------+----------------+----------------------------------------------------------------------------------| | | | <80> | |-------------+----------------+----------------------------------------------------------------------------------| +| tdc\_v2.2 | 08.03.2015 | Faster clock (400 MHz) for the delay line is used. | +|-------------+----------------+----------------------------------------------------------------------------------| | tdc\_v2.1.2 | 28.01.2015 | In case of a missing reference time a header error bit is set and DAQ keeps running. | | | | Grass hits in ToT with calbration trigger is removed. The ToT mean value - 10ns gives the stretching offset of the channel. | | | | Channel invert bits are implemented. | | | | Trigger window bugfix. | +| | | Resource usages in Channel_200 and Channel entity are decreased. | +| | | Hit detection is increased to 2 bits. | +| | | Coarse counter number is increased to channel number for better timing. | +| | | Instead of the internal oscillator 125MHz clock input is used for the calibration. | +| | | | |-------------+----------------+----------------------------------------------------------------------------------| | tdc\_v2.1.1 | 28.01.2015 | The dead time of the TDC is decreased to 20ns. | | | | Small bug with "Light Mode" is removed. | diff --git a/releases/tdc_v2.1.2/BusHandler.vhd b/releases/tdc_v2.1.2/BusHandler.vhd index d0d7b65..1801f27 100644 --- a/releases/tdc_v2.1.2/BusHandler.vhd +++ b/releases/tdc_v2.1.2/BusHandler.vhd @@ -4,8 +4,6 @@ use ieee.numeric_std.all; library work; use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb3_components.all; entity BusHandler is generic ( @@ -68,18 +66,6 @@ begin end if; end process READ_WRITE_RESPONSE; - - --FifoWriteSignal : process (CLK) - --begin - -- if rising_edge(CLK) then - -- if RESET = '1' then - -- unknown_addr_reg <= '0'; - -- else - -- unknown_addr_reg <= '1'; - -- end if; - -- end if; - --end process FifoWriteSignal; - DATA_OUT <= data_out_reg; DATAREADY_OUT <= data_ready_reg; UNKNOWN_ADDR_OUT <= unknown_addr_reg; diff --git a/releases/tdc_v2.1.2/Channel.vhd b/releases/tdc_v2.1.2/Channel.vhd index fce4642..665dfed 100644 --- a/releases/tdc_v2.1.2/Channel.vhd +++ b/releases/tdc_v2.1.2/Channel.vhd @@ -5,7 +5,6 @@ use ieee.numeric_std.all; library work; use work.trb_net_std.all; use work.trb_net_components.all; -use work.trb3_components.all; use work.tdc_components.all; use work.config.all; @@ -32,16 +31,9 @@ entity Channel is FIFO_DATA_VALID_OUT : out std_logic; FIFO_ALMOST_FULL_OUT : out std_logic; -- fifo almost full signal ringbuffer overwrite detection FIFO_EMPTY_OUT : out std_logic; - FIFO_FULL_OUT : out std_logic; - FIFO_ALMOST_EMPTY_OUT : out std_logic; RING_BUFFER_FULL_THRES_IN : in std_logic_vector(6 downto 0); COARSE_COUNTER_IN : in std_logic_vector(10 downto 0); EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0); --- - VALID_TIMING_TRG_IN : in std_logic; - VALID_NOTIMING_TRG_IN : in std_logic; - SPIKE_DETECTED_IN : in std_logic; - MULTI_TMG_TRG_IN : in std_logic; -- EPOCH_WRITE_EN_IN : in std_logic; LOST_HIT_NUMBER : out std_logic_vector(23 downto 0); @@ -62,8 +54,8 @@ architecture Channel of Channel is ------------------------------------------------------------------------------- -- time stamp - signal coarse_cntr_reg : std_logic_vector(10 downto 0); - signal epoch_cntr_reg : std_logic_vector(27 downto 0); +-- signal coarse_cntr_reg : std_logic_vector(10 downto 0); +-- signal epoch_cntr_reg : std_logic_vector(27 downto 0); signal trg_win_end_tdc : std_logic; signal trg_win_end_rdo : std_logic; @@ -77,13 +69,11 @@ architecture Channel of Channel is signal buf_empty : std_logic; signal buf_empty_reg : std_logic; signal buf_full : std_logic; - signal buf_almost_full : std_logic; -- fron readout signal rd_en_reg : std_logic; -- debug - signal sync_q : std_logic_vector(2 downto 0); signal hit_pulse_100 : std_logic; signal encoder_finished : std_logic; signal encoder_finished_100 : std_logic; @@ -108,15 +98,15 @@ architecture Channel of Channel is attribute syn_keep : boolean; attribute syn_keep of trg_win_end_tdc : signal is true; attribute syn_keep of trg_win_end_rdo : signal is true; - attribute syn_keep of epoch_cntr_reg : signal is true; +-- attribute syn_keep of epoch_cntr_reg : signal is true; attribute syn_preserve : boolean; - attribute syn_preserve of coarse_cntr_reg : signal is true; +-- attribute syn_preserve of coarse_cntr_reg : signal is true; attribute syn_preserve of trg_win_end_tdc : signal is true; - attribute syn_preserve of epoch_cntr_reg : signal is true; +-- attribute syn_preserve of epoch_cntr_reg : signal is true; attribute nomerge : string; attribute nomerge of trg_win_end_tdc : signal is "true"; attribute nomerge of trg_win_end_rdo : signal is "true"; - attribute nomerge of epoch_cntr_reg : signal is "true"; +-- attribute nomerge of epoch_cntr_reg : signal is "true"; ------------------------------------------------------------------------------- @@ -137,17 +127,12 @@ begin HIT_EDGE_IN => HIT_EDGE_IN, TRG_WIN_END_TDC_IN => trg_win_end_tdc, TRG_WIN_END_RDO_IN => trg_win_end_rdo, - EPOCH_COUNTER_IN => epoch_cntr_reg, - COARSE_COUNTER_IN => coarse_cntr_reg, - READ_EN_IN => READ_EN_IN, + EPOCH_COUNTER_IN => EPOCH_COUNTER_IN, -- epoch_cntr_reg, + COARSE_COUNTER_IN => COARSE_COUNTER_IN, -- coarse_cntr_reg, FIFO_DATA_OUT => ch_data, FIFO_DATA_VALID_OUT => ch_data_valid, FIFO_ALMOST_FULL_OUT => FIFO_ALMOST_FULL_OUT, RING_BUFFER_FULL_THRES_IN => RING_BUFFER_FULL_THRES_IN, - VALID_TIMING_TRG_IN => VALID_TIMING_TRG_IN, - VALID_NOTIMING_TRG_IN => VALID_NOTIMING_TRG_IN, - SPIKE_DETECTED_IN => SPIKE_DETECTED_IN, - MULTI_TMG_TRG_IN => MULTI_TMG_TRG_IN, EPOCH_WRITE_EN_IN => EPOCH_WRITE_EN_IN, ENCODER_START_OUT => encoder_start, ENCODER_FINISHED_OUT => encoder_finished, @@ -196,7 +181,6 @@ begin FIFO_DATA_OUT <= buf_data; FIFO_DATA_VALID_OUT <= buf_data_valid; FIFO_EMPTY_OUT <= buf_empty; - FIFO_ALMOST_EMPTY_OUT <= '0'; trg_win_end_tdc <= TRG_WIN_END_TDC_IN; trg_win_end_rdo <= TRG_WIN_END_RDO_IN; rd_en_reg <= READ_EN_IN when rising_edge(CLK_100); @@ -230,44 +214,20 @@ begin RESET_B_IN => RESET_100, PULSE_B_OUT => fifo_write_100); - CoarseCounter : ShiftRegisterSISO - generic map ( - DEPTH => 1, - WIDTH => 11) - port map ( - CLK => CLK_200, - D_IN => COARSE_COUNTER_IN, - D_OUT => coarse_cntr_reg); + --CoarseCounter : ShiftRegisterSISO + -- generic map ( + -- DEPTH => 1, + -- WIDTH => 11) + -- port map ( + -- CLK => CLK_200, + -- D_IN => COARSE_COUNTER_IN, + -- D_OUT => coarse_cntr_reg); - epoch_cntr_reg <= EPOCH_COUNTER_IN when rising_edge(CLK_200); + --epoch_cntr_reg <= EPOCH_COUNTER_IN when rising_edge(CLK_200); ------------------------------------------------------------------------------- -- DEBUG Counters ------------------------------------------------------------------------------- - --purpose: Hit Signal Synchroniser - --sync_q(0) <= HIT_IN when rising_edge(CLK_100); - --sync_q(1) <= sync_q(0) when rising_edge(CLK_100); - --sync_q(2) <= sync_q(1) when rising_edge(CLK_100); - - --risingEdgeDetect_1 : risingEdgeDetect - -- port map ( - -- CLK => CLK_100, - -- SIGNAL_IN => sync_q(2), - -- PULSE_OUT => hit_pulse_100); - - ----purpose: Counts the detected hits - --Hit_Detect_Counter : process (CLK_100) - --begin - -- if rising_edge(CLK_100) then - -- if RESET_COUNTERS = '1' then - -- hit_detect_cntr <= (others => '0'); - -- elsif hit_pulse_100 = '1' then - -- hit_detect_cntr <= hit_detect_cntr + to_unsigned(1, 31); - -- end if; - -- end if; - --end process Hit_Detect_Counter; - - --HIT_DETECT_NUMBER <= std_logic_vector(hit_detect_cntr) when rising_edge(CLK_100); HIT_DETECT_NUMBER <= (others => '0'); -- Moved to TDC.vhd gen_DEBUG : if DEBUG = c_YES generate diff --git a/releases/tdc_v2.1.2/Channel_200.vhd b/releases/tdc_v2.1.2/Channel_200.vhd index 523c47f..4a21070 100644 --- a/releases/tdc_v2.1.2/Channel_200.vhd +++ b/releases/tdc_v2.1.2/Channel_200.vhd @@ -5,7 +5,7 @@ -- File : Channel_200.vhd -- Author : c.ugur@gsi.de -- Created : 2012-08-28 --- Last update: 2015-03-20 +-- Last update: 2015-04-24 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- @@ -16,8 +16,6 @@ use ieee.numeric_std.all; library work; use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb3_components.all; use work.tdc_components.all; use work.config.all; @@ -40,16 +38,10 @@ entity Channel_200 is TRG_WIN_END_RDO_IN : in std_logic; -- trigger window end strobe EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0); -- system coarse counter COARSE_COUNTER_IN : in std_logic_vector(10 downto 0); - READ_EN_IN : in std_logic; -- read en signal FIFO_DATA_OUT : out std_logic_vector(35 downto 0); -- fifo data out FIFO_DATA_VALID_OUT : out std_logic; -- fifo data valid signal FIFO_ALMOST_FULL_OUT : out std_logic; -- fifo almost full signal ringbuffer overwrite detection RING_BUFFER_FULL_THRES_IN : in std_logic_vector(6 downto 0); -- ring buffer almost full threshold --- - VALID_TIMING_TRG_IN : in std_logic; - VALID_NOTIMING_TRG_IN : in std_logic; - SPIKE_DETECTED_IN : in std_logic; - MULTI_TMG_TRG_IN : in std_logic; -- EPOCH_WRITE_EN_IN : in std_logic; ENCODER_START_OUT : out std_logic; @@ -70,31 +62,22 @@ architecture Channel_200 of Channel_200 is -- hit detection signal result_2_r : std_logic := '0'; + signal result_3_r : std_logic := '0'; signal hit_detect : std_logic := '0'; signal hit_detect_r : std_logic; signal hit_detect_2r : std_logic; signal edge_type : std_logic := '0'; - signal rising_edge_written : std_logic := '0'; - signal memory : std_logic_vector(7 downto 0) := (others => '0'); - signal wr_ptr : integer range 0 to 7 := 0; - signal rd_ptr : integer range 0 to 7 := 0; + signal memory : std_logic_vector(1 downto 0) := (others => '0'); + signal wr_ptr : integer range 0 to 1 := 0; + signal rd_ptr : integer range 0 to 1 := 0; -- time stamp - signal time_stamp : std_logic_vector(10 downto 0); - signal time_stamp_r : std_logic_vector(10 downto 0); - signal time_stamp_2r : std_logic_vector(10 downto 0); - signal time_stamp_3r : std_logic_vector(10 downto 0); - signal time_stamp_4r : std_logic_vector(10 downto 0); - signal time_stamp_5r : std_logic_vector(10 downto 0); - signal time_stamp_6r : std_logic_vector(10 downto 0); - signal coarse_cntr_r : std_logic_vector(10 downto 0); - signal coarse_cntr_overflow : std_logic; - signal coarse_cntr_overflow_r : std_logic; - signal coarse_cntr_overflow_2r : std_logic; - signal coarse_cntr_overflow_3r : std_logic; - signal coarse_cntr_overflow_4r : std_logic; - signal coarse_cntr_overflow_5r : std_logic; - signal coarse_cntr_overflow_6r : std_logic; + signal time_stamp_array : std_logic_vector_array_11(3 downto 0); + signal ts_wr_ptr : integer range 0 to 3 := 0; + signal ts_rd_ptr : integer range 0 to 3 := 0; + signal coarse_cntr_r : std_logic_vector(10 downto 0); + signal coarse_cntr_overflow : std_logic_vector(0 downto 0); + signal coarse_cntr_overflow_r : std_logic_vector(0 downto 0); -- encoder signal encoder_start : std_logic; @@ -104,7 +87,6 @@ architecture Channel_200 of Channel_200 is -- epoch counter signal epoch_cntr : std_logic_vector(27 downto 0) := (others => '0'); - signal epoch_cntr_r : std_logic_vector(27 downto 0) := (others => '0'); signal epoch_cntr_updated : std_logic := '0'; signal epoch_value : std_logic_vector(35 downto 0); @@ -138,7 +120,6 @@ architecture Channel_200 of Channel_200 is signal write_stop_b : std_logic := '0'; signal write_data_flag_fsm : std_logic; signal write_data_flag : std_logic := '0'; - signal trg_win_end_tdc_flag_fsm : std_logic; signal trg_win_end_tdc_flag : std_logic := '0'; signal fsm_wr_debug_fsm : std_logic_vector(3 downto 0); signal fsm_wr_debug : std_logic_vector(3 downto 0); @@ -166,7 +147,7 @@ begin -- Channel_200 FC : Adder_304 port map ( CLK => CLK_200, - RESET => RESET_200, + RESET => '0', --RESET_200, DataA => data_a, DataB => data_b, ClkEn => ff_array_en, @@ -179,7 +160,7 @@ begin -- Channel_200 FC : Adder_304 port map ( CLK => CLK_200, - RESET => RESET_200, + RESET => '0', --RESET_200, DataA => data_a, DataB => data_b, CLKEn => ff_array_en, @@ -191,14 +172,15 @@ begin -- Channel_200 ff_array_en <= not(hit_detect or hit_detect_r); -- or hit_detect_2r); result_2_r <= result(2) when rising_edge(CLK_200); - hit_detect <= (not result_2_r) and result(2); -- detects the hit by + result_3_r <= result(3) when rising_edge(CLK_200); + hit_detect <= ((not result_2_r) and result(2)) or ((not result_3_r) and result(3)); -- detects the hit by -- comparing the -- previous state of the -- hit detection bit hit_detect_r <= hit_detect when rising_edge(CLK_200); hit_detect_2r <= hit_detect_r when rising_edge(CLK_200); - coarse_cntr_r <= COARSE_COUNTER_IN when rising_edge(CLK_200); +-- coarse_cntr_r <= COARSE_COUNTER_IN when rising_edge(CLK_200); encoder_start <= hit_detect; --hit_detect_r; ENCODER_START_OUT <= encoder_start; @@ -206,31 +188,13 @@ begin -- Channel_200 edge_type <= '1'; end generate isReferenceEdge; - --isChannelEdge : if REFERENCE = c_NO and (DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3) generate - -- EdgeTypeCapture : process (CLK_200) is - -- begin -- process EdgeTypeCapture - -- if rising_edge(CLK_200) then - -- if write_data = '1' and edge_type = '1' then - -- rising_edge_written <= '1'; - -- elsif write_data = '1' and edge_type = '0' then - -- rising_edge_written <= '0'; - -- end if; - -- if HIT_EDGE_IN = '1' and edge_type = '0' then - -- edge_type <= '1'; - -- elsif rising_edge_written = '1' then - -- edge_type <= '0'; - -- end if; - -- end if; - -- end process EdgeTypeCapture; - --end generate isChannelEdge; - isChannelEdge : if REFERENCE = c_NO and (DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3) generate EdgeTypeCapture : process (CLK_200) is begin -- process EdgeTypeCapture if rising_edge(CLK_200) then if hit_detect_2r = '1' then memory(wr_ptr) <= HIT_EDGE_IN; - if wr_ptr = 7 then + if wr_ptr = 1 then wr_ptr <= 0; else wr_ptr <= wr_ptr + 1; @@ -238,7 +202,7 @@ begin -- Channel_200 end if; if encoder_finished = '1' then edge_type <= memory(rd_ptr); - if rd_ptr = 7 then + if rd_ptr = 1 then rd_ptr <= 0; else rd_ptr <= rd_ptr + 1; @@ -252,34 +216,42 @@ begin -- Channel_200 begin if rising_edge(CLK_200) then if hit_detect_r = '1' then - time_stamp <= coarse_cntr_r; + time_stamp_array(ts_wr_ptr) <= COARSE_COUNTER_IN; + if ts_wr_ptr = 3 then + ts_wr_ptr <= 0; + else + ts_wr_ptr <= ts_wr_ptr + 1; + end if; + end if; + if write_data = '1' then + if ts_rd_ptr = 3 then + ts_rd_ptr <= 0; + else + ts_rd_ptr <= ts_rd_ptr + 1; + end if; end if; - time_stamp_r <= time_stamp; - time_stamp_2r <= time_stamp_r; - time_stamp_3r <= time_stamp_2r; - time_stamp_4r <= time_stamp_3r; - time_stamp_5r <= time_stamp_4r; - time_stamp_6r <= time_stamp_5r; end if; end process TimeStampCapture; - CoarseCounterOverflow : entity work.fallingEdgeDetect + CoarseCounterOverflow_1 : entity work.fallingEdgeDetect port map ( CLK => CLK_200, - SIGNAL_IN => coarse_cntr_r(10), - PULSE_OUT => coarse_cntr_overflow); - - coarse_cntr_overflow_r <= coarse_cntr_overflow when rising_edge(CLK_200); - coarse_cntr_overflow_2r <= coarse_cntr_overflow_r when rising_edge(CLK_200); - coarse_cntr_overflow_3r <= coarse_cntr_overflow_2r when rising_edge(CLK_200); - coarse_cntr_overflow_4r <= coarse_cntr_overflow_3r when rising_edge(CLK_200); - coarse_cntr_overflow_5r <= coarse_cntr_overflow_4r when rising_edge(CLK_200); - coarse_cntr_overflow_6r <= coarse_cntr_overflow_5r when rising_edge(CLK_200); + SIGNAL_IN => COARSE_COUNTER_IN(10), -- coarse_cntr_r(10), + PULSE_OUT => coarse_cntr_overflow(0)); + CoarseCounterOverflow_2: entity work.ShiftRegisterSISO + generic map ( + DEPTH => 6, + WIDTH => 1) + port map ( + CLK => CLK_200, + D_IN => coarse_cntr_overflow, + D_OUT => coarse_cntr_overflow_r); + EpochCounterCapture : process (CLK_200) begin if rising_edge(CLK_200) then - if coarse_cntr_overflow_6r = '1' then + if coarse_cntr_overflow_r(0) = '1' then epoch_cntr <= EPOCH_COUNTER_IN; epoch_cntr_updated <= '1'; elsif write_epoch = '1' then @@ -388,16 +360,18 @@ begin -- Channel_200 -- Readout fsm FSM_CLK : process (CLK_200) begin - if RESET_200 = '1' then - FSM_WR_CURRENT <= WRITE_EPOCH_WORD; - elsif rising_edge(CLK_200) then - FSM_WR_CURRENT <= FSM_WR_NEXT; - write_epoch <= write_epoch_fsm; - write_data <= write_data_fsm; - write_stop_a <= write_stop_a_fsm; - write_stop_b <= write_stop_b_fsm; - write_data_flag <= write_data_flag_fsm; - fsm_wr_debug <= fsm_wr_debug_fsm; + if rising_edge(CLK_200) then + if RESET_200 = '1' then + FSM_WR_CURRENT <= WRITE_EPOCH_WORD; + else + FSM_WR_CURRENT <= FSM_WR_NEXT; + write_epoch <= write_epoch_fsm; + write_data <= write_data_fsm; + write_stop_a <= write_stop_a_fsm; + write_stop_b <= write_stop_b_fsm; + write_data_flag <= write_data_flag_fsm; + fsm_wr_debug <= fsm_wr_debug_fsm; + end if; end if; end process FSM_CLK; @@ -536,7 +510,7 @@ begin -- Channel_200 ringBuffer_data_in(28 downto 22) <= std_logic_vector(to_unsigned(CHANNEL_ID, 7)); -- channel number ringBuffer_data_in(21 downto 12) <= encoder_data_out; -- fine time from the encoder ringBuffer_data_in(11) <= edge_type; -- rising '1' or falling '0' edge - ringBuffer_data_in(10 downto 0) <= time_stamp_6r; -- hit time stamp + ringBuffer_data_in(10 downto 0) <= time_stamp_array(ts_rd_ptr); -- hit time stamp ringBuffer_wr_en <= '1'; elsif write_stop_a = '1' then ringBuffer_data_in(35 downto 32) <= x"f"; diff --git a/releases/tdc_v2.1.2/LogicAnalyser.vhd b/releases/tdc_v2.1.2/LogicAnalyser.vhd index 96035c0..3c6091d 100644 --- a/releases/tdc_v2.1.2/LogicAnalyser.vhd +++ b/releases/tdc_v2.1.2/LogicAnalyser.vhd @@ -5,7 +5,7 @@ -- File : LogicAnalyser.vhd -- Author : cugur@gsi.de -- Created : 2012-10-26 --- Last update: 2014-12-04 +-- Last update: 2015-04-21 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- @@ -15,9 +15,6 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb3_components.all; entity LogicAnalyser is generic ( diff --git a/releases/tdc_v2.1.2/Readout.vhd b/releases/tdc_v2.1.2/Readout.vhd index eded840..234eac9 100644 --- a/releases/tdc_v2.1.2/Readout.vhd +++ b/releases/tdc_v2.1.2/Readout.vhd @@ -5,7 +5,7 @@ -- File : Readout.vhd -- Author : cugur@gsi.de -- Created : 2012-10-25 --- Last update: 2015-02-10 +-- Last update: 2015-04-21 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- @@ -18,8 +18,6 @@ use ieee.numeric_std.all; library work; use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb3_components.all; use work.tdc_components.all; entity Readout is @@ -38,8 +36,6 @@ entity Readout is CH_DATA_VALID_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); CH_ALMOST_FULL_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); CH_EMPTY_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); - CH_FULL_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); - CH_ALMOST_EMPTY_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); -- from the endpoint TRG_DATA_VALID_IN : in std_logic; VALID_TIMING_TRG_IN : in std_logic; @@ -52,7 +48,6 @@ entity Readout is TRG_CODE_IN : in std_logic_vector(7 downto 0); TRG_INFORMATION_IN : in std_logic_vector(23 downto 0); TRG_TYPE_IN : in std_logic_vector(3 downto 0); - DATA_LIMIT_IN : in unsigned(7 downto 0); -- to the endpoint TRG_RELEASE_OUT : out std_logic; TRG_STATUSBIT_OUT : out std_logic_vector(31 downto 0); @@ -73,8 +68,6 @@ entity Readout is MISSING_REF_TIME_IN : in std_logic; -- miscellaneous LIGHT_MODE_IN : in std_logic; - COARSE_COUNTER_IN : in std_logic_vector(10 downto 0); - EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0); DEBUG_MODE_EN_IN : in std_logic; STATISTICS_OUT : out std_logic_vector_array_24(0 to 15); READOUT_DEBUG : out std_logic_vector(31 downto 0) @@ -324,10 +317,9 @@ begin -- behavioral READ_EN_OUT <= rd_en; RD_FSM_PROC : process (RD_CURRENT, VALID_TIMING_TRG_IN, VALID_NOTIMING_TRG_IN, TRG_DATA_VALID_IN, - INVALID_TRG_IN, TMGTRG_TIMEOUT_IN, TRG_TYPE_IN, finished, - SPURIOUS_TRG_IN, stop_status, DEBUG_MODE_EN_IN, fifo_nr_rd, - TRG_WIN_END_RDO_IN, buf_delay, CH_EMPTY_IN, CLK_100, buffer_transfer_done_2r, - MISSING_REF_TIME_IN) + INVALID_TRG_IN, TMGTRG_TIMEOUT_IN, TRG_TYPE_IN, SPURIOUS_TRG_IN, stop_status, + DEBUG_MODE_EN_IN, fifo_nr_rd, TRG_WIN_END_RDO_IN, buf_delay, CH_EMPTY_IN, + buffer_transfer_done_2r, MISSING_REF_TIME_IN, wrong_readout, isNoHit_r) begin RD_NEXT <= RD_CURRENT; @@ -492,7 +484,8 @@ begin -- behavioral end if; end process WR_FSM_CLK; - WR_FSM : process (WR_CURRENT, fifo_nr_wr, start_write, CH_DATA_VALID_IN, ch_data_2r) + WR_FSM : process (WR_CURRENT, fifo_nr_wr, start_write, CH_DATA_VALID_IN, ch_data_2r, + isNoHit_r) begin diff --git a/releases/tdc_v2.1.2/Stretcher.vhd b/releases/tdc_v2.1.2/Stretcher.vhd index 6938dd2..c35f444 100644 --- a/releases/tdc_v2.1.2/Stretcher.vhd +++ b/releases/tdc_v2.1.2/Stretcher.vhd @@ -5,7 +5,7 @@ -- File : Stretcher.vhd -- Author : cugur@gsi.de -- Created : 2012-11-07 --- Last update: 2015-02-17 +-- Last update: 2015-04-21 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- @@ -40,7 +40,7 @@ begin -- behavioral pulse_a_in(DEPTH*i) <= PULSE_IN(i-1); pulse_a_in(DEPTH*i-1 downto DEPTH*(i-1)+1) <= pulse_b_out(DEPTH*i-1 downto DEPTH*(i-1)+1); pulse_b_in(DEPTH*i-1 downto DEPTH*(i-1)+1) <= pulse_a_out(DEPTH*i-1 downto DEPTH*(i-1)+1); - PULSE_OUT(i-1) <= transport not pulse_a_out(DEPTH*(i-1)) after 28 ns; + PULSE_OUT(i-1) <= transport not pulse_a_out(DEPTH*(i-1)) after 15 ns; end generate GEN; Stretcher_A_1 : entity work.Stretcher_A diff --git a/releases/tdc_v2.1.2/TDC.vhd b/releases/tdc_v2.1.2/TDC.vhd index 30beec0..4460dec 100644 --- a/releases/tdc_v2.1.2/TDC.vhd +++ b/releases/tdc_v2.1.2/TDC.vhd @@ -5,9 +5,8 @@ use ieee.math_real.all; library work; use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb3_components.all; use work.config.all; +use work.trb3_components.all; use work.tdc_components.all; use work.tdc_version.all; @@ -103,9 +102,9 @@ architecture TDC of TDC is signal reset_tdc_i : std_logic; signal reset_tdc : std_logic; -- Coarse counters - signal coarse_cntr : std_logic_vector_array_11(0 to 8); + signal coarse_cntr : std_logic_vector_array_11(0 to CHANNEL_NUMBER); signal coarse_cntr_reset : std_logic; - signal coarse_cntr_reset_r : std_logic_vector(8 downto 0); + signal coarse_cntr_reset_r : std_logic_vector(CHANNEL_NUMBER downto 0); -- Slow control signal logic_anal_control : std_logic_vector(3 downto 0); signal debug_mode_en : std_logic; @@ -121,7 +120,6 @@ architecture TDC of TDC is signal reset_coarse_cntr_flag : std_logic := '0'; signal ch_en : std_logic_vector(64 downto 1); signal ch_invert : std_logic_vector(64 downto 1); - signal data_limit : unsigned(7 downto 0); signal ring_buffer_full_thres : std_logic_vector(6 downto 0); signal calibration_on : std_logic := '0'; -- turns on calibration for trig type 0xD signal calibration_on_r : std_logic := '0'; -- turns on calibration for trig type 0xD @@ -164,10 +162,7 @@ architecture TDC of TDC is -- From the channels signal ch_data : std_logic_vector_array_36(0 to CHANNEL_NUMBER); signal ch_data_valid : std_logic_vector(CHANNEL_NUMBER-1 downto 0); - signal ch_wcnt : unsigned_array_8(0 to CHANNEL_NUMBER-1); signal ch_empty : std_logic_vector(CHANNEL_NUMBER-1 downto 0); - signal ch_full : std_logic_vector(CHANNEL_NUMBER-1 downto 0); - signal ch_almost_empty : std_logic_vector(CHANNEL_NUMBER-1 downto 0); signal ch_almost_full : std_logic_vector(CHANNEL_NUMBER-1 downto 0); signal ch_lost_hit_number : std_logic_vector_array_24(0 to CHANNEL_NUMBER-1); signal ch_encoder_start_number : std_logic_vector_array_24(0 to CHANNEL_NUMBER-1); @@ -208,7 +203,6 @@ architecture TDC of TDC is signal ch_hit_detect_cntr : unsigned_array_31(0 to CHANNEL_NUMBER-1); -- Debug signals - signal ref_debug : std_logic_vector(31 downto 0); signal ch_debug : std_logic_vector_array_32(0 to CHANNEL_NUMBER-1); signal ch_200_debug : std_logic_vector_array_32(0 to CHANNEL_NUMBER-1); signal readout_debug : std_logic_vector(31 downto 0); @@ -247,7 +241,6 @@ begin trg_win_en <= CONTROL_REG_IN(1*32+31); ch_en <= CONTROL_REG_IN(3*32+31 downto 2*32+0); - -- data_limit <= unsigned(CONTROL_REG_IN(4*32+7 downto 4*32+0)); -- since flexible threshold it is not needed ring_buffer_full_thres <= CONTROL_REG_IN(4*32+6 downto 4*32+0) when rising_edge(CLK_READOUT); ch_invert <= CONTROL_REG_IN(6*32+31 downto 5*32+0); @@ -264,7 +257,7 @@ begin begin if rising_edge(HIT_CAL_IN) then -- rising clock edge if cal_cntr_start = '0' then - cal_cntr <= (others => '0'); + cal_cntr <= "100"; else cal_cntr <= std_logic_vector(unsigned(cal_cntr) + to_unsigned(1,3)); end if; @@ -490,19 +483,13 @@ begin TRG_WIN_END_TDC_IN => trg_win_end_tdc_r(0), TRG_WIN_END_RDO_IN => trg_win_end_rdo, EPOCH_COUNTER_IN => epoch_cntr, - COARSE_COUNTER_IN => coarse_cntr(1), + COARSE_COUNTER_IN => coarse_cntr(0), READ_EN_IN => rd_en(0), FIFO_DATA_OUT => ch_data(0), FIFO_DATA_VALID_OUT => ch_data_valid(0), FIFO_ALMOST_FULL_OUT => ch_almost_full(0), FIFO_EMPTY_OUT => ch_empty(0), - FIFO_FULL_OUT => ch_full(0), - FIFO_ALMOST_EMPTY_OUT => ch_almost_empty(0), RING_BUFFER_FULL_THRES_IN => ring_buffer_full_thres, - VALID_TIMING_TRG_IN => VALID_TIMING_TRG_IN, - VALID_NOTIMING_TRG_IN => VALID_NOTIMING_TRG_IN, - SPIKE_DETECTED_IN => SPIKE_DETECTED_IN, - MULTI_TMG_TRG_IN => MULTI_TMG_TRG_IN, EPOCH_WRITE_EN_IN => '1', LOST_HIT_NUMBER => ch_lost_hit_number(0), HIT_DETECT_NUMBER => open, --ch_hit_detect_number(0), @@ -531,19 +518,13 @@ begin TRG_WIN_END_TDC_IN => trg_win_end_tdc_r(i), TRG_WIN_END_RDO_IN => trg_win_end_rdo, EPOCH_COUNTER_IN => epoch_cntr, - COARSE_COUNTER_IN => coarse_cntr(integer(ceil(real(i)/real(8)))), + COARSE_COUNTER_IN => coarse_cntr(i), -- coarse_cntr(integer(ceil(real(i)/real(8)))), READ_EN_IN => rd_en(i), FIFO_DATA_OUT => ch_data(i), FIFO_DATA_VALID_OUT => ch_data_valid(i), FIFO_ALMOST_FULL_OUT => ch_almost_full(i), FIFO_EMPTY_OUT => ch_empty(i), - FIFO_FULL_OUT => ch_full(i), - FIFO_ALMOST_EMPTY_OUT => ch_almost_empty(i), RING_BUFFER_FULL_THRES_IN => ring_buffer_full_thres, - VALID_TIMING_TRG_IN => '0', - VALID_NOTIMING_TRG_IN => '0', - SPIKE_DETECTED_IN => '0', - MULTI_TMG_TRG_IN => '0', EPOCH_WRITE_EN_IN => '1', LOST_HIT_NUMBER => ch_lost_hit_number(i), HIT_DETECT_NUMBER => open, --ch_hit_detect_number(i), @@ -593,7 +574,7 @@ begin TRG_WIN_END_RDO_OUT => trg_win_end_rdo, TRG_WIN_END_TDC_OUT => trg_win_end_tdc, MISSING_REF_TIME_OUT => missing_ref_time, - COARSE_COUNTER_IN => coarse_cntr(0), + COARSE_COUNTER_IN => coarse_cntr(CHANNEL_NUMBER), EPOCH_COUNTER_IN => epoch_cntr, TRG_TIME_OUT => trg_time, DEBUG_OUT => trg_handler_status_registers @@ -622,8 +603,6 @@ begin CH_DATA_VALID_IN => ch_data_valid, CH_ALMOST_FULL_IN => ch_almost_full, CH_EMPTY_IN => ch_empty, - CH_FULL_IN => ch_full, - CH_ALMOST_EMPTY_IN => ch_almost_empty, -- from the endpoint TRG_DATA_VALID_IN => TRG_DATA_VALID_IN, VALID_TIMING_TRG_IN => VALID_TIMING_TRG_IN, @@ -636,7 +615,6 @@ begin TRG_CODE_IN => TRG_CODE_IN, TRG_INFORMATION_IN => TRG_INFORMATION_IN, TRG_TYPE_IN => TRG_TYPE_IN, - DATA_LIMIT_IN => (others => '0'), --data_limit, -- to the endpoint TRG_RELEASE_OUT => ep_trg_release, TRG_STATUSBIT_OUT => ep_trg_statusbit, @@ -657,8 +635,6 @@ begin MISSING_REF_TIME_IN => missing_ref_time, -- miscellaneous LIGHT_MODE_IN => light_mode_en, - COARSE_COUNTER_IN => coarse_cntr(0), - EPOCH_COUNTER_IN => epoch_cntr, DEBUG_MODE_EN_IN => debug_mode_en, STATISTICS_OUT => readout_statistics, READOUT_DEBUG => readout_debug @@ -674,7 +650,7 @@ begin -- Coarse & Epoch Counters ------------------------------------------------------------------------------- -- Coarse counter - GenCoarseCounter : for i in 0 to 8 generate + GenCoarseCounter : for i in 0 to CHANNEL_NUMBER generate TheCoarseCounter : up_counter generic map ( NUMBER_OF_BITS => 11) @@ -719,7 +695,7 @@ begin SIGNAL_IN => reset_coarse_cntr_200, PULSE_OUT => reset_coarse_cntr_edge_200); - GenCoarseCounterReset : for i in 0 to 8 generate + GenCoarseCounterReset : for i in 0 to CHANNEL_NUMBER generate coarse_cntr_reset_r(i) <= coarse_cntr_reset when rising_edge(CLK_TDC); end generate GenCoarseCounterReset; @@ -732,8 +708,8 @@ begin RESET => epoch_cntr_reset, COUNT_OUT => epoch_cntr, UP_IN => epoch_cntr_up); - epoch_cntr_up <= and_all(coarse_cntr(0)); - epoch_cntr_reset <= coarse_cntr_reset_r(0); + epoch_cntr_up <= and_all(coarse_cntr(CHANNEL_NUMBER)); + epoch_cntr_reset <= coarse_cntr_reset_r(CHANNEL_NUMBER); ------------------------------------------------------------------------------- -- Statistics @@ -950,7 +926,7 @@ begin --logic_anal_data(13) <= readout_debug(8); --data_wr_r; --logic_anal_data(14) <= readout_debug(9); --data_finished_r; --logic_anal_data(15) <= readout_debug(10); --trg_release_r; - --logic_anal_data(31 downto 16) <= ref_debug(15 downto 0); + --logic_anal_data(31 downto 16) <= (others => '0'); --logic_anal_data(37 downto 32) <= readout_debug(16 downto 11); --data_out_r(27 downto 22); --logic_anal_data(47 downto 38) <= (others => '0'); --logic_anal_data(63 downto 48) <= ch_debug(1)(15 downto 0); diff --git a/releases/tdc_v2.1.2/TriggerHandler.vhd b/releases/tdc_v2.1.2/TriggerHandler.vhd index 21baf37..9ffe22d 100644 --- a/releases/tdc_v2.1.2/TriggerHandler.vhd +++ b/releases/tdc_v2.1.2/TriggerHandler.vhd @@ -4,7 +4,7 @@ -- File : TriggerHandler.vhd -- Author : Cahit Ugur c.ugur@gsi.de -- Created : 2013-03-13 --- Last update: 2015-03-10 +-- Last update: 2015-04-21 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- @@ -14,6 +14,7 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; +use work.trb_net_std.all; use work.trb_net_components.all; use work.trb3_components.all; diff --git a/releases/tdc_v2.1.2/cbmtof.vhd b/releases/tdc_v2.1.2/cbmtof.vhd index ff6ce5e..27f1b95 100644 --- a/releases/tdc_v2.1.2/cbmtof.vhd +++ b/releases/tdc_v2.1.2/cbmtof.vhd @@ -340,30 +340,6 @@ begin CLKOK => clk_200_i, -- 200 MHz, bypass LOCK => pll_lock_1); - --THE_CALIBRATION_PLL : entity work.pll_calibration - -- port map ( - -- CLK => clk_100_i, -- clk_in 100MHz - -- CLKOP => open, -- 12,5MHz %50 Duty cycle - -- CLKOS => osc_int, -- 12,5MHz 10ns pulse - -- CLKOK => open, -- clk_in bypass 100MHz - -- LOCK => pll_lock_2 - -- ); - - -- internal oscillator with frequency of 20MHz for tdc calibration - --OSCInst0 : OSCF - -- -- synthesis translate_off - -- generic map ( - -- NOM_FREQ => "20.0") - -- -- synthesis translate_on - -- port map ( - -- OSC => clk_osc_int); - - --THE_CALIBRATION_PLL : entity work.pll_calibration - -- port map ( - -- CLK => clk_osc_int, -- 20MHz - -- CLKOP => clk_cal, -- 100 MHz - -- LOCK => pll_lock_2 - -- ); clk_cal <= clk_100_i; diff --git a/releases/tdc_v2.1.2/tdc_components.vhd b/releases/tdc_v2.1.2/tdc_components.vhd index 12c6068..42cf908 100644 --- a/releases/tdc_v2.1.2/tdc_components.vhd +++ b/releases/tdc_v2.1.2/tdc_components.vhd @@ -100,15 +100,9 @@ package tdc_components is FIFO_DATA_VALID_OUT : out std_logic; FIFO_ALMOST_FULL_OUT : out std_logic; FIFO_EMPTY_OUT : out std_logic; - FIFO_FULL_OUT : out std_logic; - FIFO_ALMOST_EMPTY_OUT : out std_logic; RING_BUFFER_FULL_THRES_IN : in std_logic_vector(6 downto 0); COARSE_COUNTER_IN : in std_logic_vector(10 downto 0); EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0); - VALID_TIMING_TRG_IN : in std_logic; - VALID_NOTIMING_TRG_IN : in std_logic; - SPIKE_DETECTED_IN : in std_logic; - MULTI_TMG_TRG_IN : in std_logic; EPOCH_WRITE_EN_IN : in std_logic; LOST_HIT_NUMBER : out std_logic_vector(23 downto 0); HIT_DETECT_NUMBER : out std_logic_vector(30 downto 0); @@ -136,15 +130,10 @@ package tdc_components is TRG_WIN_END_RDO_IN : in std_logic; EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0); COARSE_COUNTER_IN : in std_logic_vector(10 downto 0); - READ_EN_IN : in std_logic; FIFO_DATA_OUT : out std_logic_vector(35 downto 0); FIFO_DATA_VALID_OUT : out std_logic; FIFO_ALMOST_FULL_OUT : out std_logic; RING_BUFFER_FULL_THRES_IN : in std_logic_vector(6 downto 0); - VALID_TIMING_TRG_IN : in std_logic; - VALID_NOTIMING_TRG_IN : in std_logic; - SPIKE_DETECTED_IN : in std_logic; - MULTI_TMG_TRG_IN : in std_logic; EPOCH_WRITE_EN_IN : in std_logic; ENCODER_START_OUT : out std_logic; ENCODER_FINISHED_OUT : out std_logic; @@ -183,8 +172,6 @@ package tdc_components is CH_DATA_VALID_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); CH_ALMOST_FULL_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); CH_EMPTY_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); - CH_FULL_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); - CH_ALMOST_EMPTY_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); TRG_DATA_VALID_IN : in std_logic; VALID_TIMING_TRG_IN : in std_logic; VALID_NOTIMING_TRG_IN : in std_logic; @@ -196,7 +183,6 @@ package tdc_components is TRG_CODE_IN : in std_logic_vector(7 downto 0); TRG_INFORMATION_IN : in std_logic_vector(23 downto 0); TRG_TYPE_IN : in std_logic_vector(3 downto 0); - DATA_LIMIT_IN : in unsigned(7 downto 0); TRG_RELEASE_OUT : out std_logic; TRG_STATUSBIT_OUT : out std_logic_vector(31 downto 0); DATA_OUT : out std_logic_vector(31 downto 0); @@ -212,8 +198,6 @@ package tdc_components is TRG_TIME_IN : in std_logic_vector(38 downto 0); MISSING_REF_TIME_IN : in std_logic; LIGHT_MODE_IN : in std_logic; - COARSE_COUNTER_IN : in std_logic_vector(10 downto 0); - EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0); DEBUG_MODE_EN_IN : in std_logic; STATISTICS_OUT : out std_logic_vector_array_24(0 to 15); READOUT_DEBUG : out std_logic_vector(31 downto 0)); @@ -536,4 +520,18 @@ package tdc_components is D_OUT : out std_logic_vector(WIDTH-1 downto 0)); end component; + component pll_in20_out100 is + port ( + CLK : in std_logic; + CLKOP : out std_logic; + LOCK : out std_logic); + end component pll_in20_out100; + + component pll_in125_out100 is + port ( + CLK : in std_logic; + CLKOP : out std_logic; + LOCK : out std_logic); + end component pll_in125_out100; + end package tdc_components; diff --git a/releases/tdc_v2.1.2/tdc_constraints_64.lpf b/releases/tdc_v2.1.2/tdc_constraints_64.lpf index 07c523e..85e82d4 100644 --- a/releases/tdc_v2.1.2/tdc_constraints_64.lpf +++ b/releases/tdc_v2.1.2/tdc_constraints_64.lpf @@ -499,7 +499,7 @@ UGROUP "FC_49" BBOX 1 51 BLKNAME THE_TDC/GEN_Channels.49.Channels/Channel200/SimAdderNo.FC; LOCATE UGROUP "FC_49" SITE "R8C131D" ; UGROUP "hitBuf_49" BBOX 1 1 - BLKNAME THE_TDC/GEN_hit_mux.49_hit_mux_ch; + BLKNAME THE_TDC/GEN_hit_mux.49.hit_mux_ch; LOCATE UGROUP "hitBuf_49" SITE "R9C133D" ; UGROUP "ff_en_49" BBOX 1 1 BLKNAME THE_TDC/GEN_Channels.49.Channels/Channel200/ff_array_en_1_i; @@ -509,7 +509,7 @@ UGROUP "FC_50" BBOX 1 51 BLKNAME THE_TDC/GEN_Channels.50.Channels/Channel200/SimAdderNo.FC; LOCATE UGROUP "FC_50" SITE "R10C131D" ; UGROUP "hitBuf_50" BBOX 1 1 - BLKNAME THE_TDC/GEN_hit_mux.50_hit_mux_ch; + BLKNAME THE_TDC/GEN_hit_mux.50.hit_mux_ch; LOCATE UGROUP "hitBuf_50" SITE "R11C133D" ; UGROUP "ff_en_50" BBOX 1 1 BLKNAME THE_TDC/GEN_Channels.50.Channels/Channel200/ff_array_en_1_i; @@ -519,7 +519,7 @@ UGROUP "FC_51" BBOX 1 51 BLKNAME THE_TDC/GEN_Channels.51.Channels/Channel200/SimAdderNo.FC; LOCATE UGROUP "FC_51" SITE "R21C131D" ; UGROUP "hitBuf_51" BBOX 1 1 - BLKNAME THE_TDC/GEN_hit_mux.51_hit_mux_ch; + BLKNAME THE_TDC/GEN_hit_mux.51.hit_mux_ch; LOCATE UGROUP "hitBuf_51" SITE "R22C133D" ; UGROUP "ff_en_51" BBOX 1 1 BLKNAME THE_TDC/GEN_Channels.51.Channels/Channel200/ff_array_en_1_i; @@ -529,7 +529,7 @@ UGROUP "FC_52" BBOX 1 51 BLKNAME THE_TDC/GEN_Channels.52.Channels/Channel200/SimAdderNo.FC; LOCATE UGROUP "FC_52" SITE "R23C131D" ; UGROUP "hitBuf_52" BBOX 1 1 - BLKNAME THE_TDC/GEN_hit_mux.52_hit_mux_ch; + BLKNAME THE_TDC/GEN_hit_mux.52.hit_mux_ch; LOCATE UGROUP "hitBuf_52" SITE "R24C133D" ; UGROUP "ff_en_52" BBOX 1 1 BLKNAME THE_TDC/GEN_Channels.52.Channels/Channel200/ff_array_en_1_i; @@ -539,7 +539,7 @@ UGROUP "FC_53" BBOX 1 51 BLKNAME THE_TDC/GEN_Channels.53.Channels/Channel200/SimAdderNo.FC; LOCATE UGROUP "FC_53" SITE "R30C131D" ; UGROUP "hitBuf_53" BBOX 1 1 - BLKNAME THE_TDC/GEN_hit_mux.53_hit_mux_ch; + BLKNAME THE_TDC/GEN_hit_mux.53.hit_mux_ch; LOCATE UGROUP "hitBuf_53" SITE "R31C133D" ; UGROUP "ff_en_53" BBOX 1 1 BLKNAME THE_TDC/GEN_Channels.53.Channels/Channel200/ff_array_en_1_i; @@ -549,7 +549,7 @@ UGROUP "FC_54" BBOX 1 51 BLKNAME THE_TDC/GEN_Channels.54.Channels/Channel200/SimAdderNo.FC; LOCATE UGROUP "FC_54" SITE "R32C131D" ; UGROUP "hitBuf_54" BBOX 1 1 - BLKNAME THE_TDC/GEN_hit_mux.54_hit_mux_ch; + BLKNAME THE_TDC/GEN_hit_mux.54.hit_mux_ch; LOCATE UGROUP "hitBuf_54" SITE "R33C133D" ; UGROUP "ff_en_54" BBOX 1 1 BLKNAME THE_TDC/GEN_Channels.54.Channels/Channel200/ff_array_en_1_i; @@ -559,7 +559,7 @@ UGROUP "FC_55" BBOX 1 51 BLKNAME THE_TDC/GEN_Channels.55.Channels/Channel200/SimAdderNo.FC; LOCATE UGROUP "FC_55" SITE "R35C131D" ; UGROUP "hitBuf_55" BBOX 1 1 - BLKNAME THE_TDC/GEN_hit_mux.55_hit_mux_ch; + BLKNAME THE_TDC/GEN_hit_mux.55.hit_mux_ch; LOCATE UGROUP "hitBuf_55" SITE "R36C133D" ; UGROUP "ff_en_55" BBOX 1 1 BLKNAME THE_TDC/GEN_Channels.55.Channels/Channel200/ff_array_en_1_i; @@ -569,7 +569,7 @@ UGROUP "FC_56" BBOX 1 51 BLKNAME THE_TDC/GEN_Channels.56.Channels/Channel200/SimAdderNo.FC; LOCATE UGROUP "FC_56" SITE "R37C131D" ; UGROUP "hitBuf_56" BBOX 1 1 - BLKNAME THE_TDC/GEN_hit_mux.56_hit_mux_ch; + BLKNAME THE_TDC/GEN_hit_mux.56.hit_mux_ch; LOCATE UGROUP "hitBuf_56" SITE "R38C133D" ; UGROUP "ff_en_56" BBOX 1 1 BLKNAME THE_TDC/GEN_Channels.56.Channels/Channel200/ff_array_en_1_i; @@ -579,7 +579,7 @@ UGROUP "FC_57" BBOX 1 51 BLKNAME THE_TDC/GEN_Channels.57.Channels/Channel200/SimAdderNo.FC; LOCATE UGROUP "FC_57" SITE "R48C131D" ; UGROUP "hitBuf_57" BBOX 1 1 - BLKNAME THE_TDC/GEN_hit_mux.57_hit_mux_ch; + BLKNAME THE_TDC/GEN_hit_mux.57.hit_mux_ch; LOCATE UGROUP "hitBuf_57" SITE "R49C133D" ; UGROUP "ff_en_57" BBOX 1 1 BLKNAME THE_TDC/GEN_Channels.57.Channels/Channel200/ff_array_en_1_i; @@ -660,14 +660,14 @@ LOCATE UGROUP "ff_en_64" SITE "R84C83D" ; ############################################################################## ## CHANNEL PLACEMENTS ## ############################################################################## -UGROUP "EF_LT2" BBOX 10 54 +UGROUP "EF_LT2" BBOX 10 51 BLKNAME THE_TDC/ReferenceChannel/Channel200 BLKNAME THE_TDC/ReferenceChannel/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.1.Channels/Channel200 BLKNAME THE_TDC/GEN_Channels.1.Channels/Buffer_128.The_Buffer ; LOCATE UGROUP "EF_LT2" SITE "R24C2D" ; -UGROUP "EF_LC1" BBOX 17 54 +UGROUP "EF_LC1" BBOX 17 51 BLKNAME THE_TDC/GEN_Channels.2.Channels/Channel200 BLKNAME THE_TDC/GEN_Channels.2.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.3.Channels/Channel200 @@ -678,7 +678,7 @@ UGROUP "EF_LC1" BBOX 17 54 BLKNAME THE_TDC/GEN_Channels.5.Channels/Buffer_128.The_Buffer ; LOCATE UGROUP "EF_LC1" SITE "R35C2D" ; -UGROUP "EF_LC3" BBOX 17 54 +UGROUP "EF_LC3" BBOX 17 51 BLKNAME THE_TDC/GEN_Channels.6.Channels/Channel200 BLKNAME THE_TDC/GEN_Channels.6.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.7.Channels/Channel200 @@ -689,7 +689,7 @@ UGROUP "EF_LC3" BBOX 17 54 BLKNAME THE_TDC/GEN_Channels.9.Channels/Buffer_128.The_Buffer ; LOCATE UGROUP "EF_LC3" SITE "R71C2D" ; -UGROUP "EF_LB1" BBOX 16 54 +UGROUP "EF_LB1" BBOX 16 51 BLKNAME THE_TDC/GEN_Channels.10.Channels/Channel200 BLKNAME THE_TDC/GEN_Channels.10.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.11.Channels/Channel200 @@ -698,7 +698,7 @@ UGROUP "EF_LB1" BBOX 16 54 BLKNAME THE_TDC/GEN_Channels.12.Channels/Buffer_128.The_Buffer ; LOCATE UGROUP "EF_LB1" SITE "R89C2D" ; -UGROUP "EF_LT1" BBOX 16 54 +UGROUP "EF_LT1" BBOX 16 51 BLKNAME THE_TDC/GEN_Channels.13.Channels/Channel200 BLKNAME THE_TDC/GEN_Channels.13.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.14.Channels/Channel200 @@ -709,7 +709,7 @@ UGROUP "EF_LT1" BBOX 16 54 BLKNAME THE_TDC/GEN_Channels.16.Channels/Buffer_128.The_Buffer ; LOCATE UGROUP "EF_LT1" SITE "R8C2D" ; -UGROUP "EF_CB1" BBOX 16 54 +UGROUP "EF_CB1" BBOX 16 51 BLKNAME THE_TDC/GEN_Channels.17.Channels/Channel200 BLKNAME THE_TDC/GEN_Channels.17.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.18.Channels/Channel200 @@ -719,15 +719,15 @@ UGROUP "EF_CB1" BBOX 16 54 BLKNAME THE_TDC/GEN_Channels.20.Channels/Channel200 BLKNAME THE_TDC/GEN_Channels.20.Channels/Buffer_128.The_Buffer ; -LOCATE UGROUP "EF_CB1" SITE "R89C56D" ; -UGROUP "EF_CB2" BBOX 10 54 +LOCATE UGROUP "EF_CB1" SITE "R89C58D" ; +UGROUP "EF_CB2" BBOX 10 51 BLKNAME THE_TDC/GEN_Channels.21.Channels/Channel200 BLKNAME THE_TDC/GEN_Channels.21.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.22.Channels/Channel200 BLKNAME THE_TDC/GEN_Channels.22.Channels/Buffer_128.The_Buffer ; -LOCATE UGROUP "EF_CB2" SITE "R105C56D" ; -UGROUP "EF_LC2" BBOX 17 54 +LOCATE UGROUP "EF_CB2" SITE "R105C58D" ; +UGROUP "EF_LC2" BBOX 17 51 BLKNAME THE_TDC/GEN_Channels.23.Channels/Channel200 BLKNAME THE_TDC/GEN_Channels.23.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.24.Channels/Channel200 @@ -738,14 +738,14 @@ UGROUP "EF_LC2" BBOX 17 54 BLKNAME THE_TDC/GEN_Channels.26.Channels/Buffer_128.The_Buffer ; LOCATE UGROUP "EF_LC2" SITE "R53C2D" ; -UGROUP "EF_LB2" BBOX 10 54 +UGROUP "EF_LB2" BBOX 10 51 BLKNAME THE_TDC/GEN_Channels.27.Channels/Channel200 BLKNAME THE_TDC/GEN_Channels.27.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.28.Channels/Channel200 BLKNAME THE_TDC/GEN_Channels.28.Channels/Buffer_128.The_Buffer ; LOCATE UGROUP "EF_LB2" SITE "R105C2D" ; -UGROUP "EF_CT1" BBOX 16 54 +UGROUP "EF_CT1" BBOX 16 51 BLKNAME THE_TDC/GEN_Channels.29.Channels/Channel200 BLKNAME THE_TDC/GEN_Channels.29.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.30.Channels/Channel200 @@ -755,15 +755,15 @@ UGROUP "EF_CT1" BBOX 16 54 BLKNAME THE_TDC/GEN_Channels.32.Channels/Channel200 BLKNAME THE_TDC/GEN_Channels.32.Channels/Buffer_128.The_Buffer ; -LOCATE UGROUP "EF_CT1" SITE "R8C56D" ; -UGROUP "EF_CT2" BBOX 10 54 +LOCATE UGROUP "EF_CT1" SITE "R8C58D" ; +UGROUP "EF_CT2" BBOX 10 51 BLKNAME THE_TDC/GEN_Channels.33.Channels/Channel200 BLKNAME THE_TDC/GEN_Channels.33.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.34.Channels/Channel200 BLKNAME THE_TDC/GEN_Channels.34.Channels/Buffer_128.The_Buffer ; -LOCATE UGROUP "EF_CT2" SITE "R24C56D" ; -UGROUP "EF_CC1" BBOX 17 54 +LOCATE UGROUP "EF_CT2" SITE "R24C58D" ; +UGROUP "EF_CC1" BBOX 17 51 BLKNAME THE_TDC/GEN_Channels.35.Channels/Channel200 BLKNAME THE_TDC/GEN_Channels.35.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.36.Channels/Channel200 @@ -773,8 +773,8 @@ UGROUP "EF_CC1" BBOX 17 54 BLKNAME THE_TDC/GEN_Channels.38.Channels/Channel200 BLKNAME THE_TDC/GEN_Channels.38.Channels/Buffer_128.The_Buffer ; -LOCATE UGROUP "EF_CC1" SITE "R35C56D" ; -UGROUP "EF_RB1" BBOX 16 54 +LOCATE UGROUP "EF_CC1" SITE "R35C58D" ; +UGROUP "EF_RB1" BBOX 16 51 BLKNAME THE_TDC/GEN_Channels.39.Channels/Channel200 BLKNAME THE_TDC/GEN_Channels.39.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.40.Channels/Channel200 @@ -784,8 +784,8 @@ UGROUP "EF_RB1" BBOX 16 54 BLKNAME THE_TDC/GEN_Channels.42.Channels/Channel200 BLKNAME THE_TDC/GEN_Channels.42.Channels/Buffer_128.The_Buffer ; -LOCATE UGROUP "EF_RB1" SITE "R89C128D" ; -UGROUP "EF_RC3" BBOX 17 54 +LOCATE UGROUP "EF_RB1" SITE "R89C131D" ; +UGROUP "EF_RC3" BBOX 17 51 BLKNAME THE_TDC/GEN_Channels.43.Channels/Channel200 BLKNAME THE_TDC/GEN_Channels.43.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.44.Channels/Channel200 @@ -795,15 +795,15 @@ UGROUP "EF_RC3" BBOX 17 54 BLKNAME THE_TDC/GEN_Channels.46.Channels/Channel200 BLKNAME THE_TDC/GEN_Channels.46.Channels/Buffer_128.The_Buffer ; -LOCATE UGROUP "EF_RC3" SITE "R71C128D" ; -UGROUP "EF_RB2" BBOX 10 54 +LOCATE UGROUP "EF_RC3" SITE "R71C131D" ; +UGROUP "EF_RB2" BBOX 10 51 BLKNAME THE_TDC/GEN_Channels.47.Channels/Channel200 BLKNAME THE_TDC/GEN_Channels.47.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.48.Channels/Channel200 BLKNAME THE_TDC/GEN_Channels.48.Channels/Buffer_128.The_Buffer ; -LOCATE UGROUP "EF_RB2" SITE "R105C128D" ; -UGROUP "EF_RT1" BBOX 17 54 +LOCATE UGROUP "EF_RB2" SITE "R105C131D" ; +UGROUP "EF_RT1" BBOX 17 51 BLKNAME THE_TDC/GEN_Channels.49.Channels/Channel200 BLKNAME THE_TDC/GEN_Channels.49.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.50.Channels/Channel200 @@ -813,15 +813,15 @@ UGROUP "EF_RT1" BBOX 17 54 BLKNAME THE_TDC/GEN_Channels.52.Channels/Channel200 BLKNAME THE_TDC/GEN_Channels.52.Channels/Buffer_128.The_Buffer ; -LOCATE UGROUP "EF_RT1" SITE "R8C128D" ; -UGROUP "EF_RT2" BBOX 17 54 +LOCATE UGROUP "EF_RT1" SITE "R8C131D" ; +UGROUP "EF_RT2" BBOX 17 51 BLKNAME THE_TDC/GEN_Channels.53.Channels/Channel200 BLKNAME THE_TDC/GEN_Channels.53.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.54.Channels/Channel200 BLKNAME THE_TDC/GEN_Channels.54.Channels/Buffer_128.The_Buffer ; -LOCATE UGROUP "EF_RT2" SITE "R24C128D" ; -UGROUP "EF_RC1" BBOX 17 54 +LOCATE UGROUP "EF_RT2" SITE "R24C131D" ; +UGROUP "EF_RC1" BBOX 17 51 BLKNAME THE_TDC/GEN_Channels.55.Channels/Channel200 BLKNAME THE_TDC/GEN_Channels.55.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.56.Channels/Channel200 @@ -831,8 +831,8 @@ UGROUP "EF_RC1" BBOX 17 54 BLKNAME THE_TDC/GEN_Channels.58.Channels/Channel200 BLKNAME THE_TDC/GEN_Channels.58.Channels/Buffer_128.The_Buffer ; -LOCATE UGROUP "EF_RC1" SITE "R35C128D" ; -UGROUP "EF_RC2" BBOX 17 54 +LOCATE UGROUP "EF_RC1" SITE "R35C131D" ; +UGROUP "EF_RC2" BBOX 17 51 BLKNAME THE_TDC/GEN_Channels.59.Channels/Channel200 BLKNAME THE_TDC/GEN_Channels.59.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.60.Channels/Channel200 @@ -842,13 +842,13 @@ UGROUP "EF_RC2" BBOX 17 54 BLKNAME THE_TDC/GEN_Channels.62.Channels/Channel200 BLKNAME THE_TDC/GEN_Channels.62.Channels/Buffer_128.The_Buffer ; -LOCATE UGROUP "EF_RC2" SITE "R53C128D" ; -UGROUP "EF_CC3" BBOX 10 54 +LOCATE UGROUP "EF_RC2" SITE "R53C131D" ; +UGROUP "EF_CC3" BBOX 10 51 BLKNAME THE_TDC/GEN_Channels.63.Channels/Channel200 BLKNAME THE_TDC/GEN_Channels.64.Channels/Channel200 BLKNAME THE_TDC/GEN_Channels.63.Channels/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.64.Channels/Buffer_128.The_Buffer; -LOCATE UGROUP "EF_CC3" SITE "R78C56D" ; +LOCATE UGROUP "EF_CC3" SITE "R78C58D" ; ############################################################################# ## Stretcher @@ -870,72 +870,3 @@ LOCATE UGROUP "Stretcher_B" SITE "R2C2D"; ############################################################################# ## Other Logic Placements ############################################################################# - - -MULTICYCLE FROM CLKNET "clk_100_i" TO CLKNET "CLK_OSC_c" 4.000000 X ; - -PROHIBIT SECONDARY NET "THE_TDC/ReferenceChannel/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.1.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.2.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.3.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.4.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.5.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.6.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.7.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.8.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.9.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.10.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.11.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.12.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.13.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.14.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.15.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.16.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.17.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.18.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.19.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.20.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.21.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.22.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.23.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.24.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.25.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.26.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.27.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.28.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.29.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.30.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.31.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.32.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.33.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.34.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.35.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.36.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.37.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.38.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.39.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.40.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.41.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.42.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.43.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.44.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.45.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.46.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.47.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.48.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.49.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.50.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.51.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.52.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.53.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.54.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.55.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.56.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.57.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.58.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.59.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.60.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.61.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.62.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.63.Channels/Channel200/ff_array_en"; -PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.64.Channels/Channel200/ff_array_en"; diff --git a/releases/tdc_v2.1.2/trb3_periph_ADA.vhd b/releases/tdc_v2.1.2/trb3_periph_ADA.vhd index 59ea67b..4578b9a 100644 --- a/releases/tdc_v2.1.2/trb3_periph_ADA.vhd +++ b/releases/tdc_v2.1.2/trb3_periph_ADA.vhd @@ -6,6 +6,7 @@ library work; use work.trb_net_std.all; use work.trb_net_components.all; use work.trb3_components.all; +use work.tdc_components.all; use work.config.all; use work.tdc_version.all; use work.version.all; @@ -36,10 +37,11 @@ entity trb3_periph_ADA is SPARE_LINE : inout std_logic_vector(3 downto 0); --inputs only INP : in std_logic_vector(63 downto 0); --DAC - DAC_SDO : in std_logic; - DAC_SDI : out std_logic; - DAC_SCK : out std_logic; - DAC_CS : out std_logic_vector(4 downto 1); + DAC_IN_SDI : in std_logic; + DAC_OUT_SDO : out std_logic; + DAC_OUT_SCK : out std_logic; + DAC_OUT_CS : out std_logic_vector(4 downto 1); + DAC_OUT_CLR : out std_logic; --Flash ROM & Reboot FLASH_CLK : out std_logic; FLASH_CS : out std_logic; @@ -77,10 +79,11 @@ entity trb3_periph_ADA is attribute syn_useioff of TEST_LINE : signal is true; attribute syn_useioff of INP : signal is false; attribute syn_useioff of SPARE_LINE : signal is true; - attribute syn_useioff of DAC_SDI : signal is true; - attribute syn_useioff of DAC_SDO : signal is true; - attribute syn_useioff of DAC_SCK : signal is true; - attribute syn_useioff of DAC_CS : signal is true; + attribute syn_useioff of DAC_IN_SDI : signal is true; + attribute syn_useioff of DAC_OUT_SDO : signal is true; + attribute syn_useioff of DAC_OUT_SCK : signal is true; + attribute syn_useioff of DAC_OUT_CS : signal is true; + attribute syn_useioff of DAC_OUT_CLR : signal is true; end entity; @@ -97,7 +100,6 @@ architecture trb3_periph_ADA_arch of trb3_periph_ADA is signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL signal clk_20 : std_logic; --clock for calibration at 20 MHz, via PLL - signal clk_20_i : std_logic; --clock for calibration at 20 MHz, via PLL signal osc_int : std_logic; --clock for calibration at 20 MHz, via internal osscilator signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic. signal pll_lock2 : std_logic; --Internal PLL locked. @@ -174,20 +176,6 @@ architecture trb3_periph_ADA_arch of trb3_periph_ADA is signal timer_ticks : std_logic_vector(1 downto 0); --Flash - --signal spictrl_read_en : std_logic; - --signal spictrl_write_en : std_logic; - --signal spictrl_data_in : std_logic_vector(31 downto 0); - --signal spictrl_addr : std_logic; - --signal spictrl_data_out : std_logic_vector(31 downto 0); - --signal spictrl_ack : std_logic; - --signal spictrl_busy : std_logic; - --signal spimem_read_en : std_logic; - --signal spimem_write_en : std_logic; - --signal spimem_data_in : std_logic_vector(31 downto 0); - --signal spimem_addr : std_logic_vector(5 downto 0); - --signal spimem_data_out : std_logic_vector(31 downto 0); - --signal spimem_ack : std_logic; - signal spimem_read_en : std_logic; signal spimem_write_en : std_logic; signal spimem_data_in : std_logic_vector(31 downto 0); @@ -324,23 +312,11 @@ begin LOCK => pll_lock); - ---- internal oscillator with frequency of 20MHz for tdc calibration - --OSCInst0 : OSCF - -- -- synthesis translate_off - -- generic map ( - -- NOM_FREQ => "20.0") - -- -- synthesis translate_on - -- port map ( - -- OSC => clk_20); - - --pll_calibration: entity work.pll_in20_out100 - -- port map ( - -- CLK => clk_20, - -- CLKOP => osc_int, - -- CLKOS => clk_20_i, - -- LOCK => pll_lock2); - - osc_int <= CLK_GPLL_LEFT; + pll_calibration: entity work.pll_in125_out100 + port map ( + CLK => CLK_GPLL_LEFT, + CLKOP => osc_int, + LOCK => open); --------------------------------------------------------------------------- @@ -535,31 +511,6 @@ begin DAT_NO_MORE_DATA_OUT => regio_no_more_data_in, DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in, - ----Bus Handler (SPI CTRL) - --BUS_READ_ENABLE_OUT(0) => spictrl_read_en, - --BUS_WRITE_ENABLE_OUT(0) => spictrl_write_en, - --BUS_DATA_OUT(0*32+31 downto 0*32) => spictrl_data_in, - --BUS_ADDR_OUT(0*16) => spictrl_addr, - --BUS_ADDR_OUT(0*16+15 downto 0*16+1) => open, - --BUS_TIMEOUT_OUT(0) => open, - --BUS_DATA_IN(0*32+31 downto 0*32) => spictrl_data_out, - --BUS_DATAREADY_IN(0) => spictrl_ack, - --BUS_WRITE_ACK_IN(0) => spictrl_ack, - --BUS_NO_MORE_DATA_IN(0) => spictrl_busy, - --BUS_UNKNOWN_ADDR_IN(0) => '0', - ----Bus Handler (SPI Memory) - --BUS_READ_ENABLE_OUT(1) => spimem_read_en, - --BUS_WRITE_ENABLE_OUT(1) => spimem_write_en, - --BUS_DATA_OUT(1*32+31 downto 1*32) => spimem_data_in, - --BUS_ADDR_OUT(1*16+5 downto 1*16) => spimem_addr, - --BUS_ADDR_OUT(1*16+15 downto 1*16+6) => open, - --BUS_TIMEOUT_OUT(1) => open, - --BUS_DATA_IN(1*32+31 downto 1*32) => spimem_data_out, - --BUS_DATAREADY_IN(1) => spimem_ack, - --BUS_WRITE_ACK_IN(1) => spimem_ack, - --BUS_NO_MORE_DATA_IN(1) => '0', - --BUS_UNKNOWN_ADDR_IN(1) => '0', - --Bus Handler (SPI Flash control) BUS_READ_ENABLE_OUT(0) => spimem_read_en, BUS_WRITE_ENABLE_OUT(0) => spimem_write_en, @@ -722,54 +673,6 @@ begin --------------------------------------------------------------------------- -- SPI / Flash --------------------------------------------------------------------------- - - --THE_SPI_MASTER : spi_master - -- port map( - -- CLK_IN => clk_100_i, - -- RESET_IN => reset_i, - -- -- Slave bus - -- BUS_READ_IN => spictrl_read_en, - -- BUS_WRITE_IN => spictrl_write_en, - -- BUS_BUSY_OUT => spictrl_busy, - -- BUS_ACK_OUT => spictrl_ack, - -- BUS_ADDR_IN(0) => spictrl_addr, - -- BUS_DATA_IN => spictrl_data_in, - -- BUS_DATA_OUT => spictrl_data_out, - -- -- SPI connections - -- SPI_CS_OUT => FLASH_CS, - -- SPI_SDI_IN => FLASH_DOUT, - -- SPI_SDO_OUT => FLASH_DIN, - -- SPI_SCK_OUT => FLASH_CLK, - -- -- BRAM for read/write data - -- BRAM_A_OUT => spi_bram_addr, - -- BRAM_WR_D_IN => spi_bram_wr_d, - -- BRAM_RD_D_OUT => spi_bram_rd_d, - -- BRAM_WE_OUT => spi_bram_we, - -- -- Status lines - -- STAT => open - -- ); - - ---- data memory for SPI accesses - --THE_SPI_MEMORY : spi_databus_memory - -- port map( - -- CLK_IN => clk_100_i, - -- RESET_IN => reset_i, - -- -- Slave bus - -- BUS_ADDR_IN => spimem_addr, - -- BUS_READ_IN => spimem_read_en, - -- BUS_WRITE_IN => spimem_write_en, - -- BUS_ACK_OUT => spimem_ack, - -- BUS_DATA_IN => spimem_data_in, - -- BUS_DATA_OUT => spimem_data_out, - -- -- state machine connections - -- BRAM_ADDR_IN => spi_bram_addr, - -- BRAM_WR_D_OUT => spi_bram_wr_d, - -- BRAM_RD_D_IN => spi_bram_rd_d, - -- BRAM_WE_IN => spi_bram_we, - -- -- Status lines - -- STAT => open - -- ); - THE_SPI_RELOAD : entity spi_flash_and_fpga_reload port map( CLK_IN => clk_100_i, @@ -797,8 +700,33 @@ begin ------------------------------------------------------------------------------- -- SPI ------------------------------------------------------------------------------- - gen_SPI : if INCLUDE_SPI = 1 generate - DAC_SPI : spi_ltc2600 + gen_SPI : if INCLUDE_SPI = 1 and SPI_FOR_PADI = 1 generate + THE_DAC_SPI : spi_ltc2600 + generic map ( + BITS => 16, + WAITCYCLES => 15) + port map( + CLK_IN => clk_100_i, + RESET_IN => reset_i, + -- Slave bus + BUS_ADDR_IN => spidac_addr, + BUS_READ_IN => spidac_read_en, + BUS_WRITE_IN => spidac_write_en, + BUS_ACK_OUT => spidac_ack, + BUS_BUSY_OUT => spidac_busy, + BUS_DATA_IN => spidac_data_in, + BUS_DATA_OUT => spidac_data_out, + -- SPI connections + SPI_CS_OUT(0) => DAC_OUT_CS(1), + SPI_SDI_IN => DAC_IN_SDI, + SPI_SDO_OUT => DAC_OUT_SDO, + SPI_SCK_OUT => DAC_OUT_SCK, + SPI_CLR_OUT(0) => DAC_OUT_CLR + ); + end generate; + + gen_ADA_SPI : if INCLUDE_SPI = 1 and SPI_FOR_PADI = 0 generate + THE_DAC_SPI : spi_ltc2600 port map ( CLK_IN => clk_100_i, RESET_IN => reset_i, @@ -811,10 +739,10 @@ begin BUS_DATA_IN => spidac_data_in, BUS_DATA_OUT => spidac_data_out, -- SPI connections - SPI_CS_OUT(3 downto 0) => DAC_CS, + SPI_CS_OUT(3 downto 0) => DAC_OUT_CS, SPI_SDI_IN => '0', - SPI_SDO_OUT => DAC_SDI, - SPI_SCK_OUT => DAC_SCK, + SPI_SDO_OUT => DAC_IN_SDI, + SPI_SCK_OUT => DAC_OUT_SCK, SPI_CLR_OUT => open); end generate; diff --git a/releases/tdc_v2.1.2/trbnet_constraints.lpf b/releases/tdc_v2.1.2/trbnet_constraints.lpf index ff8f4a3..f099041 100644 --- a/releases/tdc_v2.1.2/trbnet_constraints.lpf +++ b/releases/tdc_v2.1.2/trbnet_constraints.lpf @@ -11,8 +11,8 @@ MULTICYCLE TO CELL "THE_MEDIA_DOWNLINK/SCI_DATA_OUT*" 50 ns; MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns; MULTICYCLE TO CELL "THE_RESET_HANDLER/final_reset*" 30 ns; MULTICYCLE TO CELL "THE_RESET_HANDLER/trb_reset_*" 20 ns; -MULTICYCLE TO CELL "gen_SPI_DAC_SPI_*io*" 20 ns; -MULTICYCLE TO CELL "THE_SPI_MASTER_THE_SPI_SLIM_tx_sreg_oregio*" 20 ns; +MULTICYCLE TO CELL "gen_SPI_THE_DAC_SPI_*io*" 20 ns; +MULTICYCLE TO CELL "THE_SPI_RELOAD_THE_SPI_MASTER_THE_SPI_SLIM_tx_sreg_oregio*" 20 ns; BLOCK PATH TO CELL "gen_TRIGGER_LOGIC_THE_TRIG_LOGIC/out_*"; diff --git a/releases/tdc_v2.1.2/unimportant_lines_constraints.lpf b/releases/tdc_v2.1.2/unimportant_lines_constraints.lpf index defc081..eb9b989 100644 --- a/releases/tdc_v2.1.2/unimportant_lines_constraints.lpf +++ b/releases/tdc_v2.1.2/unimportant_lines_constraints.lpf @@ -1,30 +1,25 @@ ############################################################################# ## Unimportant Data Lines ## ############################################################################# -MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" TO CLKNET CLK_PCLK_LEFT 2x; +MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" TO CLKNET CLK_PCLK_LEFT_c 2x; MULTICYCLE FROM CELL "THE_TDC/reset_counters*" 4x; -MULTICYCLE TO CELL "THE_TDC/ReferenceChannel/sync_q*" 4 x; -MULTICYCLE TO CELL "THE_TDC/GEN_Channels*Channels/sync_q*" 4 x; - MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/FF*" TO CELL "THE_TDC/ReferenceChannel/Channel200/ringBuffer_almost_full_sync*" 2x; MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/FF*" TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/ringBuffer_almost_full_sync*" 2x; -MULTICYCLE FROM CELL "THE_TDC/TheEpochCounter/counter*" TO CELL "THE_TDC/ReferenceChannel/epoch_cntr_reg*" 3 X; -MULTICYCLE FROM CELL "THE_TDC/TheEpochCounter/counter*" TO CELL "THE_TDC/GEN_Channels*Channels/epoch_cntr_reg*" 3 X; +MULTICYCLE FROM CELL "THE_TDC/TheEpochCounter/counter*" TO CELL "THE_TDC/ReferenceChannel/Channel200/epoch_cntr[*]" 4 X; +MULTICYCLE FROM CELL "THE_TDC/TheEpochCounter/counter*" TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/epoch_cntr[*]" 4 X; MULTICYCLE TO CELL "THE_TDC/TheReadout/TW_pre*" 4 x; MULTICYCLE TO CELL "THE_TDC/TheReadout/TW_post*" 4 x; +MULTICYCLE TO CELL "THE_TDC/TheChannelDebugBus/data_out_reg[*]" 4 x; +MULTICYCLE FROM CLKNET "clk_100_i" TO CLKNET "CLK_OSC_c" 4.000000 X ; -#BLOCK PATH TO CELL "THE_TDC/edge_rising_r[*]" ; -#BLOCK PATH TO CELL "THE_TDC/edge_falling_r[*]" ; BLOCK NET "THE_TDC/pulse[*]"; BLOCK NET "THE_TDC/hit_in_s*"; -#BLOCK NET "THE_TDC/edge_rising[*]" ; -#BLOCK NET "THE_TDC/edge_falling[*]" ; MAXDELAY NET "THE_TDC/hit_in_i*" 0.600000 nS; #DATAPATH_ONLY ; @@ -41,11 +36,72 @@ MAXDELAY NET "THE_TDC/hit_in_i*" 0.600000 nS; #DATAPATH_ONLY ; # MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/The_Buffer/*" TO CELL "THE_TDC/TheReadout/rd_en*" 2 X; -# # BLOCK NET "THE_TDC/reset_tdc*" ; -# # BLOCK NET "THE_TDC/reset_rdo*" ; -# # #BLOCK NET "THE_TDC/hit_in_*" ; -# # BLOCK NET "THE_TDC/hit_latch*" ; -# # BLOCK NET "THE_TDC/reset_counters*" ; +PROHIBIT SECONDARY NET "THE_TDC/ReferenceChannel/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.1.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.2.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.3.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.4.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.5.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.6.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.7.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.8.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.9.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.10.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.11.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.12.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.13.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.14.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.15.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.16.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.17.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.18.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.19.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.20.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.21.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.22.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.23.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.24.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.25.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.26.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.27.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.28.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.29.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.30.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.31.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.32.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.33.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.34.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.35.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.36.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.37.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.38.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.39.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.40.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.41.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.42.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.43.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.44.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.45.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.46.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.47.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.48.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.49.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.50.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.51.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.52.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.53.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.54.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.55.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.56.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.57.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.58.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.59.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.60.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.61.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.62.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.63.Channels/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.64.Channels/Channel200/ff_array_en"; + -- 2.43.0