From b56096e50ce6a276a7a8d3380d3f3903a51c0be3 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Thu, 4 Jun 2009 16:25:22 +0000 Subject: [PATCH] started component package for trbnet, Jan --- media_interfaces/trb_net16_lsm_sfp.vhd | 4 +- media_interfaces/trb_net16_med_ecp_fot.vhd | 2 +- trb_net16_api_base.vhd | 302 ++++++++------------- trb_net16_endpoint_hades_full.vhd | 6 +- trb_net_components.vhd | 121 +++++++++ 5 files changed, 242 insertions(+), 193 deletions(-) create mode 100644 trb_net_components.vhd diff --git a/media_interfaces/trb_net16_lsm_sfp.vhd b/media_interfaces/trb_net16_lsm_sfp.vhd index c85d334..6094af6 100644 --- a/media_interfaces/trb_net16_lsm_sfp.vhd +++ b/media_interfaces/trb_net16_lsm_sfp.vhd @@ -317,7 +317,7 @@ begin next_med_error <= ERROR_OK; end if; when CVFND => - if( cv_ctr(15) = '0' ) then + if( cv_ctr(1) = '0' ) then NEXT_STATE <= LINK; -- try again (?) next_rx_allow <= '1'; next_tx_allow <= '1'; @@ -369,7 +369,7 @@ begin when CVFND => state_bits <= "0111"; link_status_led <= '1'; when LINK => state_bits <= "1000"; - link_status_led <= '1'; + link_status_led <= '0'; when CVBAD => state_bits <= "1001"; link_status_led <= timing_ctr(25) and timing_ctr(24) and timing_ctr(23); when others => state_bits <= "1111"; diff --git a/media_interfaces/trb_net16_med_ecp_fot.vhd b/media_interfaces/trb_net16_med_ecp_fot.vhd index 57ed375..c1bfe7c 100644 --- a/media_interfaces/trb_net16_med_ecp_fot.vhd +++ b/media_interfaces/trb_net16_med_ecp_fot.vhd @@ -238,7 +238,7 @@ attribute HGROUP of trb_net16_med_ecp_fot_arch : architecture is "GROUP_PCS"; signal rx_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0); signal sfp_los : std_logic; - signal led_counter : std_logic_vector(15 downto 0); + signal led_counter : std_logic_vector(13 downto 0); signal rx_led : std_logic; signal tx_led : std_logic; diff --git a/trb_net16_api_base.vhd b/trb_net16_api_base.vhd index 8172d95..38609a0 100644 --- a/trb_net16_api_base.vhd +++ b/trb_net16_api_base.vhd @@ -5,6 +5,7 @@ USE IEEE.std_logic_UNSIGNED.ALL; library work; use work.trb_net_std.all; +use work.trb_net_components.all; entity trb_net16_api_base is generic ( @@ -75,6 +76,8 @@ entity trb_net16_api_base is INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_SLAVE_READ_OUT : out std_logic; + CTRL_SEQNR_RESET : in std_logic; + -- Status and control port STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0); STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0) @@ -85,116 +88,6 @@ end entity; architecture trb_net16_api_base_arch of trb_net16_api_base is - component trb_net16_dummy_fifo is - port ( - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0); - PACKET_NUM_IN : in std_logic_vector(1 downto 0); - WRITE_ENABLE_IN : in std_logic; - DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0); - PACKET_NUM_OUT : out std_logic_vector(1 downto 0); - READ_ENABLE_IN : in std_logic; - FULL_OUT : out std_logic; - EMPTY_OUT : out std_logic - ); - end component; - - component trb_net16_fifo is - generic ( - USE_VENDOR_CORES : integer range 0 to 1 := c_NO; - DEPTH : integer := 6 - ); - port ( - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0); - PACKET_NUM_IN : in std_logic_vector(1 downto 0); - WRITE_ENABLE_IN : in std_logic; - DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0); - PACKET_NUM_OUT : out std_logic_vector(1 downto 0); - READ_ENABLE_IN : in std_logic; - FULL_OUT : out std_logic; - EMPTY_OUT : out std_logic - ); - end component; - - component trb_net16_sbuf is - generic ( - VERSION : integer := 0 - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- port to combinatorial logic - COMB_DATAREADY_IN : in STD_LOGIC; --comb logic provides data word - COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle - COMB_READ_IN : in STD_LOGIC; --comb logic IS reading - COMB_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); - COMB_PACKET_NUM_IN: in STD_LOGIC_VECTOR(c_NUM_WIDTH-1 downto 0); - -- Port to synchronous output. - SYN_DATAREADY_OUT : out STD_LOGIC; - SYN_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); - SYN_PACKET_NUM_OUT: out STD_LOGIC_VECTOR(c_NUM_WIDTH-1 downto 0); - SYN_READ_IN : in STD_LOGIC; - -- Status and control port - STAT_BUFFER : out STD_LOGIC - ); - end component; - - component trb_net16_term is - generic ( - USE_APL_PORT : integer range 0 to 1 := c_YES; - --even when 0, ERROR_PACKET_IN is used for automatic replys - SECURE_MODE : integer range 0 to 1 := std_TERM_SECURE_MODE - --if secure_mode is not used, apl must provide error pattern and dtype until - --next trigger comes in. In secure mode these need to be available while relase_trg is high - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - INT_DATAREADY_OUT : out std_logic; - INT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_READ_IN : in std_logic; - - INT_DATAREADY_IN : in std_logic; - INT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_READ_OUT : out std_logic; - - APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0) - ); - end component; - - component trb_net_sbuf is - generic ( - DATA_WIDTH : integer := c_DATA_WIDTH + c_NUM_WIDTH; - VERSION: integer := SBUF_VERSION); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- port to combinatorial logic - COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word - COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle - COMB_READ_IN: in STD_LOGIC; --comb logic IS reading - COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); - SYN_DATAREADY_OUT: out STD_LOGIC; - SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); - SYN_READ_IN: in STD_LOGIC; - STAT_BUFFER: out STD_LOGIC - ); - end component; - -- signals for the APL to INT fifo: signal fifo_to_int_data_in : std_logic_vector(c_DATA_WIDTH-1 downto 0); signal fifo_to_int_packet_num_in : std_logic_vector(1 downto 0); @@ -224,10 +117,10 @@ architecture trb_net16_api_base_arch of trb_net16_api_base is signal saved_fifo_to_apl_packet_type : std_logic_vector(2 downto 0); signal current_fifo_to_apl_packet_type : std_logic_vector(2 downto 0); -signal saved_fifo_to_int_long_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0); -signal saved_fifo_to_apl_long_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0); -signal last_fifo_to_apl_read : std_logic; -signal last_fifo_to_int_read : std_logic; + signal saved_fifo_to_int_long_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0); + signal saved_fifo_to_apl_long_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0); + signal last_fifo_to_apl_read : std_logic; + signal last_fifo_to_int_read : std_logic; signal state_bits_to_int, state_bits_to_apl : std_logic_vector(2 downto 0); -- signal slave_running, next_slave_running, get_slave_running, release_slave_running : std_logic; @@ -315,39 +208,6 @@ begin INT_SLAVE_PACKET_NUM_OUT <= (others => '0'); end generate; - STAT_FIFO_TO_INT(2 downto 0) <= fifo_to_int_data_in(2 downto 0); - STAT_FIFO_TO_INT(3) <= fifo_to_int_write; - STAT_FIFO_TO_INT(6 downto 4) <= buf_INT_MASTER_PACKET_NUM_OUT; - STAT_FIFO_TO_INT(7) <= buf_INT_MASTER_DATAREADY_OUT; - STAT_FIFO_TO_INT(8) <= INT_MASTER_READ_IN; - STAT_FIFO_TO_INT(11 downto 9) <= fifo_to_int_data_out(2 downto 0); - STAT_FIFO_TO_INT(12) <= fifo_to_int_read; - STAT_FIFO_TO_INT(13) <= fifo_to_int_read_before; - STAT_FIFO_TO_INT(14) <= fifo_to_int_full; - STAT_FIFO_TO_INT(15) <= fifo_to_int_empty; - STAT_FIFO_TO_INT(16) <= next_APL_DATAREADY_OUT; - STAT_FIFO_TO_INT(17) <= sbuf_to_apl_free; - STAT_FIFO_TO_INT(18) <= fifo_to_apl_read_before; - STAT_FIFO_TO_INT(19) <= slave_running; - STAT_FIFO_TO_INT(20) <= buf_APL_RUN_OUT; - STAT_FIFO_TO_INT(21) <= master_running; - STAT_FIFO_TO_INT(24 downto 22) <= next_INT_MASTER_PACKET_NUM_OUT; - STAT_FIFO_TO_INT(25) <= next_INT_MASTER_DATAREADY_OUT; - STAT_FIFO_TO_INT(28 downto 26) <= state_bits_to_int; - STAT_FIFO_TO_INT(31 downto 29) <= state_bits_to_apl; - - STAT_FIFO_TO_APL(2 downto 0) <= fifo_to_apl_data_in(2 downto 0); - STAT_FIFO_TO_APL(3) <= fifo_to_apl_write; - STAT_FIFO_TO_APL(7 downto 4) <= (others => '0'); - STAT_FIFO_TO_APL(9 downto 8) <= fifo_to_apl_data_out(1 downto 0); - STAT_FIFO_TO_APL(10) <= reg_APL_DATAREADY_OUT; - STAT_FIFO_TO_APL(11) <= fifo_to_apl_read; - STAT_FIFO_TO_APL(12) <= INT_SLAVE_DATAREADY_IN; - STAT_FIFO_TO_APL(13) <= reg_INT_SLAVE_READ_OUT; - STAT_FIFO_TO_APL(14) <= fifo_to_apl_full; - STAT_FIFO_TO_APL(15) <= fifo_to_apl_empty; - --STAT_FIFO_TO_APL(13 downto 12) <= (others => '0'); - STAT_FIFO_TO_APL(31 downto 16) <= (others => '0'); --------------------------------------- -- a sbuf (to_int direction) @@ -907,23 +767,29 @@ INT_MASTER_DATAREADY_OUT <= buf_INT_MASTER_DATAREADY_OUT; state_to_int <= IDLE; end if; send_trm_wrong_addr <= '0'; - sequence_counter <= (others => '0'); fifo_was_not_empty <= '0'; elsif CLK_EN = '1' then state_to_apl <= next_state_to_apl; state_to_int <= next_state_to_int; send_trm_wrong_addr <= next_send_trm_wrong_addr; - sequence_counter <= next_sequence_counter; fifo_was_not_empty <= next_fifo_was_not_empty; end if; end if; end process; + PROC_SEQ_CNT : process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' or CTRL_SEQNR_RESET = '1' then + sequence_counter <= (others => '0'); + else + sequence_counter <= next_sequence_counter; + end if; + end if; + end process; + ---------------------------------------- --- ---------------------------------------- process(CLK) begin if rising_edge(CLK) then @@ -938,51 +804,29 @@ INT_MASTER_DATAREADY_OUT <= buf_INT_MASTER_DATAREADY_OUT; end process; - --get target address from active APL - gentarget1: if API_TYPE = 1 generate - combined_header_F1 <= APL_TARGET_ADDRESS_IN; - end generate; - --save target address for passive api - gentarget0: if API_TYPE = 0 generate - reg_hdr_f1: process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - combined_header_F1 <= (others => '1'); - elsif current_fifo_to_apl_packet_type = TYPE_HDR and fifo_to_apl_long_packet_num_out = c_F0 and CLK_EN = '1' then - combined_header_F1 <= fifo_to_apl_data_out; - end if; - end if; - end process; - end generate; - -- combine the next header - combined_header_F0 <= APL_MY_ADDRESS_IN; - combined_header_F2 <= APL_LENGTH_IN; - combined_header_F3(15 downto 14) <= (others => '0'); -- LAY - combined_header_F3(13 downto 12) <= (others => '0'); -- VERS - combined_header_F3(11 downto 4) <= sequence_counter; -- SEQNR - combined_header_F3(3 downto 0) <= APL_DTYPE_IN; - combined_trailer_F0 <= (others => '0'); - combined_trailer_F1 <= APL_ERROR_PATTERN_IN(31 downto 16); - combined_trailer_F2 <= APL_ERROR_PATTERN_IN(15 downto 1) & endpoint_reached when API_TYPE = c_API_PASSIVE else - APL_ERROR_PATTERN_IN(15 downto 0); - combined_trailer_F3(15 downto 14) <= (others => '0'); -- res. - combined_trailer_F3(13 downto 12) <= (others => '0'); -- VERS - combined_trailer_F3(11 downto 4) <= sequence_counter; -- SEQNR - combined_trailer_F3(3 downto 0) <= APL_DTYPE_IN; + + +--------------------------------------------------------------------- +--Connection to FIFOs +--------------------------------------------------------------------- + -- connect Transmitter port fifo_to_int_data_in <= APL_DATA_IN; fifo_to_int_packet_num_in <= APL_PACKET_NUM_IN(2) & APL_PACKET_NUM_IN(0); fifo_to_int_write <= (APL_DATAREADY_IN and not fifo_to_int_full); - APL_READ_OUT <= not fifo_to_int_full; -- APL has to stop writing + APL_READ_OUT <= not fifo_to_int_full; -- APL has to stop writing -- connect receiver fifo_to_apl_data_in <= INT_SLAVE_DATA_IN; fifo_to_apl_packet_num_in <= INT_SLAVE_PACKET_NUM_IN(2) & INT_SLAVE_PACKET_NUM_IN(0); INT_SLAVE_READ_OUT <= reg_INT_SLAVE_READ_OUT; +--------------------------------------------------------------------- +--Running Signals +--------------------------------------------------------------------- + RUN_OUT_gen : process(CLK) begin if rising_edge(CLK) then @@ -1028,7 +872,47 @@ INT_MASTER_DATAREADY_OUT <= buf_INT_MASTER_DATAREADY_OUT; end if; end process; - REG3 : process(CLK) +--------------------------------------------------------------------- +--Header & Trailer Words +--------------------------------------------------------------------- + + + --get target address from active APL + gentarget1: if API_TYPE = 1 generate + combined_header_F1 <= APL_TARGET_ADDRESS_IN; + end generate; + + --save target address for passive api + gentarget0: if API_TYPE = 0 generate + reg_hdr_f1: process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + combined_header_F1 <= (others => '1'); + elsif current_fifo_to_apl_packet_type = TYPE_HDR and fifo_to_apl_long_packet_num_out = c_F0 and CLK_EN = '1' then + combined_header_F1 <= fifo_to_apl_data_out; + end if; + end if; + end process; + end generate; + + -- combine the next header + combined_header_F0 <= APL_MY_ADDRESS_IN; + combined_header_F2 <= APL_LENGTH_IN; + combined_header_F3(15 downto 14) <= (others => '0'); -- LAY + combined_header_F3(13 downto 12) <= (others => '0'); -- VERS + combined_header_F3(11 downto 4) <= sequence_counter; -- SEQNR + combined_header_F3(3 downto 0) <= APL_DTYPE_IN; + combined_trailer_F0 <= (others => '0'); + combined_trailer_F1 <= APL_ERROR_PATTERN_IN(31 downto 16); + combined_trailer_F2 <= APL_ERROR_PATTERN_IN(15 downto 1) & endpoint_reached when API_TYPE = c_API_PASSIVE else + APL_ERROR_PATTERN_IN(15 downto 0); + combined_trailer_F3(15 downto 14) <= (others => '0'); -- res. + combined_trailer_F3(13 downto 12) <= (others => '0'); -- VERS + combined_trailer_F3(11 downto 4) <= sequence_counter; -- SEQNR + combined_trailer_F3(3 downto 0) <= APL_DTYPE_IN; + + PROC_REG3 : process(CLK) begin if rising_edge(CLK) then if update_registered_trailer = '1' then @@ -1057,10 +941,11 @@ INT_MASTER_DATAREADY_OUT <= buf_INT_MASTER_DATAREADY_OUT; end if; end process; ---for simulation only - +--------------------------------------------------------------------- +--Decode FSM states +--------------------------------------------------------------------- - process(state_to_apl) + process(state_to_apl) begin case state_to_apl is when sa_IDLE => state_bits_to_apl <= "000"; @@ -1070,6 +955,7 @@ INT_MASTER_DATAREADY_OUT <= buf_INT_MASTER_DATAREADY_OUT; when others => state_bits_to_apl <= "111"; end case; end process; + process(state_to_int) begin case state_to_int is @@ -1084,5 +970,43 @@ INT_MASTER_DATAREADY_OUT <= buf_INT_MASTER_DATAREADY_OUT; end case; end process; +--------------------------------------------------------------------- +--Debugging & Status Signals +--------------------------------------------------------------------- + + STAT_FIFO_TO_INT(2 downto 0) <= fifo_to_int_data_in(2 downto 0); + STAT_FIFO_TO_INT(3) <= fifo_to_int_write; + STAT_FIFO_TO_INT(6 downto 4) <= buf_INT_MASTER_PACKET_NUM_OUT; + STAT_FIFO_TO_INT(7) <= buf_INT_MASTER_DATAREADY_OUT; + STAT_FIFO_TO_INT(8) <= INT_MASTER_READ_IN; + STAT_FIFO_TO_INT(11 downto 9) <= fifo_to_int_data_out(2 downto 0); + STAT_FIFO_TO_INT(12) <= fifo_to_int_read; + STAT_FIFO_TO_INT(13) <= fifo_to_int_read_before; + STAT_FIFO_TO_INT(14) <= fifo_to_int_full; + STAT_FIFO_TO_INT(15) <= fifo_to_int_empty; + STAT_FIFO_TO_INT(16) <= next_APL_DATAREADY_OUT; + STAT_FIFO_TO_INT(17) <= sbuf_to_apl_free; + STAT_FIFO_TO_INT(18) <= fifo_to_apl_read_before; + STAT_FIFO_TO_INT(19) <= slave_running; + STAT_FIFO_TO_INT(20) <= buf_APL_RUN_OUT; + STAT_FIFO_TO_INT(21) <= master_running; + STAT_FIFO_TO_INT(24 downto 22) <= next_INT_MASTER_PACKET_NUM_OUT; + STAT_FIFO_TO_INT(25) <= next_INT_MASTER_DATAREADY_OUT; + STAT_FIFO_TO_INT(28 downto 26) <= state_bits_to_int; + STAT_FIFO_TO_INT(31 downto 29) <= state_bits_to_apl; + + STAT_FIFO_TO_APL(2 downto 0) <= fifo_to_apl_data_in(2 downto 0); + STAT_FIFO_TO_APL(3) <= fifo_to_apl_write; + STAT_FIFO_TO_APL(7 downto 4) <= (others => '0'); + STAT_FIFO_TO_APL(9 downto 8) <= fifo_to_apl_data_out(1 downto 0); + STAT_FIFO_TO_APL(10) <= reg_APL_DATAREADY_OUT; + STAT_FIFO_TO_APL(11) <= fifo_to_apl_read; + STAT_FIFO_TO_APL(12) <= INT_SLAVE_DATAREADY_IN; + STAT_FIFO_TO_APL(13) <= reg_INT_SLAVE_READ_OUT; + STAT_FIFO_TO_APL(14) <= fifo_to_apl_full; + STAT_FIFO_TO_APL(15) <= fifo_to_apl_empty; + --STAT_FIFO_TO_APL(13 downto 12) <= (others => '0'); + STAT_FIFO_TO_APL(31 downto 16) <= (others => '0'); + end architecture; diff --git a/trb_net16_endpoint_hades_full.vhd b/trb_net16_endpoint_hades_full.vhd index dba9ab8..24ee93b 100644 --- a/trb_net16_endpoint_hades_full.vhd +++ b/trb_net16_endpoint_hades_full.vhd @@ -390,6 +390,7 @@ architecture trb_net16_endpoint_hades_full_arch of trb_net16_endpoint_hades_full INT_SLAVE_READ_OUT : out std_logic; -- Status and control port + CTRL_SEQNR_RESET : in std_logic; STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0); STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0) ); @@ -598,6 +599,7 @@ signal buf_STAT_REPLY_OBUF_DEBUG : std_logic_vector (32*4-1 downto 0); signal REGIO_REGIO_STAT : std_logic_vector(31 downto 0); signal buf_COMMON_STAT_REG_IN: std_logic_vector(std_COMSTATREG*32-1 downto 0); +signal buf_REGIO_COMMON_CTRL_REG_OUT : std_logic_vector(std_COMCTRLREG*32-1 downto 0); signal buf_IDRAM_DATA_IN : std_logic_vector(15 downto 0); signal buf_IDRAM_DATA_OUT : std_logic_vector(15 downto 0); @@ -740,6 +742,7 @@ begin INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), INT_SLAVE_READ_OUT => buf_to_apl_INIT_READ(i), -- Status and control port + CTRL_SEQNR_RESET => buf_REGIO_COMMON_CTRL_REG_OUT(10), STAT_FIFO_TO_INT => buf_api_stat_fifo_to_int((i+1)*32-1 downto i*32), STAT_FIFO_TO_APL => buf_api_stat_fifo_to_apl((i+1)*32-1 downto i*32) ); @@ -901,7 +904,7 @@ begin TIMER_US_TICK => TIMER_US_TICK_OUT, --Common Register in / out COMMON_STAT_REG_IN => buf_COMMON_STAT_REG_IN, - COMMON_CTRL_REG_OUT => REGIO_COMMON_CTRL_REG_OUT, + COMMON_CTRL_REG_OUT => buf_REGIO_COMMON_CTRL_REG_OUT, --Custom Register in / out REGISTERS_IN => REGIO_REGISTERS_IN, REGISTERS_OUT => REGIO_REGISTERS_OUT, @@ -1070,6 +1073,7 @@ begin ); buf_CTRL_GEN <= IOBUF_CTRL_GEN; +REGIO_COMMON_CTRL_REG_OUT <= buf_REGIO_COMMON_CTRL_REG_OUT; --STAT_DEBUG_1 <= STAT_MPLEX; STAT_DEBUG_2(3 downto 0) <= MED_IO_DATA_OUT(7*16+3 downto 7*16); diff --git a/trb_net_components.vhd b/trb_net_components.vhd new file mode 100644 index 0000000..892c1b7 --- /dev/null +++ b/trb_net_components.vhd @@ -0,0 +1,121 @@ +library ieee; +use ieee.std_logic_1164.all; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; +library work; +use work.trb_net_std.all; + +package trb_net_components is + + component trb_net16_dummy_fifo is + port ( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0); + PACKET_NUM_IN : in std_logic_vector(1 downto 0); + WRITE_ENABLE_IN : in std_logic; + DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0); + PACKET_NUM_OUT : out std_logic_vector(1 downto 0); + READ_ENABLE_IN : in std_logic; + FULL_OUT : out std_logic; + EMPTY_OUT : out std_logic + ); + end component; + + component trb_net16_fifo is + generic ( + USE_VENDOR_CORES : integer range 0 to 1 := c_NO; + DEPTH : integer := 6 + ); + port ( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0); + PACKET_NUM_IN : in std_logic_vector(1 downto 0); + WRITE_ENABLE_IN : in std_logic; + DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0); + PACKET_NUM_OUT : out std_logic_vector(1 downto 0); + READ_ENABLE_IN : in std_logic; + FULL_OUT : out std_logic; + EMPTY_OUT : out std_logic + ); + end component; + + component trb_net16_sbuf is + generic ( + VERSION : integer := 0 + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- port to combinatorial logic + COMB_DATAREADY_IN : in STD_LOGIC; --comb logic provides data word + COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle + COMB_READ_IN : in STD_LOGIC; --comb logic IS reading + COMB_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + COMB_PACKET_NUM_IN: in STD_LOGIC_VECTOR(c_NUM_WIDTH-1 downto 0); + -- Port to synchronous output. + SYN_DATAREADY_OUT : out STD_LOGIC; + SYN_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + SYN_PACKET_NUM_OUT: out STD_LOGIC_VECTOR(c_NUM_WIDTH-1 downto 0); + SYN_READ_IN : in STD_LOGIC; + -- Status and control port + STAT_BUFFER : out STD_LOGIC + ); + end component; + + component trb_net16_term is + generic ( + USE_APL_PORT : integer range 0 to 1 := c_YES; + --even when 0, ERROR_PACKET_IN is used for automatic replys + SECURE_MODE : integer range 0 to 1 := std_TERM_SECURE_MODE + --if secure_mode is not used, apl must provide error pattern and dtype until + --next trigger comes in. In secure mode these need to be available while relase_trg is high + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + INT_DATAREADY_OUT : out std_logic; + INT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_READ_IN : in std_logic; + + INT_DATAREADY_IN : in std_logic; + INT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_READ_OUT : out std_logic; + + APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0) + ); + end component; + + component trb_net_sbuf is + generic ( + DATA_WIDTH : integer := 18; + VERSION: integer := std_SBUF_VERSION); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- port to combinatorial logic + COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word + COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle + COMB_READ_IN: in STD_LOGIC; --comb logic IS reading + COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); + SYN_DATAREADY_OUT: out STD_LOGIC; + SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); + SYN_READ_IN: in STD_LOGIC; + STAT_BUFFER: out STD_LOGIC + ); + end component; + + +end package; \ No newline at end of file -- 2.43.0