From b5a8392decdb1b64c2ab8d229c00349f96c86c2b Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Fri, 3 Jul 2009 07:31:21 +0000 Subject: [PATCH] attilio: new fifo with registered out --- ..._8192depth_36width_dual_thresh_reg_out.vhd | 3085 +++++++++++++++++ 1 file changed, 3085 insertions(+) create mode 100644 design/fifo_8192depth_36width_dual_thresh_reg_out.vhd diff --git a/design/fifo_8192depth_36width_dual_thresh_reg_out.vhd b/design/fifo_8192depth_36width_dual_thresh_reg_out.vhd new file mode 100644 index 0000000..40d64e6 --- /dev/null +++ b/design/fifo_8192depth_36width_dual_thresh_reg_out.vhd @@ -0,0 +1,3085 @@ +-- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 4.6 +--/storage120/lattice/isplever7.2/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 8192 -width 36 -depth 8192 -regout -no_enable -pe 0 -pe2 0 -pf 7000 -fill -e + +-- Fri Jun 26 10:07:43 2009 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity fifo_8192depth_36width_dual_thresh_reg_out is + port ( + Data: in std_logic_vector(35 downto 0); + Clock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + AmEmptySetThresh: in std_logic_vector(12 downto 0); + AmEmptyClrThresh: in std_logic_vector(12 downto 0); + Q: out std_logic_vector(35 downto 0); + WCNT: out std_logic_vector(13 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostEmpty: out std_logic; + AlmostFull: out std_logic); +end fifo_8192depth_36width_dual_thresh_reg_out; + +architecture Structure of fifo_8192depth_36width_dual_thresh_reg_out is + + -- internal signal declarations + signal invout_2: std_logic; + signal invout_1: std_logic; + signal rden_i_inv: std_logic; + signal invout_0: std_logic; + signal r_nw: std_logic; + signal rcnt_reg_12_inv: std_logic; + signal fcnt_en: std_logic; + signal empty_i: std_logic; + signal empty_d: std_logic; + signal full_i: std_logic; + signal full_d: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wptr_5: std_logic; + signal wptr_6: std_logic; + signal wptr_7: std_logic; + signal wptr_8: std_logic; + signal wptr_9: std_logic; + signal wptr_10: std_logic; + signal wptr_11: std_logic; + signal wptr_12: std_logic; + signal wptr_13: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal rptr_5: std_logic; + signal rptr_6: std_logic; + signal rptr_7: std_logic; + signal rptr_8: std_logic; + signal rptr_9: std_logic; + signal rptr_10: std_logic; + signal rptr_13: std_logic; + signal rptr_11: std_logic; + signal rptr_12: std_logic; + signal rcnt_reg_13: std_logic; + signal ae: std_logic; + signal ae_d: std_logic; + signal ifcount_0: std_logic; + signal ifcount_1: std_logic; + signal bdcnt_bctr_ci: std_logic; + signal ifcount_2: std_logic; + signal ifcount_3: std_logic; + signal co0: std_logic; + signal ifcount_4: std_logic; + signal ifcount_5: std_logic; + signal co1: std_logic; + signal ifcount_6: std_logic; + signal ifcount_7: std_logic; + signal co2: std_logic; + signal ifcount_8: std_logic; + signal ifcount_9: std_logic; + signal co3: std_logic; + signal ifcount_10: std_logic; + signal ifcount_11: std_logic; + signal co4: std_logic; + signal ifcount_12: std_logic; + signal ifcount_13: std_logic; + signal co6: std_logic; + signal cnt_con: std_logic; + signal co5: std_logic; + signal cmp_ci: std_logic; + signal co0_1: std_logic; + signal co1_1: std_logic; + signal co2_1: std_logic; + signal co3_1: std_logic; + signal co4_1: std_logic; + signal co5_1: std_logic; + signal cmp_le_1: std_logic; + signal cmp_le_1_c: std_logic; + signal cmp_ci_1: std_logic; + signal fcount_0: std_logic; + signal fcount_1: std_logic; + signal co0_2: std_logic; + signal fcount_2: std_logic; + signal co1_2: std_logic; + signal co2_2: std_logic; + signal co3_2: std_logic; + signal co4_2: std_logic; + signal co5_2: std_logic; + signal wren_i: std_logic; + signal wren_i_inv: std_logic; + signal cmp_ge_d1: std_logic; + signal cmp_ge_d1_c: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_ctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0_3: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1_3: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2_3: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co3_3: std_logic; + signal iwcount_10: std_logic; + signal iwcount_11: std_logic; + signal co4_3: std_logic; + signal iwcount_12: std_logic; + signal iwcount_13: std_logic; + signal co6_1: std_logic; + signal wcount_13: std_logic; + signal co5_3: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_ctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_4: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_4: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_4: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co3_4: std_logic; + signal ircount_10: std_logic; + signal ircount_11: std_logic; + signal co4_4: std_logic; + signal ircount_12: std_logic; + signal ircount_13: std_logic; + signal co6_2: std_logic; + signal rcount_13: std_logic; + signal co5_4: std_logic; + signal ffidata_0: std_logic; + signal mdout1_3_0: std_logic; + signal mdout1_2_0: std_logic; + signal mdout1_1_0: std_logic; + signal mdout1_0_0: std_logic; + signal ffidata_1: std_logic; + signal mdout1_3_1: std_logic; + signal mdout1_2_1: std_logic; + signal mdout1_1_1: std_logic; + signal mdout1_0_1: std_logic; + signal ffidata_2: std_logic; + signal mdout1_3_2: std_logic; + signal mdout1_2_2: std_logic; + signal mdout1_1_2: std_logic; + signal mdout1_0_2: std_logic; + signal ffidata_3: std_logic; + signal mdout1_3_3: std_logic; + signal mdout1_2_3: std_logic; + signal mdout1_1_3: std_logic; + signal mdout1_0_3: std_logic; + signal ffidata_4: std_logic; + signal mdout1_3_4: std_logic; + signal mdout1_2_4: std_logic; + signal mdout1_1_4: std_logic; + signal mdout1_0_4: std_logic; + signal ffidata_5: std_logic; + signal mdout1_3_5: std_logic; + signal mdout1_2_5: std_logic; + signal mdout1_1_5: std_logic; + signal mdout1_0_5: std_logic; + signal ffidata_6: std_logic; + signal mdout1_3_6: std_logic; + signal mdout1_2_6: std_logic; + signal mdout1_1_6: std_logic; + signal mdout1_0_6: std_logic; + signal ffidata_7: std_logic; + signal mdout1_3_7: std_logic; + signal mdout1_2_7: std_logic; + signal mdout1_1_7: std_logic; + signal mdout1_0_7: std_logic; + signal ffidata_8: std_logic; + signal mdout1_3_8: std_logic; + signal mdout1_2_8: std_logic; + signal mdout1_1_8: std_logic; + signal mdout1_0_8: std_logic; + signal ffidata_9: std_logic; + signal mdout1_3_9: std_logic; + signal mdout1_2_9: std_logic; + signal mdout1_1_9: std_logic; + signal mdout1_0_9: std_logic; + signal ffidata_10: std_logic; + signal mdout1_3_10: std_logic; + signal mdout1_2_10: std_logic; + signal mdout1_1_10: std_logic; + signal mdout1_0_10: std_logic; + signal ffidata_11: std_logic; + signal mdout1_3_11: std_logic; + signal mdout1_2_11: std_logic; + signal mdout1_1_11: std_logic; + signal mdout1_0_11: std_logic; + signal ffidata_12: std_logic; + signal mdout1_3_12: std_logic; + signal mdout1_2_12: std_logic; + signal mdout1_1_12: std_logic; + signal mdout1_0_12: std_logic; + signal ffidata_13: std_logic; + signal mdout1_3_13: std_logic; + signal mdout1_2_13: std_logic; + signal mdout1_1_13: std_logic; + signal mdout1_0_13: std_logic; + signal ffidata_14: std_logic; + signal mdout1_3_14: std_logic; + signal mdout1_2_14: std_logic; + signal mdout1_1_14: std_logic; + signal mdout1_0_14: std_logic; + signal ffidata_15: std_logic; + signal mdout1_3_15: std_logic; + signal mdout1_2_15: std_logic; + signal mdout1_1_15: std_logic; + signal mdout1_0_15: std_logic; + signal ffidata_16: std_logic; + signal mdout1_3_16: std_logic; + signal mdout1_2_16: std_logic; + signal mdout1_1_16: std_logic; + signal mdout1_0_16: std_logic; + signal ffidata_17: std_logic; + signal mdout1_3_17: std_logic; + signal mdout1_2_17: std_logic; + signal mdout1_1_17: std_logic; + signal mdout1_0_17: std_logic; + signal ffidata_18: std_logic; + signal mdout1_3_18: std_logic; + signal mdout1_2_18: std_logic; + signal mdout1_1_18: std_logic; + signal mdout1_0_18: std_logic; + signal ffidata_19: std_logic; + signal mdout1_3_19: std_logic; + signal mdout1_2_19: std_logic; + signal mdout1_1_19: std_logic; + signal mdout1_0_19: std_logic; + signal ffidata_20: std_logic; + signal mdout1_3_20: std_logic; + signal mdout1_2_20: std_logic; + signal mdout1_1_20: std_logic; + signal mdout1_0_20: std_logic; + signal ffidata_21: std_logic; + signal mdout1_3_21: std_logic; + signal mdout1_2_21: std_logic; + signal mdout1_1_21: std_logic; + signal mdout1_0_21: std_logic; + signal ffidata_22: std_logic; + signal mdout1_3_22: std_logic; + signal mdout1_2_22: std_logic; + signal mdout1_1_22: std_logic; + signal mdout1_0_22: std_logic; + signal ffidata_23: std_logic; + signal mdout1_3_23: std_logic; + signal mdout1_2_23: std_logic; + signal mdout1_1_23: std_logic; + signal mdout1_0_23: std_logic; + signal ffidata_24: std_logic; + signal mdout1_3_24: std_logic; + signal mdout1_2_24: std_logic; + signal mdout1_1_24: std_logic; + signal mdout1_0_24: std_logic; + signal ffidata_25: std_logic; + signal mdout1_3_25: std_logic; + signal mdout1_2_25: std_logic; + signal mdout1_1_25: std_logic; + signal mdout1_0_25: std_logic; + signal ffidata_26: std_logic; + signal mdout1_3_26: std_logic; + signal mdout1_2_26: std_logic; + signal mdout1_1_26: std_logic; + signal mdout1_0_26: std_logic; + signal ffidata_27: std_logic; + signal mdout1_3_27: std_logic; + signal mdout1_2_27: std_logic; + signal mdout1_1_27: std_logic; + signal mdout1_0_27: std_logic; + signal ffidata_28: std_logic; + signal mdout1_3_28: std_logic; + signal mdout1_2_28: std_logic; + signal mdout1_1_28: std_logic; + signal mdout1_0_28: std_logic; + signal ffidata_29: std_logic; + signal mdout1_3_29: std_logic; + signal mdout1_2_29: std_logic; + signal mdout1_1_29: std_logic; + signal mdout1_0_29: std_logic; + signal ffidata_30: std_logic; + signal mdout1_3_30: std_logic; + signal mdout1_2_30: std_logic; + signal mdout1_1_30: std_logic; + signal mdout1_0_30: std_logic; + signal ffidata_31: std_logic; + signal mdout1_3_31: std_logic; + signal mdout1_2_31: std_logic; + signal mdout1_1_31: std_logic; + signal mdout1_0_31: std_logic; + signal ffidata_32: std_logic; + signal mdout1_3_32: std_logic; + signal mdout1_2_32: std_logic; + signal mdout1_1_32: std_logic; + signal mdout1_0_32: std_logic; + signal ffidata_33: std_logic; + signal mdout1_3_33: std_logic; + signal mdout1_2_33: std_logic; + signal mdout1_1_33: std_logic; + signal mdout1_0_33: std_logic; + signal ffidata_34: std_logic; + signal mdout1_3_34: std_logic; + signal mdout1_2_34: std_logic; + signal mdout1_1_34: std_logic; + signal mdout1_0_34: std_logic; + signal ffidata_35: std_logic; + signal rptr_12_ff: std_logic; + signal rptr_11_ff: std_logic; + signal mdout1_3_35: std_logic; + signal mdout1_2_35: std_logic; + signal mdout1_1_35: std_logic; + signal mdout1_0_35: std_logic; + signal rcnt_sub_0: std_logic; + signal r_nw_inv_inv: std_logic; + signal rcount_0: std_logic; + signal r_nw_inv: std_logic; + signal wcount_0: std_logic; + signal rcnt_sub_1: std_logic; + signal rcnt_sub_2: std_logic; + signal co0_5: std_logic; + signal rcount_1: std_logic; + signal rcount_2: std_logic; + signal wcount_1: std_logic; + signal wcount_2: std_logic; + signal rcnt_sub_3: std_logic; + signal rcnt_sub_4: std_logic; + signal co1_5: std_logic; + signal rcount_3: std_logic; + signal rcount_4: std_logic; + signal wcount_3: std_logic; + signal wcount_4: std_logic; + signal rcnt_sub_5: std_logic; + signal rcnt_sub_6: std_logic; + signal co2_5: std_logic; + signal rcount_5: std_logic; + signal rcount_6: std_logic; + signal wcount_5: std_logic; + signal wcount_6: std_logic; + signal rcnt_sub_7: std_logic; + signal rcnt_sub_8: std_logic; + signal co3_5: std_logic; + signal rcount_7: std_logic; + signal rcount_8: std_logic; + signal wcount_7: std_logic; + signal wcount_8: std_logic; + signal rcnt_sub_9: std_logic; + signal rcnt_sub_10: std_logic; + signal co4_5: std_logic; + signal rcount_9: std_logic; + signal rcount_10: std_logic; + signal wcount_9: std_logic; + signal wcount_10: std_logic; + signal rcnt_sub_11: std_logic; + signal rcnt_sub_12: std_logic; + signal co5_5: std_logic; + signal rcount_11: std_logic; + signal rcount_12: std_logic; + signal wcount_11: std_logic; + signal wcount_12: std_logic; + signal rcnt_sub_13: std_logic; + signal co6_3: std_logic; + signal rcnt_sub_msb: std_logic; + signal cmp_ci_2: std_logic; + signal co0_6: std_logic; + signal co1_6: std_logic; + signal co2_6: std_logic; + signal co3_6: std_logic; + signal co4_6: std_logic; + signal co5_6: std_logic; + signal ae_set_clrsig: std_logic; + signal ae_set_setsig: std_logic; + signal ae_set_d: std_logic; + signal ae_set_d_c: std_logic; + signal rden_i: std_logic; + signal cmp_ci_3: std_logic; + signal rcnt_reg_0: std_logic; + signal rcnt_reg_1: std_logic; + signal co0_7: std_logic; + signal rcnt_reg_2: std_logic; + signal rcnt_reg_3: std_logic; + signal co1_7: std_logic; + signal rcnt_reg_4: std_logic; + signal rcnt_reg_5: std_logic; + signal co2_7: std_logic; + signal rcnt_reg_6: std_logic; + signal rcnt_reg_7: std_logic; + signal co3_7: std_logic; + signal rcnt_reg_8: std_logic; + signal rcnt_reg_9: std_logic; + signal co4_7: std_logic; + signal rcnt_reg_10: std_logic; + signal rcnt_reg_11: std_logic; + signal co5_7: std_logic; + signal rcnt_reg_12: std_logic; + signal ae_clr_clrsig: std_logic; + signal ae_clr_setsig: std_logic; + signal ae_clr_d: std_logic; + signal ae_clr_d_c: std_logic; + signal cmp_ci_4: std_logic; + signal fcount_3: std_logic; + signal fcount_4: std_logic; + signal co0_8: std_logic; + signal fcount_5: std_logic; + signal fcount_6: std_logic; + signal co1_8: std_logic; + signal fcount_7: std_logic; + signal fcount_8: std_logic; + signal co2_8: std_logic; + signal fcount_9: std_logic; + signal fcount_10: std_logic; + signal co3_8: std_logic; + signal scuba_vhi: std_logic; + signal fcount_11: std_logic; + signal fcount_12: std_logic; + signal co4_8: std_logic; + signal fcount_13: std_logic; + signal af_d: std_logic; + signal af_d_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component ALEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; LE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component CB2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CON: in std_logic; CO: out std_logic; NC0: out std_logic; + NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FSUB2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; BI: in std_logic; BOUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component MUX41 + port (D0: in std_logic; D1: in std_logic; D2: in std_logic; + D3: in std_logic; SD1: in std_logic; SD2: in std_logic; + Z: out std_logic); + end component; + component ROM16X1 + -- synopsys translate_off + generic (initval : in String); + -- synopsys translate_on + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component DP16KB + -- synopsys translate_off + generic (GSR : in String; WRITEMODE_B : in String; + CSDECODE_B : in std_logic_vector(2 downto 0); + CSDECODE_A : in std_logic_vector(2 downto 0); + WRITEMODE_A : in String; RESETMODE : in String; + REGMODE_B : in String; REGMODE_A : in String; + DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer); + -- synopsys translate_on + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic; + CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic; + CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute initval : string; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute CSDECODE_B : string; + attribute CSDECODE_A : string; + attribute WRITEMODE_B : string; + attribute WRITEMODE_A : string; + attribute RESETMODE : string; + attribute REGMODE_B : string; + attribute REGMODE_A : string; + attribute DATA_WIDTH_B : string; + attribute DATA_WIDTH_A : string; + attribute GSR : string; + attribute initval of LUT4_2 : label is "0x3232"; + attribute initval of LUT4_1 : label is "0x3232"; + attribute initval of LUT4_0 : label is "0x4450"; + attribute MEM_LPC_FILE of pdp_ram_0_0_15 : label is "fifo_8192depth_36width_dual_thresh_reg_out.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_15 : label is ""; + attribute CSDECODE_B of pdp_ram_0_0_15 : label is "0b000"; + attribute CSDECODE_A of pdp_ram_0_0_15 : label is "0b000"; + attribute WRITEMODE_B of pdp_ram_0_0_15 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_0_0_15 : label is "NORMAL"; + attribute GSR of pdp_ram_0_0_15 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_0_0_15 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_0_0_15 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_0_0_15 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_0_0_15 : label is "9"; + attribute DATA_WIDTH_A of pdp_ram_0_0_15 : label is "9"; + attribute MEM_LPC_FILE of pdp_ram_0_1_14 : label is "fifo_8192depth_36width_dual_thresh_reg_out.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_1_14 : label is ""; + attribute CSDECODE_B of pdp_ram_0_1_14 : label is "0b000"; + attribute CSDECODE_A of pdp_ram_0_1_14 : label is "0b000"; + attribute WRITEMODE_B of pdp_ram_0_1_14 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_0_1_14 : label is "NORMAL"; + attribute GSR of pdp_ram_0_1_14 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_0_1_14 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_0_1_14 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_0_1_14 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_0_1_14 : label is "9"; + attribute DATA_WIDTH_A of pdp_ram_0_1_14 : label is "9"; + attribute MEM_LPC_FILE of pdp_ram_0_2_13 : label is "fifo_8192depth_36width_dual_thresh_reg_out.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_2_13 : label is ""; + attribute CSDECODE_B of pdp_ram_0_2_13 : label is "0b000"; + attribute CSDECODE_A of pdp_ram_0_2_13 : label is "0b000"; + attribute WRITEMODE_B of pdp_ram_0_2_13 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_0_2_13 : label is "NORMAL"; + attribute GSR of pdp_ram_0_2_13 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_0_2_13 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_0_2_13 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_0_2_13 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_0_2_13 : label is "9"; + attribute DATA_WIDTH_A of pdp_ram_0_2_13 : label is "9"; + attribute MEM_LPC_FILE of pdp_ram_0_3_12 : label is "fifo_8192depth_36width_dual_thresh_reg_out.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_3_12 : label is ""; + attribute CSDECODE_B of pdp_ram_0_3_12 : label is "0b000"; + attribute CSDECODE_A of pdp_ram_0_3_12 : label is "0b000"; + attribute WRITEMODE_B of pdp_ram_0_3_12 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_0_3_12 : label is "NORMAL"; + attribute GSR of pdp_ram_0_3_12 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_0_3_12 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_0_3_12 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_0_3_12 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_0_3_12 : label is "9"; + attribute DATA_WIDTH_A of pdp_ram_0_3_12 : label is "9"; + attribute MEM_LPC_FILE of pdp_ram_1_0_11 : label is "fifo_8192depth_36width_dual_thresh_reg_out.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_0_11 : label is ""; + attribute CSDECODE_B of pdp_ram_1_0_11 : label is "0b001"; + attribute CSDECODE_A of pdp_ram_1_0_11 : label is "0b001"; + attribute WRITEMODE_B of pdp_ram_1_0_11 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_1_0_11 : label is "NORMAL"; + attribute GSR of pdp_ram_1_0_11 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_1_0_11 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_1_0_11 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_1_0_11 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_1_0_11 : label is "9"; + attribute DATA_WIDTH_A of pdp_ram_1_0_11 : label is "9"; + attribute MEM_LPC_FILE of pdp_ram_1_1_10 : label is "fifo_8192depth_36width_dual_thresh_reg_out.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_1_10 : label is ""; + attribute CSDECODE_B of pdp_ram_1_1_10 : label is "0b001"; + attribute CSDECODE_A of pdp_ram_1_1_10 : label is "0b001"; + attribute WRITEMODE_B of pdp_ram_1_1_10 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_1_1_10 : label is "NORMAL"; + attribute GSR of pdp_ram_1_1_10 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_1_1_10 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_1_1_10 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_1_1_10 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_1_1_10 : label is "9"; + attribute DATA_WIDTH_A of pdp_ram_1_1_10 : label is "9"; + attribute MEM_LPC_FILE of pdp_ram_1_2_9 : label is "fifo_8192depth_36width_dual_thresh_reg_out.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_2_9 : label is ""; + attribute CSDECODE_B of pdp_ram_1_2_9 : label is "0b001"; + attribute CSDECODE_A of pdp_ram_1_2_9 : label is "0b001"; + attribute WRITEMODE_B of pdp_ram_1_2_9 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_1_2_9 : label is "NORMAL"; + attribute GSR of pdp_ram_1_2_9 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_1_2_9 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_1_2_9 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_1_2_9 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_1_2_9 : label is "9"; + attribute DATA_WIDTH_A of pdp_ram_1_2_9 : label is "9"; + attribute MEM_LPC_FILE of pdp_ram_1_3_8 : label is "fifo_8192depth_36width_dual_thresh_reg_out.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_3_8 : label is ""; + attribute CSDECODE_B of pdp_ram_1_3_8 : label is "0b001"; + attribute CSDECODE_A of pdp_ram_1_3_8 : label is "0b001"; + attribute WRITEMODE_B of pdp_ram_1_3_8 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_1_3_8 : label is "NORMAL"; + attribute GSR of pdp_ram_1_3_8 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_1_3_8 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_1_3_8 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_1_3_8 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_1_3_8 : label is "9"; + attribute DATA_WIDTH_A of pdp_ram_1_3_8 : label is "9"; + attribute MEM_LPC_FILE of pdp_ram_2_0_7 : label is "fifo_8192depth_36width_dual_thresh_reg_out.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_0_7 : label is ""; + attribute CSDECODE_B of pdp_ram_2_0_7 : label is "0b010"; + attribute CSDECODE_A of pdp_ram_2_0_7 : label is "0b010"; + attribute WRITEMODE_B of pdp_ram_2_0_7 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_2_0_7 : label is "NORMAL"; + attribute GSR of pdp_ram_2_0_7 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_2_0_7 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_2_0_7 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_2_0_7 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_2_0_7 : label is "9"; + attribute DATA_WIDTH_A of pdp_ram_2_0_7 : label is "9"; + attribute MEM_LPC_FILE of pdp_ram_2_1_6 : label is "fifo_8192depth_36width_dual_thresh_reg_out.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_1_6 : label is ""; + attribute CSDECODE_B of pdp_ram_2_1_6 : label is "0b010"; + attribute CSDECODE_A of pdp_ram_2_1_6 : label is "0b010"; + attribute WRITEMODE_B of pdp_ram_2_1_6 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_2_1_6 : label is "NORMAL"; + attribute GSR of pdp_ram_2_1_6 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_2_1_6 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_2_1_6 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_2_1_6 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_2_1_6 : label is "9"; + attribute DATA_WIDTH_A of pdp_ram_2_1_6 : label is "9"; + attribute MEM_LPC_FILE of pdp_ram_2_2_5 : label is "fifo_8192depth_36width_dual_thresh_reg_out.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_2_5 : label is ""; + attribute CSDECODE_B of pdp_ram_2_2_5 : label is "0b010"; + attribute CSDECODE_A of pdp_ram_2_2_5 : label is "0b010"; + attribute WRITEMODE_B of pdp_ram_2_2_5 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_2_2_5 : label is "NORMAL"; + attribute GSR of pdp_ram_2_2_5 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_2_2_5 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_2_2_5 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_2_2_5 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_2_2_5 : label is "9"; + attribute DATA_WIDTH_A of pdp_ram_2_2_5 : label is "9"; + attribute MEM_LPC_FILE of pdp_ram_2_3_4 : label is "fifo_8192depth_36width_dual_thresh_reg_out.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_3_4 : label is ""; + attribute CSDECODE_B of pdp_ram_2_3_4 : label is "0b010"; + attribute CSDECODE_A of pdp_ram_2_3_4 : label is "0b010"; + attribute WRITEMODE_B of pdp_ram_2_3_4 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_2_3_4 : label is "NORMAL"; + attribute GSR of pdp_ram_2_3_4 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_2_3_4 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_2_3_4 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_2_3_4 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_2_3_4 : label is "9"; + attribute DATA_WIDTH_A of pdp_ram_2_3_4 : label is "9"; + attribute MEM_LPC_FILE of pdp_ram_3_0_3 : label is "fifo_8192depth_36width_dual_thresh_reg_out.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_0_3 : label is ""; + attribute CSDECODE_B of pdp_ram_3_0_3 : label is "0b011"; + attribute CSDECODE_A of pdp_ram_3_0_3 : label is "0b011"; + attribute WRITEMODE_B of pdp_ram_3_0_3 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_3_0_3 : label is "NORMAL"; + attribute GSR of pdp_ram_3_0_3 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_3_0_3 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_3_0_3 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_3_0_3 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_3_0_3 : label is "9"; + attribute DATA_WIDTH_A of pdp_ram_3_0_3 : label is "9"; + attribute MEM_LPC_FILE of pdp_ram_3_1_2 : label is "fifo_8192depth_36width_dual_thresh_reg_out.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_1_2 : label is ""; + attribute CSDECODE_B of pdp_ram_3_1_2 : label is "0b011"; + attribute CSDECODE_A of pdp_ram_3_1_2 : label is "0b011"; + attribute WRITEMODE_B of pdp_ram_3_1_2 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_3_1_2 : label is "NORMAL"; + attribute GSR of pdp_ram_3_1_2 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_3_1_2 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_3_1_2 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_3_1_2 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_3_1_2 : label is "9"; + attribute DATA_WIDTH_A of pdp_ram_3_1_2 : label is "9"; + attribute MEM_LPC_FILE of pdp_ram_3_2_1 : label is "fifo_8192depth_36width_dual_thresh_reg_out.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_2_1 : label is ""; + attribute CSDECODE_B of pdp_ram_3_2_1 : label is "0b011"; + attribute CSDECODE_A of pdp_ram_3_2_1 : label is "0b011"; + attribute WRITEMODE_B of pdp_ram_3_2_1 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_3_2_1 : label is "NORMAL"; + attribute GSR of pdp_ram_3_2_1 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_3_2_1 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_3_2_1 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_3_2_1 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_3_2_1 : label is "9"; + attribute DATA_WIDTH_A of pdp_ram_3_2_1 : label is "9"; + attribute MEM_LPC_FILE of pdp_ram_3_3_0 : label is "fifo_8192depth_36width_dual_thresh_reg_out.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_3_0 : label is ""; + attribute CSDECODE_B of pdp_ram_3_3_0 : label is "0b011"; + attribute CSDECODE_A of pdp_ram_3_3_0 : label is "0b011"; + attribute WRITEMODE_B of pdp_ram_3_3_0 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_3_3_0 : label is "NORMAL"; + attribute GSR of pdp_ram_3_3_0 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_3_3_0 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_3_3_0 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_3_3_0 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_3_3_0 : label is "9"; + attribute DATA_WIDTH_A of pdp_ram_3_3_0 : label is "9"; + attribute GSR of FF_125 : label is "ENABLED"; + attribute GSR of FF_124 : label is "ENABLED"; + attribute GSR of FF_123 : label is "ENABLED"; + attribute GSR of FF_122 : label is "ENABLED"; + attribute GSR of FF_121 : label is "ENABLED"; + attribute GSR of FF_120 : label is "ENABLED"; + attribute GSR of FF_119 : label is "ENABLED"; + attribute GSR of FF_118 : label is "ENABLED"; + attribute GSR of FF_117 : label is "ENABLED"; + attribute GSR of FF_116 : label is "ENABLED"; + attribute GSR of FF_115 : label is "ENABLED"; + attribute GSR of FF_114 : label is "ENABLED"; + attribute GSR of FF_113 : label is "ENABLED"; + attribute GSR of FF_112 : label is "ENABLED"; + attribute GSR of FF_111 : label is "ENABLED"; + attribute GSR of FF_110 : label is "ENABLED"; + attribute GSR of FF_109 : label is "ENABLED"; + attribute GSR of FF_108 : label is "ENABLED"; + attribute GSR of FF_107 : label is "ENABLED"; + attribute GSR of FF_106 : label is "ENABLED"; + attribute GSR of FF_105 : label is "ENABLED"; + attribute GSR of FF_104 : label is "ENABLED"; + attribute GSR of FF_103 : label is "ENABLED"; + attribute GSR of FF_102 : label is "ENABLED"; + attribute GSR of FF_101 : label is "ENABLED"; + attribute GSR of FF_100 : label is "ENABLED"; + attribute GSR of FF_99 : label is "ENABLED"; + attribute GSR of FF_98 : label is "ENABLED"; + attribute GSR of FF_97 : label is "ENABLED"; + attribute GSR of FF_96 : label is "ENABLED"; + attribute GSR of FF_95 : label is "ENABLED"; + attribute GSR of FF_94 : label is "ENABLED"; + attribute GSR of FF_93 : label is "ENABLED"; + attribute GSR of FF_92 : label is "ENABLED"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + AND2_t9: AND2 + port map (A=>WrEn, B=>invout_2, Z=>wren_i); + + INV_7: INV + port map (A=>full_i, Z=>invout_2); + + AND2_t8: AND2 + port map (A=>RdEn, B=>invout_1, Z=>rden_i); + + INV_6: INV + port map (A=>empty_i, Z=>invout_1); + + AND2_t7: AND2 + port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con); + + XOR2_t6: XOR2 + port map (A=>wren_i, B=>rden_i, Z=>fcnt_en); + + INV_5: INV + port map (A=>rden_i, Z=>rden_i_inv); + + INV_4: INV + port map (A=>wren_i, Z=>wren_i_inv); + + LUT4_2: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x3232") + -- synopsys translate_on + port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, + AD0=>empty_i, DO0=>empty_d); + + LUT4_1: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x3232") + -- synopsys translate_on + port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, + AD0=>full_i, DO0=>full_d); + + AND2_t5: AND2 + port map (A=>rden_i, B=>invout_0, Z=>r_nw); + + INV_3: INV + port map (A=>wren_i, Z=>invout_0); + + INV_2: INV + port map (A=>r_nw, Z=>r_nw_inv); + + XOR2_t4: XOR2 + port map (A=>wcount_13, B=>rcount_13, Z=>rcnt_sub_msb); + + INV_1: INV + port map (A=>r_nw_inv, Z=>r_nw_inv_inv); + + INV_0: INV + port map (A=>rcnt_reg_12, Z=>rcnt_reg_12_inv); + + AND2_t3: AND2 + port map (A=>rcnt_reg_13, B=>rcnt_reg_12_inv, Z=>ae_set_clrsig); + + AND2_t2: AND2 + port map (A=>rcnt_reg_13, B=>rcnt_reg_12, Z=>ae_set_setsig); + + AND2_t1: AND2 + port map (A=>rcnt_reg_13, B=>rcnt_reg_12_inv, Z=>ae_clr_clrsig); + + AND2_t0: AND2 + port map (A=>rcnt_reg_13, B=>rcnt_reg_12, Z=>ae_clr_setsig); + + LUT4_0: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x4450") + -- synopsys translate_on + port map (AD3=>ae, AD2=>ae_set_d, AD1=>ae_clr_d, AD0=>scuba_vlo, + DO0=>ae_d); + + pdp_ram_0_0_15: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + -- synopsys translate_on + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, + CSA0=>wptr_11, CSA1=>wptr_12, CSA2=>scuba_vlo, RSTA=>Reset, + DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, + DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, + DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, + DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, + DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, + DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, + ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, + ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, + ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, + ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, + CLKB=>Clock, WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>rptr_12, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0, DOB1=>mdout1_0_1, + DOB2=>mdout1_0_2, DOB3=>mdout1_0_3, DOB4=>mdout1_0_4, + DOB5=>mdout1_0_5, DOB6=>mdout1_0_6, DOB7=>mdout1_0_7, + DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_0_1_14: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + -- synopsys translate_on + port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11), + DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14), + DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17), + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, + ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, + ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, + ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>Clock, WEB=>scuba_vlo, + CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_0_9, DOB1=>mdout1_0_10, DOB2=>mdout1_0_11, + DOB3=>mdout1_0_12, DOB4=>mdout1_0_13, DOB5=>mdout1_0_14, + DOB6=>mdout1_0_15, DOB7=>mdout1_0_16, DOB8=>mdout1_0_17, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_0_2_13: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + -- synopsys translate_on + port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20), + DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23), + DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26), + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, + ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, + ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, + ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>Clock, WEB=>scuba_vlo, + CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_0_18, DOB1=>mdout1_0_19, DOB2=>mdout1_0_20, + DOB3=>mdout1_0_21, DOB4=>mdout1_0_22, DOB5=>mdout1_0_23, + DOB6=>mdout1_0_24, DOB7=>mdout1_0_25, DOB8=>mdout1_0_26, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_0_3_12: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + -- synopsys translate_on + port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29), + DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32), + DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35), + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, + ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, + ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, + ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>Clock, WEB=>scuba_vlo, + CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_0_27, DOB1=>mdout1_0_28, DOB2=>mdout1_0_29, + DOB3=>mdout1_0_30, DOB4=>mdout1_0_31, DOB5=>mdout1_0_32, + DOB6=>mdout1_0_33, DOB7=>mdout1_0_34, DOB8=>mdout1_0_35, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_1_0_11: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + -- synopsys translate_on + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, + CSA0=>wptr_11, CSA1=>wptr_12, CSA2=>scuba_vlo, RSTA=>Reset, + DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, + DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, + DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, + DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, + DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, + DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, + ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, + ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, + ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, + ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, + CLKB=>Clock, WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>rptr_12, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0, DOB1=>mdout1_1_1, + DOB2=>mdout1_1_2, DOB3=>mdout1_1_3, DOB4=>mdout1_1_4, + DOB5=>mdout1_1_5, DOB6=>mdout1_1_6, DOB7=>mdout1_1_7, + DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_1_1_10: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + -- synopsys translate_on + port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11), + DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14), + DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17), + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, + ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, + ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, + ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>Clock, WEB=>scuba_vlo, + CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_1_9, DOB1=>mdout1_1_10, DOB2=>mdout1_1_11, + DOB3=>mdout1_1_12, DOB4=>mdout1_1_13, DOB5=>mdout1_1_14, + DOB6=>mdout1_1_15, DOB7=>mdout1_1_16, DOB8=>mdout1_1_17, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_1_2_9: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + -- synopsys translate_on + port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20), + DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23), + DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26), + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, + ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, + ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, + ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>Clock, WEB=>scuba_vlo, + CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_1_18, DOB1=>mdout1_1_19, DOB2=>mdout1_1_20, + DOB3=>mdout1_1_21, DOB4=>mdout1_1_22, DOB5=>mdout1_1_23, + DOB6=>mdout1_1_24, DOB7=>mdout1_1_25, DOB8=>mdout1_1_26, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_1_3_8: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + -- synopsys translate_on + port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29), + DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32), + DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35), + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, + ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, + ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, + ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>Clock, WEB=>scuba_vlo, + CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_1_27, DOB1=>mdout1_1_28, DOB2=>mdout1_1_29, + DOB3=>mdout1_1_30, DOB4=>mdout1_1_31, DOB5=>mdout1_1_32, + DOB6=>mdout1_1_33, DOB7=>mdout1_1_34, DOB8=>mdout1_1_35, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_2_0_7: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + -- synopsys translate_on + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, + CSA0=>wptr_11, CSA1=>wptr_12, CSA2=>scuba_vlo, RSTA=>Reset, + DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, + DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, + DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, + DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, + DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, + DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, + ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, + ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, + ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, + ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, + CLKB=>Clock, WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>rptr_12, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_2_0, DOB1=>mdout1_2_1, + DOB2=>mdout1_2_2, DOB3=>mdout1_2_3, DOB4=>mdout1_2_4, + DOB5=>mdout1_2_5, DOB6=>mdout1_2_6, DOB7=>mdout1_2_7, + DOB8=>mdout1_2_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_2_1_6: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + -- synopsys translate_on + port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11), + DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14), + DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17), + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, + ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, + ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, + ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>Clock, WEB=>scuba_vlo, + CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_2_9, DOB1=>mdout1_2_10, DOB2=>mdout1_2_11, + DOB3=>mdout1_2_12, DOB4=>mdout1_2_13, DOB5=>mdout1_2_14, + DOB6=>mdout1_2_15, DOB7=>mdout1_2_16, DOB8=>mdout1_2_17, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_2_2_5: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + -- synopsys translate_on + port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20), + DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23), + DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26), + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, + ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, + ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, + ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>Clock, WEB=>scuba_vlo, + CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_2_18, DOB1=>mdout1_2_19, DOB2=>mdout1_2_20, + DOB3=>mdout1_2_21, DOB4=>mdout1_2_22, DOB5=>mdout1_2_23, + DOB6=>mdout1_2_24, DOB7=>mdout1_2_25, DOB8=>mdout1_2_26, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_2_3_4: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + -- synopsys translate_on + port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29), + DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32), + DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35), + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, + ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, + ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, + ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>Clock, WEB=>scuba_vlo, + CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_2_27, DOB1=>mdout1_2_28, DOB2=>mdout1_2_29, + DOB3=>mdout1_2_30, DOB4=>mdout1_2_31, DOB5=>mdout1_2_32, + DOB6=>mdout1_2_33, DOB7=>mdout1_2_34, DOB8=>mdout1_2_35, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_3_0_3: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + -- synopsys translate_on + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, + CSA0=>wptr_11, CSA1=>wptr_12, CSA2=>scuba_vlo, RSTA=>Reset, + DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, + DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, + DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, + DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, + DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, + DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, + ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, + ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, + ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, + ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, + CLKB=>Clock, WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>rptr_12, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_3_0, DOB1=>mdout1_3_1, + DOB2=>mdout1_3_2, DOB3=>mdout1_3_3, DOB4=>mdout1_3_4, + DOB5=>mdout1_3_5, DOB6=>mdout1_3_6, DOB7=>mdout1_3_7, + DOB8=>mdout1_3_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_3_1_2: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + -- synopsys translate_on + port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11), + DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14), + DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17), + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, + ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, + ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, + ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>Clock, WEB=>scuba_vlo, + CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_3_9, DOB1=>mdout1_3_10, DOB2=>mdout1_3_11, + DOB3=>mdout1_3_12, DOB4=>mdout1_3_13, DOB5=>mdout1_3_14, + DOB6=>mdout1_3_15, DOB7=>mdout1_3_16, DOB8=>mdout1_3_17, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_3_2_1: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + -- synopsys translate_on + port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20), + DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23), + DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26), + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, + ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, + ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, + ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>Clock, WEB=>scuba_vlo, + CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_3_18, DOB1=>mdout1_3_19, DOB2=>mdout1_3_20, + DOB3=>mdout1_3_21, DOB4=>mdout1_3_22, DOB5=>mdout1_3_23, + DOB6=>mdout1_3_24, DOB7=>mdout1_3_25, DOB8=>mdout1_3_26, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + pdp_ram_3_3_0: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + -- synopsys translate_on + port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29), + DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32), + DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35), + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, + ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, + ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, + ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>Clock, WEB=>scuba_vlo, + CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>scuba_vlo, RSTB=>Reset, + DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, + DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, + DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, + DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, + DOB0=>mdout1_3_27, DOB1=>mdout1_3_28, DOB2=>mdout1_3_29, + DOB3=>mdout1_3_30, DOB4=>mdout1_3_31, DOB5=>mdout1_3_32, + DOB6=>mdout1_3_33, DOB7=>mdout1_3_34, DOB8=>mdout1_3_35, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + FF_125: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_0); + + FF_124: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_1); + + FF_123: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_2); + + FF_122: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_3); + + FF_121: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_4); + + FF_120: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_5); + + FF_119: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_6); + + FF_118: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_7); + + FF_117: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_8); + + FF_116: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_9); + + FF_115: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_10); + + FF_114: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_11, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_11); + + FF_113: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_12, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_12); + + FF_112: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_13, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_13); + + FF_111: FD1S3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i); + + FF_110: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i); + + FF_109: FD1P3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset, + Q=>wcount_0); + + FF_108: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_1); + + FF_107: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_2); + + FF_106: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_3); + + FF_105: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_4); + + FF_104: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_5); + + FF_103: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_6); + + FF_102: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_7); + + FF_101: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_8); + + FF_100: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_9); + + FF_99: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_10); + + FF_98: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_11, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_11); + + FF_97: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_12, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_12); + + FF_96: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_13, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_13); + + FF_95: FD1P3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset, + Q=>rcount_0); + + FF_94: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_1); + + FF_93: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_2); + + FF_92: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_3); + + FF_91: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_4); + + FF_90: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_5); + + FF_89: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_6); + + FF_88: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_7); + + FF_87: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_8); + + FF_86: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_9); + + FF_85: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_10); + + FF_84: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_11, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_11); + + FF_83: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_12, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_12); + + FF_82: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_13, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_13); + + FF_81: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_0); + + FF_80: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_1); + + FF_79: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_2); + + FF_78: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_3); + + FF_77: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_4); + + FF_76: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_5); + + FF_75: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_6); + + FF_74: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_7); + + FF_73: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_8); + + FF_72: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_9); + + FF_71: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_10, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_10); + + FF_70: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_11, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_11); + + FF_69: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_12, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_12); + + FF_68: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_13, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_13); + + FF_67: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_0); + + FF_66: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_1); + + FF_65: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_2); + + FF_64: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_3); + + FF_63: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_4); + + FF_62: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_5); + + FF_61: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_6, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_6); + + FF_60: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_7, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_7); + + FF_59: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_8, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_8); + + FF_58: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_9, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_9); + + FF_57: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_10, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_10); + + FF_56: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_11, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_11); + + FF_55: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_12, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_12); + + FF_54: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_13, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_13); + + FF_53: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rptr_11, SP=>rden_i, CK=>Clock, CD=>scuba_vlo, + Q=>rptr_11_ff); + + FF_52: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rptr_12, SP=>rden_i, CK=>Clock, CD=>scuba_vlo, + Q=>rptr_12_ff); + + FF_51: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_0, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(0)); + + FF_50: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_1, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(1)); + + FF_49: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_2, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(2)); + + FF_48: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_3, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(3)); + + FF_47: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_4, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(4)); + + FF_46: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_5, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(5)); + + FF_45: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_6, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(6)); + + FF_44: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_7, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(7)); + + FF_43: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_8, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(8)); + + FF_42: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_9, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(9)); + + FF_41: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_10, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(10)); + + FF_40: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_11, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(11)); + + FF_39: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_12, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(12)); + + FF_38: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_13, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(13)); + + FF_37: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_14, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(14)); + + FF_36: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_15, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(15)); + + FF_35: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_16, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(16)); + + FF_34: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_17, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(17)); + + FF_33: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_18, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(18)); + + FF_32: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_19, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(19)); + + FF_31: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_20, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(20)); + + FF_30: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_21, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(21)); + + FF_29: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_22, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(22)); + + FF_28: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_23, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(23)); + + FF_27: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_24, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(24)); + + FF_26: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_25, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(25)); + + FF_25: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_26, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(26)); + + FF_24: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_27, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(27)); + + FF_23: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_28, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(28)); + + FF_22: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_29, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(29)); + + FF_21: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_30, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(30)); + + FF_20: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_31, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(31)); + + FF_19: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_32, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(32)); + + FF_18: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_33, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(33)); + + FF_17: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_34, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(34)); + + FF_16: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_35, SP=>scuba_vhi, CK=>Clock, CD=>Reset, + Q=>Q(35)); + + FF_15: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcnt_sub_0, CK=>Clock, CD=>Reset, Q=>rcnt_reg_0); + + FF_14: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcnt_sub_1, CK=>Clock, CD=>Reset, Q=>rcnt_reg_1); + + FF_13: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcnt_sub_2, CK=>Clock, CD=>Reset, Q=>rcnt_reg_2); + + FF_12: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcnt_sub_3, CK=>Clock, CD=>Reset, Q=>rcnt_reg_3); + + FF_11: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcnt_sub_4, CK=>Clock, CD=>Reset, Q=>rcnt_reg_4); + + FF_10: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcnt_sub_5, CK=>Clock, CD=>Reset, Q=>rcnt_reg_5); + + FF_9: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcnt_sub_6, CK=>Clock, CD=>Reset, Q=>rcnt_reg_6); + + FF_8: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcnt_sub_7, CK=>Clock, CD=>Reset, Q=>rcnt_reg_7); + + FF_7: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcnt_sub_8, CK=>Clock, CD=>Reset, Q=>rcnt_reg_8); + + FF_6: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcnt_sub_9, CK=>Clock, CD=>Reset, Q=>rcnt_reg_9); + + FF_5: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcnt_sub_10, CK=>Clock, CD=>Reset, Q=>rcnt_reg_10); + + FF_4: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcnt_sub_11, CK=>Clock, CD=>Reset, Q=>rcnt_reg_11); + + FF_3: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcnt_sub_12, CK=>Clock, CD=>Reset, Q=>rcnt_reg_12); + + FF_2: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcnt_sub_13, CK=>Clock, CD=>Reset, Q=>rcnt_reg_13); + + FF_1: FD1S3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ae_d, CK=>Clock, PD=>Reset, Q=>ae); + + FF_0: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>af_d, CK=>Clock, CD=>Reset, Q=>AlmostFull); + + bdcnt_bctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, + CI=>scuba_vlo, COUT=>bdcnt_bctr_ci, S0=>open, S1=>open); + + bdcnt_bctr_0: CB2 + port map (CI=>bdcnt_bctr_ci, PC0=>fcount_0, PC1=>fcount_1, + CON=>cnt_con, CO=>co0, NC0=>ifcount_0, NC1=>ifcount_1); + + bdcnt_bctr_1: CB2 + port map (CI=>co0, PC0=>fcount_2, PC1=>fcount_3, CON=>cnt_con, + CO=>co1, NC0=>ifcount_2, NC1=>ifcount_3); + + bdcnt_bctr_2: CB2 + port map (CI=>co1, PC0=>fcount_4, PC1=>fcount_5, CON=>cnt_con, + CO=>co2, NC0=>ifcount_4, NC1=>ifcount_5); + + bdcnt_bctr_3: CB2 + port map (CI=>co2, PC0=>fcount_6, PC1=>fcount_7, CON=>cnt_con, + CO=>co3, NC0=>ifcount_6, NC1=>ifcount_7); + + bdcnt_bctr_4: CB2 + port map (CI=>co3, PC0=>fcount_8, PC1=>fcount_9, CON=>cnt_con, + CO=>co4, NC0=>ifcount_8, NC1=>ifcount_9); + + bdcnt_bctr_5: CB2 + port map (CI=>co4, PC0=>fcount_10, PC1=>fcount_11, CON=>cnt_con, + CO=>co5, NC0=>ifcount_10, NC1=>ifcount_11); + + bdcnt_bctr_6: CB2 + port map (CI=>co5, PC0=>fcount_12, PC1=>fcount_13, CON=>cnt_con, + CO=>co6, NC0=>ifcount_12, NC1=>ifcount_13); + + e_cmp_ci_a: FADD2B + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, + S1=>open); + + e_cmp_0: ALEB2 + port map (A0=>fcount_0, A1=>fcount_1, B0=>rden_i, B1=>scuba_vlo, + CI=>cmp_ci, LE=>co0_1); + + e_cmp_1: ALEB2 + port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co0_1, LE=>co1_1); + + e_cmp_2: ALEB2 + port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co1_1, LE=>co2_1); + + e_cmp_3: ALEB2 + port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co2_1, LE=>co3_1); + + e_cmp_4: ALEB2 + port map (A0=>fcount_8, A1=>fcount_9, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co3_1, LE=>co4_1); + + e_cmp_5: ALEB2 + port map (A0=>fcount_10, A1=>fcount_11, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co4_1, LE=>co5_1); + + e_cmp_6: ALEB2 + port map (A0=>fcount_12, A1=>fcount_13, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co5_1, LE=>cmp_le_1_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>cmp_le_1_c, COUT=>open, S0=>cmp_le_1, + S1=>open); + + g_cmp_ci_a: FADD2B + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, + S1=>open); + + g_cmp_0: AGEB2 + port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i, + CI=>cmp_ci_1, GE=>co0_2); + + g_cmp_1: AGEB2 + port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i, + CI=>co0_2, GE=>co1_2); + + g_cmp_2: AGEB2 + port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i, + CI=>co1_2, GE=>co2_2); + + g_cmp_3: AGEB2 + port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i, + CI=>co2_2, GE=>co3_2); + + g_cmp_4: AGEB2 + port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i, + CI=>co3_2, GE=>co4_2); + + g_cmp_5: AGEB2 + port map (A0=>fcount_10, A1=>fcount_11, B0=>wren_i, B1=>wren_i, + CI=>co4_2, GE=>co5_2); + + g_cmp_6: AGEB2 + port map (A0=>fcount_12, A1=>fcount_13, B0=>wren_i, + B1=>wren_i_inv, CI=>co5_2, GE=>cmp_ge_d1_c); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>cmp_ge_d1_c, COUT=>open, S0=>cmp_ge_d1, + S1=>open); + + w_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_ctr_ci, S0=>open, + S1=>open); + + w_ctr_0: CU2 + port map (CI=>w_ctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0_3, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_ctr_1: CU2 + port map (CI=>co0_3, PC0=>wcount_2, PC1=>wcount_3, CO=>co1_3, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_ctr_2: CU2 + port map (CI=>co1_3, PC0=>wcount_4, PC1=>wcount_5, CO=>co2_3, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_ctr_3: CU2 + port map (CI=>co2_3, PC0=>wcount_6, PC1=>wcount_7, CO=>co3_3, + NC0=>iwcount_6, NC1=>iwcount_7); + + w_ctr_4: CU2 + port map (CI=>co3_3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4_3, + NC0=>iwcount_8, NC1=>iwcount_9); + + w_ctr_5: CU2 + port map (CI=>co4_3, PC0=>wcount_10, PC1=>wcount_11, CO=>co5_3, + NC0=>iwcount_10, NC1=>iwcount_11); + + w_ctr_6: CU2 + port map (CI=>co5_3, PC0=>wcount_12, PC1=>wcount_13, CO=>co6_1, + NC0=>iwcount_12, NC1=>iwcount_13); + + r_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_ctr_ci, S0=>open, + S1=>open); + + r_ctr_0: CU2 + port map (CI=>r_ctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_4, + NC0=>ircount_0, NC1=>ircount_1); + + r_ctr_1: CU2 + port map (CI=>co0_4, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_4, + NC0=>ircount_2, NC1=>ircount_3); + + r_ctr_2: CU2 + port map (CI=>co1_4, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_4, + NC0=>ircount_4, NC1=>ircount_5); + + r_ctr_3: CU2 + port map (CI=>co2_4, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_4, + NC0=>ircount_6, NC1=>ircount_7); + + r_ctr_4: CU2 + port map (CI=>co3_4, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_4, + NC0=>ircount_8, NC1=>ircount_9); + + r_ctr_5: CU2 + port map (CI=>co4_4, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_4, + NC0=>ircount_10, NC1=>ircount_11); + + r_ctr_6: CU2 + port map (CI=>co5_4, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_2, + NC0=>ircount_12, NC1=>ircount_13); + + mux_35: MUX41 + port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0, + D3=>mdout1_3_0, SD1=>rptr_11_ff, SD2=>rptr_12_ff, + Z=>ffidata_0); + + mux_34: MUX41 + port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1, + D3=>mdout1_3_1, SD1=>rptr_11_ff, SD2=>rptr_12_ff, + Z=>ffidata_1); + + mux_33: MUX41 + port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2, + D3=>mdout1_3_2, SD1=>rptr_11_ff, SD2=>rptr_12_ff, + Z=>ffidata_2); + + mux_32: MUX41 + port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3, + D3=>mdout1_3_3, SD1=>rptr_11_ff, SD2=>rptr_12_ff, + Z=>ffidata_3); + + mux_31: MUX41 + port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4, + D3=>mdout1_3_4, SD1=>rptr_11_ff, SD2=>rptr_12_ff, + Z=>ffidata_4); + + mux_30: MUX41 + port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5, + D3=>mdout1_3_5, SD1=>rptr_11_ff, SD2=>rptr_12_ff, + Z=>ffidata_5); + + mux_29: MUX41 + port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6, + D3=>mdout1_3_6, SD1=>rptr_11_ff, SD2=>rptr_12_ff, + Z=>ffidata_6); + + mux_28: MUX41 + port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7, + D3=>mdout1_3_7, SD1=>rptr_11_ff, SD2=>rptr_12_ff, + Z=>ffidata_7); + + mux_27: MUX41 + port map (D0=>mdout1_0_8, D1=>mdout1_1_8, D2=>mdout1_2_8, + D3=>mdout1_3_8, SD1=>rptr_11_ff, SD2=>rptr_12_ff, + Z=>ffidata_8); + + mux_26: MUX41 + port map (D0=>mdout1_0_9, D1=>mdout1_1_9, D2=>mdout1_2_9, + D3=>mdout1_3_9, SD1=>rptr_11_ff, SD2=>rptr_12_ff, + Z=>ffidata_9); + + mux_25: MUX41 + port map (D0=>mdout1_0_10, D1=>mdout1_1_10, D2=>mdout1_2_10, + D3=>mdout1_3_10, SD1=>rptr_11_ff, SD2=>rptr_12_ff, + Z=>ffidata_10); + + mux_24: MUX41 + port map (D0=>mdout1_0_11, D1=>mdout1_1_11, D2=>mdout1_2_11, + D3=>mdout1_3_11, SD1=>rptr_11_ff, SD2=>rptr_12_ff, + Z=>ffidata_11); + + mux_23: MUX41 + port map (D0=>mdout1_0_12, D1=>mdout1_1_12, D2=>mdout1_2_12, + D3=>mdout1_3_12, SD1=>rptr_11_ff, SD2=>rptr_12_ff, + Z=>ffidata_12); + + mux_22: MUX41 + port map (D0=>mdout1_0_13, D1=>mdout1_1_13, D2=>mdout1_2_13, + D3=>mdout1_3_13, SD1=>rptr_11_ff, SD2=>rptr_12_ff, + Z=>ffidata_13); + + mux_21: MUX41 + port map (D0=>mdout1_0_14, D1=>mdout1_1_14, D2=>mdout1_2_14, + D3=>mdout1_3_14, SD1=>rptr_11_ff, SD2=>rptr_12_ff, + Z=>ffidata_14); + + mux_20: MUX41 + port map (D0=>mdout1_0_15, D1=>mdout1_1_15, D2=>mdout1_2_15, + D3=>mdout1_3_15, SD1=>rptr_11_ff, SD2=>rptr_12_ff, + Z=>ffidata_15); + + mux_19: MUX41 + port map (D0=>mdout1_0_16, D1=>mdout1_1_16, D2=>mdout1_2_16, + D3=>mdout1_3_16, SD1=>rptr_11_ff, SD2=>rptr_12_ff, + Z=>ffidata_16); + + mux_18: MUX41 + port map (D0=>mdout1_0_17, D1=>mdout1_1_17, D2=>mdout1_2_17, + D3=>mdout1_3_17, SD1=>rptr_11_ff, SD2=>rptr_12_ff, + Z=>ffidata_17); + + mux_17: MUX41 + port map (D0=>mdout1_0_18, D1=>mdout1_1_18, D2=>mdout1_2_18, + D3=>mdout1_3_18, SD1=>rptr_11_ff, SD2=>rptr_12_ff, + Z=>ffidata_18); + + mux_16: MUX41 + port map (D0=>mdout1_0_19, D1=>mdout1_1_19, D2=>mdout1_2_19, + D3=>mdout1_3_19, SD1=>rptr_11_ff, SD2=>rptr_12_ff, + Z=>ffidata_19); + + mux_15: MUX41 + port map (D0=>mdout1_0_20, D1=>mdout1_1_20, D2=>mdout1_2_20, + D3=>mdout1_3_20, SD1=>rptr_11_ff, SD2=>rptr_12_ff, + Z=>ffidata_20); + + mux_14: MUX41 + port map (D0=>mdout1_0_21, D1=>mdout1_1_21, D2=>mdout1_2_21, + D3=>mdout1_3_21, SD1=>rptr_11_ff, SD2=>rptr_12_ff, + Z=>ffidata_21); + + mux_13: MUX41 + port map (D0=>mdout1_0_22, D1=>mdout1_1_22, D2=>mdout1_2_22, + D3=>mdout1_3_22, SD1=>rptr_11_ff, SD2=>rptr_12_ff, + Z=>ffidata_22); + + mux_12: MUX41 + port map (D0=>mdout1_0_23, D1=>mdout1_1_23, D2=>mdout1_2_23, + D3=>mdout1_3_23, SD1=>rptr_11_ff, SD2=>rptr_12_ff, + Z=>ffidata_23); + + mux_11: MUX41 + port map (D0=>mdout1_0_24, D1=>mdout1_1_24, D2=>mdout1_2_24, + D3=>mdout1_3_24, SD1=>rptr_11_ff, SD2=>rptr_12_ff, + Z=>ffidata_24); + + mux_10: MUX41 + port map (D0=>mdout1_0_25, D1=>mdout1_1_25, D2=>mdout1_2_25, + D3=>mdout1_3_25, SD1=>rptr_11_ff, SD2=>rptr_12_ff, + Z=>ffidata_25); + + mux_9: MUX41 + port map (D0=>mdout1_0_26, D1=>mdout1_1_26, D2=>mdout1_2_26, + D3=>mdout1_3_26, SD1=>rptr_11_ff, SD2=>rptr_12_ff, + Z=>ffidata_26); + + mux_8: MUX41 + port map (D0=>mdout1_0_27, D1=>mdout1_1_27, D2=>mdout1_2_27, + D3=>mdout1_3_27, SD1=>rptr_11_ff, SD2=>rptr_12_ff, + Z=>ffidata_27); + + mux_7: MUX41 + port map (D0=>mdout1_0_28, D1=>mdout1_1_28, D2=>mdout1_2_28, + D3=>mdout1_3_28, SD1=>rptr_11_ff, SD2=>rptr_12_ff, + Z=>ffidata_28); + + mux_6: MUX41 + port map (D0=>mdout1_0_29, D1=>mdout1_1_29, D2=>mdout1_2_29, + D3=>mdout1_3_29, SD1=>rptr_11_ff, SD2=>rptr_12_ff, + Z=>ffidata_29); + + mux_5: MUX41 + port map (D0=>mdout1_0_30, D1=>mdout1_1_30, D2=>mdout1_2_30, + D3=>mdout1_3_30, SD1=>rptr_11_ff, SD2=>rptr_12_ff, + Z=>ffidata_30); + + mux_4: MUX41 + port map (D0=>mdout1_0_31, D1=>mdout1_1_31, D2=>mdout1_2_31, + D3=>mdout1_3_31, SD1=>rptr_11_ff, SD2=>rptr_12_ff, + Z=>ffidata_31); + + mux_3: MUX41 + port map (D0=>mdout1_0_32, D1=>mdout1_1_32, D2=>mdout1_2_32, + D3=>mdout1_3_32, SD1=>rptr_11_ff, SD2=>rptr_12_ff, + Z=>ffidata_32); + + mux_2: MUX41 + port map (D0=>mdout1_0_33, D1=>mdout1_1_33, D2=>mdout1_2_33, + D3=>mdout1_3_33, SD1=>rptr_11_ff, SD2=>rptr_12_ff, + Z=>ffidata_33); + + mux_1: MUX41 + port map (D0=>mdout1_0_34, D1=>mdout1_1_34, D2=>mdout1_2_34, + D3=>mdout1_3_34, SD1=>rptr_11_ff, SD2=>rptr_12_ff, + Z=>ffidata_34); + + mux_0: MUX41 + port map (D0=>mdout1_0_35, D1=>mdout1_1_35, D2=>mdout1_2_35, + D3=>mdout1_3_35, SD1=>rptr_11_ff, SD2=>rptr_12_ff, + Z=>ffidata_35); + + rcnt_0: FSUB2B + port map (A0=>r_nw_inv, A1=>wcount_0, B0=>r_nw_inv_inv, + B1=>rcount_0, BI=>scuba_vlo, BOUT=>co0_5, S0=>open, + S1=>rcnt_sub_0); + + rcnt_1: FSUB2B + port map (A0=>wcount_1, A1=>wcount_2, B0=>rcount_1, B1=>rcount_2, + BI=>co0_5, BOUT=>co1_5, S0=>rcnt_sub_1, S1=>rcnt_sub_2); + + rcnt_2: FSUB2B + port map (A0=>wcount_3, A1=>wcount_4, B0=>rcount_3, B1=>rcount_4, + BI=>co1_5, BOUT=>co2_5, S0=>rcnt_sub_3, S1=>rcnt_sub_4); + + rcnt_3: FSUB2B + port map (A0=>wcount_5, A1=>wcount_6, B0=>rcount_5, B1=>rcount_6, + BI=>co2_5, BOUT=>co3_5, S0=>rcnt_sub_5, S1=>rcnt_sub_6); + + rcnt_4: FSUB2B + port map (A0=>wcount_7, A1=>wcount_8, B0=>rcount_7, B1=>rcount_8, + BI=>co3_5, BOUT=>co4_5, S0=>rcnt_sub_7, S1=>rcnt_sub_8); + + rcnt_5: FSUB2B + port map (A0=>wcount_9, A1=>wcount_10, B0=>rcount_9, + B1=>rcount_10, BI=>co4_5, BOUT=>co5_5, S0=>rcnt_sub_9, + S1=>rcnt_sub_10); + + rcnt_6: FSUB2B + port map (A0=>wcount_11, A1=>wcount_12, B0=>rcount_11, + B1=>rcount_12, BI=>co5_5, BOUT=>co6_3, S0=>rcnt_sub_11, + S1=>rcnt_sub_12); + + rcnt_7: FSUB2B + port map (A0=>rcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, BI=>co6_3, BOUT=>open, S0=>rcnt_sub_13, + S1=>open); + + ae_set_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open); + + ae_set_cmp_0: AGEB2 + port map (A0=>AmEmptySetThresh(0), A1=>AmEmptySetThresh(1), + B0=>rcnt_reg_0, B1=>rcnt_reg_1, CI=>cmp_ci_2, GE=>co0_6); + + ae_set_cmp_1: AGEB2 + port map (A0=>AmEmptySetThresh(2), A1=>AmEmptySetThresh(3), + B0=>rcnt_reg_2, B1=>rcnt_reg_3, CI=>co0_6, GE=>co1_6); + + ae_set_cmp_2: AGEB2 + port map (A0=>AmEmptySetThresh(4), A1=>AmEmptySetThresh(5), + B0=>rcnt_reg_4, B1=>rcnt_reg_5, CI=>co1_6, GE=>co2_6); + + ae_set_cmp_3: AGEB2 + port map (A0=>AmEmptySetThresh(6), A1=>AmEmptySetThresh(7), + B0=>rcnt_reg_6, B1=>rcnt_reg_7, CI=>co2_6, GE=>co3_6); + + ae_set_cmp_4: AGEB2 + port map (A0=>AmEmptySetThresh(8), A1=>AmEmptySetThresh(9), + B0=>rcnt_reg_8, B1=>rcnt_reg_9, CI=>co3_6, GE=>co4_6); + + ae_set_cmp_5: AGEB2 + port map (A0=>AmEmptySetThresh(10), A1=>AmEmptySetThresh(11), + B0=>rcnt_reg_10, B1=>rcnt_reg_11, CI=>co4_6, GE=>co5_6); + + ae_set_cmp_6: AGEB2 + port map (A0=>AmEmptySetThresh(12), A1=>ae_set_setsig, + B0=>rcnt_reg_12, B1=>ae_set_clrsig, CI=>co5_6, + GE=>ae_set_d_c); + + a2: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>ae_set_d_c, COUT=>open, S0=>ae_set_d, + S1=>open); + + ae_clr_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci_3, S0=>open, S1=>open); + + ae_clr_cmp_0: AGEB2 + port map (A0=>AmEmptyClrThresh(0), A1=>AmEmptyClrThresh(1), + B0=>rcnt_reg_0, B1=>rcnt_reg_1, CI=>cmp_ci_3, GE=>co0_7); + + ae_clr_cmp_1: AGEB2 + port map (A0=>AmEmptyClrThresh(2), A1=>AmEmptyClrThresh(3), + B0=>rcnt_reg_2, B1=>rcnt_reg_3, CI=>co0_7, GE=>co1_7); + + ae_clr_cmp_2: AGEB2 + port map (A0=>AmEmptyClrThresh(4), A1=>AmEmptyClrThresh(5), + B0=>rcnt_reg_4, B1=>rcnt_reg_5, CI=>co1_7, GE=>co2_7); + + ae_clr_cmp_3: AGEB2 + port map (A0=>AmEmptyClrThresh(6), A1=>AmEmptyClrThresh(7), + B0=>rcnt_reg_6, B1=>rcnt_reg_7, CI=>co2_7, GE=>co3_7); + + ae_clr_cmp_4: AGEB2 + port map (A0=>AmEmptyClrThresh(8), A1=>AmEmptyClrThresh(9), + B0=>rcnt_reg_8, B1=>rcnt_reg_9, CI=>co3_7, GE=>co4_7); + + ae_clr_cmp_5: AGEB2 + port map (A0=>AmEmptyClrThresh(10), A1=>AmEmptyClrThresh(11), + B0=>rcnt_reg_10, B1=>rcnt_reg_11, CI=>co4_7, GE=>co5_7); + + ae_clr_cmp_6: AGEB2 + port map (A0=>AmEmptyClrThresh(12), A1=>ae_clr_setsig, + B0=>rcnt_reg_12, B1=>ae_clr_clrsig, CI=>co5_7, + GE=>ae_clr_d_c); + + a3: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>ae_clr_d_c, COUT=>open, S0=>ae_clr_d, + S1=>open); + + af_cmp_ci_a: FADD2B + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_4, S0=>open, + S1=>open); + + af_cmp_0: AGEB2 + port map (A0=>fcount_3, A1=>fcount_4, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>cmp_ci_4, GE=>co0_8); + + af_cmp_1: AGEB2 + port map (A0=>fcount_5, A1=>fcount_6, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>co0_8, GE=>co1_8); + + af_cmp_2: AGEB2 + port map (A0=>fcount_7, A1=>fcount_8, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>co1_8, GE=>co2_8); + + af_cmp_3: AGEB2 + port map (A0=>fcount_9, A1=>fcount_10, B0=>scuba_vhi, + B1=>scuba_vlo, CI=>co2_8, GE=>co3_8); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + af_cmp_4: AGEB2 + port map (A0=>fcount_11, A1=>fcount_12, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>co3_8, GE=>co4_8); + + af_cmp_5: AGEB2 + port map (A0=>fcount_13, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co4_8, GE=>af_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a4: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>af_d_c, COUT=>open, S0=>af_d, S1=>open); + + WCNT(0) <= fcount_0; + WCNT(1) <= fcount_1; + WCNT(2) <= fcount_2; + WCNT(3) <= fcount_3; + WCNT(4) <= fcount_4; + WCNT(5) <= fcount_5; + WCNT(6) <= fcount_6; + WCNT(7) <= fcount_7; + WCNT(8) <= fcount_8; + WCNT(9) <= fcount_9; + WCNT(10) <= fcount_10; + WCNT(11) <= fcount_11; + WCNT(12) <= fcount_12; + WCNT(13) <= fcount_13; + Empty <= empty_i; + Full <= full_i; + AlmostEmpty <= ae; +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of fifo_8192depth_36width_dual_thresh_reg_out is + for Structure + for all:AGEB2 use entity ecp2m.AGEB2(V); end for; + for all:ALEB2 use entity ecp2m.ALEB2(V); end for; + for all:AND2 use entity ecp2m.AND2(V); end for; + for all:CU2 use entity ecp2m.CU2(V); end for; + for all:CB2 use entity ecp2m.CB2(V); end for; + for all:FADD2B use entity ecp2m.FADD2B(V); end for; + for all:FSUB2B use entity ecp2m.FSUB2B(V); end for; + for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for; + for all:INV use entity ecp2m.INV(V); end for; + for all:MUX41 use entity ecp2m.MUX41(V); end for; + for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for; + for all:VHI use entity ecp2m.VHI(V); end for; + for all:VLO use entity ecp2m.VLO(V); end for; + for all:XOR2 use entity ecp2m.XOR2(V); end for; + for all:DP16KB use entity ecp2m.DP16KB(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on -- 2.43.0