From b61a6af856ea7db5fae8700676903fabc03f91ab Mon Sep 17 00:00:00 2001 From: Ludwig Maier Date: Mon, 30 Sep 2013 01:03:03 +0200 Subject: [PATCH] added nx_data_delay --- base/trb3_periph_nxyter.lpf | 4 +- nxyter/cores/fifo_44_data_delay.ipx | 9 + nxyter/cores/fifo_44_data_delay.lpc | 45 + nxyter/cores/fifo_44_data_delay.vhd | 1131 ++++++++++++++++ nxyter/cores/fifo_ts_32to32_dc.ipx | 10 +- nxyter/cores/fifo_ts_32to32_dc.lpc | 14 +- nxyter/cores/fifo_ts_32to32_dc.vhd | 603 ++------- nxyter/source/adc_spi_master.vhd | 902 ++++++------- nxyter/source/adc_spi_readbyte.vhd | 344 ++--- nxyter/source/adc_spi_sendbyte.vhd | 322 ++--- nxyter/source/debug_multiplexer.vhd | 222 ++-- nxyter/source/nx_data_delay.vhd | 226 ++++ nxyter/source/nx_data_receiver.vhd | 1662 ++++++++++++------------ nxyter/source/nx_data_validate.vhd | 780 +++++------ nxyter/source/nx_fpga_timestamp.vhd | 35 +- nxyter/source/nx_histograms.vhd | 10 +- nxyter/source/nx_i2c_master.vhd | 1116 ++++++++-------- nxyter/source/nx_i2c_readbyte.vhd | 482 +++---- nxyter/source/nx_i2c_sendbyte.vhd | 570 ++++---- nxyter/source/nx_i2c_startstop.vhd | 376 +++--- nxyter/source/nx_setup.vhd | 1316 ++++++++++--------- nxyter/source/nx_timer.vhd | 158 +-- nxyter/source/nx_timestamp_sim.vhd | 202 +-- nxyter/source/nx_trigger_generator.vhd | 623 +++++---- nxyter/source/nx_trigger_handler.vhd | 785 +++++------ nxyter/source/nx_trigger_validate.vhd | 26 +- nxyter/source/nxyter_components.vhd | 52 +- nxyter/source/nxyter_fee_board.vhd | 107 +- nxyter/source/nxyter_registers.vhd | 448 +++---- nxyter/source/registers.txt | 90 +- nxyter/trb3_periph.prj | 2 + nxyter/trb3_periph.vhd | 33 +- 32 files changed, 7058 insertions(+), 5647 deletions(-) create mode 100644 nxyter/cores/fifo_44_data_delay.ipx create mode 100644 nxyter/cores/fifo_44_data_delay.lpc create mode 100644 nxyter/cores/fifo_44_data_delay.vhd create mode 100644 nxyter/source/nx_data_delay.vhd diff --git a/base/trb3_periph_nxyter.lpf b/base/trb3_periph_nxyter.lpf index beb1c3a..1d81839 100644 --- a/base/trb3_periph_nxyter.lpf +++ b/base/trb3_periph_nxyter.lpf @@ -98,7 +98,7 @@ LOCATE COMP "NX1_TESTPULSE_OUT" SITE "T7"; #DQLL1_8 #46 LOCATE COMP "NX1_CLK256A_OUT" SITE "AB1"; #DQLL2_2 #29 LOCATE COMP "NX1_RESET_OUT" SITE "V6"; #DQLL2_8 #45 #LOCATE COMP "NX1_CLK128_IN" SITE "M3"; #DQUL3_8_OUTOFLANE_FPGA__3 #69 -LOCATE COMP "NX1_CLK128_IN" SITE "K4"; #DQSUL2_T #62 see DQUL3_8_OUTOFLANE +LOCATE COMP "NX1_CLK128_IN" SITE "K4"; #DQSUL2_T #62 see DQUL3_8_OUTOFLANE LOCATE COMP "NX1_I2C_SM_RESET_OUT" SITE "P4"; #DQLL1_4 #34 LOCATE COMP "NX1_I2C_REG_RESET_OUT" SITE "R3"; #DQLL1_5 #36 @@ -172,6 +172,7 @@ LOCATE COMP "NX2_CLK256A_OUT" SITE "AA26"; #DQLR1_4 #177 LOCATE COMP "NX2_TESTPULSE_OUT" SITE "AA24"; #DQLR1_6 #185 LOCATE COMP "NX2_CLK128_IN" SITE "M23"; #DQSUR1_T #118 #LOCATE COMP "NX2_CLK128_IN" SITE "N23"; #DQUR2_2 #134 +LOCATE COMP "ADDON_TRIGGER_OUT" SITE "N23"; #DQUR2_2 #134 LOCATE COMP "NX2_I2C_SCL_INOUT" SITE "R25"; #DQLR2_0 #170 LOCATE COMP "NX2_I2C_SDA_INOUT" SITE "R26"; #DQLR2_1 #172 @@ -221,6 +222,7 @@ IOBUF PORT "NX2_ADC_B_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100; IOBUF PORT "NX2_ADC_FCLK_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100; IOBUF PORT "NX2_ADC_SAMPLE_CLK_OUT" IO_TYPE=LVDS25; +IOBUF PORT "ADDON_TRIGGER_OUT" IO_TYPE=LVDS25; IOBUF PORT "NX2_CLK128_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100; IOBUF PORT "NX2_TESTPULSE_OUT" IO_TYPE=LVDS25; IOBUF PORT "NX2_CLK256A_OUT" IO_TYPE=LVDS25; diff --git a/nxyter/cores/fifo_44_data_delay.ipx b/nxyter/cores/fifo_44_data_delay.ipx new file mode 100644 index 0000000..71fca1c --- /dev/null +++ b/nxyter/cores/fifo_44_data_delay.ipx @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/nxyter/cores/fifo_44_data_delay.lpc b/nxyter/cores/fifo_44_data_delay.lpc new file mode 100644 index 0000000..6549a89 --- /dev/null +++ b/nxyter/cores/fifo_44_data_delay.lpc @@ -0,0 +1,45 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN672C +SpeedGrade=8 +Package=FPBGA672 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO +CoreRevision=4.8 +ModuleName=fifo_44_data_delay +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=09/29/2013 +Time=20:18:14 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=128 +Width=44 +regout=1 +CtrlByRdEn=1 +EmpFlg=1 +PeMode=Dynamic - Single Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=0 +PfMode=Static - Dual Threshold +PfAssert=508 +PfDeassert=506 +RDataCount=0 +EnECC=0 +EnFWFT=0 diff --git a/nxyter/cores/fifo_44_data_delay.vhd b/nxyter/cores/fifo_44_data_delay.vhd new file mode 100644 index 0000000..9acc944 --- /dev/null +++ b/nxyter/cores/fifo_44_data_delay.vhd @@ -0,0 +1,1131 @@ +-- VHDL netlist generated by SCUBA Diamond_2.1_Production (100) +-- Module Version: 4.8 +--/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 128 -width 44 -depth 128 -regout -pe 0 -pf -1 -e + +-- Sun Sep 29 20:18:15 2013 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity fifo_44_data_delay is + port ( + Data: in std_logic_vector(43 downto 0); + Clock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + AmEmptyThresh: in std_logic_vector(6 downto 0); + Q: out std_logic_vector(43 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostEmpty: out std_logic); +end fifo_44_data_delay; + +architecture Structure of fifo_44_data_delay is + + -- internal signal declarations + signal invout_2: std_logic; + signal invout_1: std_logic; + signal rden_i_inv: std_logic; + signal invout_0: std_logic; + signal r_nw: std_logic; + signal rcnt_reg_6_inv: std_logic; + signal fcnt_en: std_logic; + signal empty_i: std_logic; + signal empty_d: std_logic; + signal full_i: std_logic; + signal full_d: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wptr_5: std_logic; + signal wptr_6: std_logic; + signal wptr_7: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal rptr_5: std_logic; + signal rptr_6: std_logic; + signal rptr_7: std_logic; + signal ffidata_0: std_logic; + signal ffidata_1: std_logic; + signal ffidata_2: std_logic; + signal ffidata_3: std_logic; + signal ffidata_4: std_logic; + signal ffidata_5: std_logic; + signal ffidata_6: std_logic; + signal ffidata_7: std_logic; + signal ffidata_8: std_logic; + signal ffidata_9: std_logic; + signal ffidata_10: std_logic; + signal ffidata_11: std_logic; + signal ffidata_12: std_logic; + signal ffidata_13: std_logic; + signal ffidata_14: std_logic; + signal ffidata_15: std_logic; + signal ffidata_16: std_logic; + signal ffidata_17: std_logic; + signal ffidata_18: std_logic; + signal ffidata_19: std_logic; + signal ffidata_20: std_logic; + signal ffidata_21: std_logic; + signal ffidata_22: std_logic; + signal ffidata_23: std_logic; + signal ffidata_24: std_logic; + signal ffidata_25: std_logic; + signal ffidata_26: std_logic; + signal ffidata_27: std_logic; + signal ffidata_28: std_logic; + signal ffidata_29: std_logic; + signal ffidata_30: std_logic; + signal ffidata_31: std_logic; + signal ffidata_32: std_logic; + signal ffidata_33: std_logic; + signal ffidata_34: std_logic; + signal ffidata_35: std_logic; + signal ffidata_36: std_logic; + signal ffidata_37: std_logic; + signal ffidata_38: std_logic; + signal ffidata_39: std_logic; + signal ffidata_40: std_logic; + signal ffidata_41: std_logic; + signal ffidata_42: std_logic; + signal ffidata_43: std_logic; + signal rcnt_reg_7: std_logic; + signal ifcount_0: std_logic; + signal ifcount_1: std_logic; + signal bdcnt_bctr_ci: std_logic; + signal ifcount_2: std_logic; + signal ifcount_3: std_logic; + signal co0: std_logic; + signal ifcount_4: std_logic; + signal ifcount_5: std_logic; + signal co1: std_logic; + signal ifcount_6: std_logic; + signal ifcount_7: std_logic; + signal co3: std_logic; + signal cnt_con: std_logic; + signal co2: std_logic; + signal cmp_ci: std_logic; + signal co0_1: std_logic; + signal co1_1: std_logic; + signal co2_1: std_logic; + signal cmp_le_1: std_logic; + signal cmp_le_1_c: std_logic; + signal cmp_ci_1: std_logic; + signal fcount_0: std_logic; + signal fcount_1: std_logic; + signal co0_2: std_logic; + signal fcount_2: std_logic; + signal fcount_3: std_logic; + signal co1_2: std_logic; + signal fcount_4: std_logic; + signal fcount_5: std_logic; + signal co2_2: std_logic; + signal wren_i: std_logic; + signal wren_i_inv: std_logic; + signal fcount_6: std_logic; + signal fcount_7: std_logic; + signal cmp_ge_d1: std_logic; + signal cmp_ge_d1_c: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_ctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0_3: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1_3: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co3_1: std_logic; + signal wcount_7: std_logic; + signal co2_3: std_logic; + signal scuba_vhi: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_ctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_4: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_4: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co3_2: std_logic; + signal rcount_7: std_logic; + signal co2_4: std_logic; + signal rcnt_sub_0: std_logic; + signal r_nw_inv_inv: std_logic; + signal rcount_0: std_logic; + signal r_nw_inv: std_logic; + signal wcount_0: std_logic; + signal rcnt_sub_1: std_logic; + signal rcnt_sub_2: std_logic; + signal co0_5: std_logic; + signal rcount_1: std_logic; + signal rcount_2: std_logic; + signal wcount_1: std_logic; + signal wcount_2: std_logic; + signal rcnt_sub_3: std_logic; + signal rcnt_sub_4: std_logic; + signal co1_5: std_logic; + signal rcount_3: std_logic; + signal rcount_4: std_logic; + signal wcount_3: std_logic; + signal wcount_4: std_logic; + signal rcnt_sub_5: std_logic; + signal rcnt_sub_6: std_logic; + signal co2_5: std_logic; + signal rcount_5: std_logic; + signal rcount_6: std_logic; + signal wcount_5: std_logic; + signal wcount_6: std_logic; + signal rcnt_sub_7: std_logic; + signal co3_3: std_logic; + signal rcnt_sub_msb: std_logic; + signal rden_i: std_logic; + signal cmp_ci_2: std_logic; + signal rcnt_reg_0: std_logic; + signal rcnt_reg_1: std_logic; + signal co0_6: std_logic; + signal rcnt_reg_2: std_logic; + signal rcnt_reg_3: std_logic; + signal co1_6: std_logic; + signal rcnt_reg_4: std_logic; + signal rcnt_reg_5: std_logic; + signal co2_6: std_logic; + signal rcnt_reg_6: std_logic; + signal ae_set_clrsig: std_logic; + signal ae_set_setsig: std_logic; + signal ae_set_d: std_logic; + signal ae_set_d_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component ALEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; LE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component CB2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CON: in std_logic; CO: out std_logic; NC0: out std_logic; + NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FSUB2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; BI: in std_logic; BOUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component PDPW16KC + generic (GSR : in String; CSDECODE_R : in String; + CSDECODE_W : in String; REGMODE : in String; + DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer); + port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; + DI3: in std_logic; DI4: in std_logic; DI5: in std_logic; + DI6: in std_logic; DI7: in std_logic; DI8: in std_logic; + DI9: in std_logic; DI10: in std_logic; DI11: in std_logic; + DI12: in std_logic; DI13: in std_logic; + DI14: in std_logic; DI15: in std_logic; + DI16: in std_logic; DI17: in std_logic; + DI18: in std_logic; DI19: in std_logic; + DI20: in std_logic; DI21: in std_logic; + DI22: in std_logic; DI23: in std_logic; + DI24: in std_logic; DI25: in std_logic; + DI26: in std_logic; DI27: in std_logic; + DI28: in std_logic; DI29: in std_logic; + DI30: in std_logic; DI31: in std_logic; + DI32: in std_logic; DI33: in std_logic; + DI34: in std_logic; DI35: in std_logic; + ADW0: in std_logic; ADW1: in std_logic; + ADW2: in std_logic; ADW3: in std_logic; + ADW4: in std_logic; ADW5: in std_logic; + ADW6: in std_logic; ADW7: in std_logic; + ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic; + BE2: in std_logic; BE3: in std_logic; CEW: in std_logic; + CLKW: in std_logic; CSW0: in std_logic; + CSW1: in std_logic; CSW2: in std_logic; + ADR0: in std_logic; ADR1: in std_logic; + ADR2: in std_logic; ADR3: in std_logic; + ADR4: in std_logic; ADR5: in std_logic; + ADR6: in std_logic; ADR7: in std_logic; + ADR8: in std_logic; ADR9: in std_logic; + ADR10: in std_logic; ADR11: in std_logic; + ADR12: in std_logic; ADR13: in std_logic; + CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic; + CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic; + DO0: out std_logic; DO1: out std_logic; + DO2: out std_logic; DO3: out std_logic; + DO4: out std_logic; DO5: out std_logic; + DO6: out std_logic; DO7: out std_logic; + DO8: out std_logic; DO9: out std_logic; + DO10: out std_logic; DO11: out std_logic; + DO12: out std_logic; DO13: out std_logic; + DO14: out std_logic; DO15: out std_logic; + DO16: out std_logic; DO17: out std_logic; + DO18: out std_logic; DO19: out std_logic; + DO20: out std_logic; DO21: out std_logic; + DO22: out std_logic; DO23: out std_logic; + DO24: out std_logic; DO25: out std_logic; + DO26: out std_logic; DO27: out std_logic; + DO28: out std_logic; DO29: out std_logic; + DO30: out std_logic; DO31: out std_logic; + DO32: out std_logic; DO33: out std_logic; + DO34: out std_logic; DO35: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_44_data_delay.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is ""; + attribute RESETMODE of pdp_ram_0_0_1 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "fifo_44_data_delay.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is ""; + attribute RESETMODE of pdp_ram_0_1_0 : label is "SYNC"; + attribute GSR of FF_94 : label is "ENABLED"; + attribute GSR of FF_93 : label is "ENABLED"; + attribute GSR of FF_92 : label is "ENABLED"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t7: AND2 + port map (A=>WrEn, B=>invout_2, Z=>wren_i); + + INV_7: INV + port map (A=>full_i, Z=>invout_2); + + AND2_t6: AND2 + port map (A=>RdEn, B=>invout_1, Z=>rden_i); + + INV_6: INV + port map (A=>empty_i, Z=>invout_1); + + AND2_t5: AND2 + port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con); + + XOR2_t4: XOR2 + port map (A=>wren_i, B=>rden_i, Z=>fcnt_en); + + INV_5: INV + port map (A=>rden_i, Z=>rden_i_inv); + + INV_4: INV + port map (A=>wren_i, Z=>wren_i_inv); + + LUT4_1: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, + AD0=>empty_i, DO0=>empty_d); + + LUT4_0: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, + AD0=>full_i, DO0=>full_d); + + AND2_t3: AND2 + port map (A=>rden_i, B=>invout_0, Z=>r_nw); + + INV_3: INV + port map (A=>wren_i, Z=>invout_0); + + INV_2: INV + port map (A=>r_nw, Z=>r_nw_inv); + + XOR2_t2: XOR2 + port map (A=>wcount_7, B=>rcount_7, Z=>rcnt_sub_msb); + + INV_1: INV + port map (A=>r_nw_inv, Z=>r_nw_inv_inv); + + INV_0: INV + port map (A=>rcnt_reg_6, Z=>rcnt_reg_6_inv); + + AND2_t1: AND2 + port map (A=>rcnt_reg_7, B=>rcnt_reg_6_inv, Z=>ae_set_clrsig); + + AND2_t0: AND2 + port map (A=>rcnt_reg_7, B=>rcnt_reg_6, Z=>ae_set_setsig); + + pdp_ram_0_0_1: PDPW16KC + generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", + REGMODE=> "NOREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) + port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), + DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), + DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), + DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), + DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), + DI18=>Data(18), DI19=>Data(19), DI20=>Data(20), + DI21=>Data(21), DI22=>Data(22), DI23=>Data(23), + DI24=>Data(24), DI25=>Data(25), DI26=>Data(26), + DI27=>Data(27), DI28=>Data(28), DI29=>Data(29), + DI30=>Data(30), DI31=>Data(31), DI32=>Data(32), + DI33=>Data(33), DI34=>Data(34), DI35=>Data(35), ADW0=>wptr_0, + ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3, ADW4=>wptr_4, + ADW5=>wptr_5, ADW6=>wptr_6, ADW7=>scuba_vlo, ADW8=>scuba_vlo, + BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi, + BE3=>scuba_vhi, CEW=>wren_i, CLKW=>Clock, CSW0=>scuba_vhi, + CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo, + ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo, + ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2, + ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6, + ADR12=>scuba_vlo, ADR13=>scuba_vlo, CER=>rden_i, CLKR=>Clock, + CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo, + RST=>Reset, DO0=>ffidata_18, DO1=>ffidata_19, + DO2=>ffidata_20, DO3=>ffidata_21, DO4=>ffidata_22, + DO5=>ffidata_23, DO6=>ffidata_24, DO7=>ffidata_25, + DO8=>ffidata_26, DO9=>ffidata_27, DO10=>ffidata_28, + DO11=>ffidata_29, DO12=>ffidata_30, DO13=>ffidata_31, + DO14=>ffidata_32, DO15=>ffidata_33, DO16=>ffidata_34, + DO17=>ffidata_35, DO18=>ffidata_0, DO19=>ffidata_1, + DO20=>ffidata_2, DO21=>ffidata_3, DO22=>ffidata_4, + DO23=>ffidata_5, DO24=>ffidata_6, DO25=>ffidata_7, + DO26=>ffidata_8, DO27=>ffidata_9, DO28=>ffidata_10, + DO29=>ffidata_11, DO30=>ffidata_12, DO31=>ffidata_13, + DO32=>ffidata_14, DO33=>ffidata_15, DO34=>ffidata_16, + DO35=>ffidata_17); + + pdp_ram_0_1_0: PDPW16KC + generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", + REGMODE=> "NOREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) + port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38), + DI3=>Data(39), DI4=>Data(40), DI5=>Data(41), DI6=>Data(42), + DI7=>Data(43), DI8=>scuba_vlo, DI9=>scuba_vlo, + DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo, + DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo, + DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo, + DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo, + DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo, + DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo, + DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo, + DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo, + DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>wptr_0, ADW1=>wptr_1, + ADW2=>wptr_2, ADW3=>wptr_3, ADW4=>wptr_4, ADW5=>wptr_5, + ADW6=>wptr_6, ADW7=>scuba_vlo, ADW8=>scuba_vlo, + BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi, + BE3=>scuba_vhi, CEW=>wren_i, CLKW=>Clock, CSW0=>scuba_vhi, + CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo, + ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo, + ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2, + ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6, + ADR12=>scuba_vlo, ADR13=>scuba_vlo, CER=>rden_i, CLKR=>Clock, + CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo, + RST=>Reset, DO0=>open, DO1=>open, DO2=>open, DO3=>open, + DO4=>open, DO5=>open, DO6=>open, DO7=>open, DO8=>open, + DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open, + DO14=>open, DO15=>open, DO16=>open, DO17=>open, + DO18=>ffidata_36, DO19=>ffidata_37, DO20=>ffidata_38, + DO21=>ffidata_39, DO22=>ffidata_40, DO23=>ffidata_41, + DO24=>ffidata_42, DO25=>ffidata_43, DO26=>open, DO27=>open, + DO28=>open, DO29=>open, DO30=>open, DO31=>open, DO32=>open, + DO33=>open, DO34=>open, DO35=>open); + + FF_94: FD1P3DX + port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_0); + + FF_93: FD1P3DX + port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_1); + + FF_92: FD1P3DX + port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_2); + + FF_91: FD1P3DX + port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_3); + + FF_90: FD1P3DX + port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_4); + + FF_89: FD1P3DX + port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_5); + + FF_88: FD1P3DX + port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_6); + + FF_87: FD1P3DX + port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_7); + + FF_86: FD1S3BX + port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i); + + FF_85: FD1S3DX + port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i); + + FF_84: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset, + Q=>wcount_0); + + FF_83: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_1); + + FF_82: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_2); + + FF_81: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_3); + + FF_80: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_4); + + FF_79: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_5); + + FF_78: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_6); + + FF_77: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_7); + + FF_76: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset, + Q=>rcount_0); + + FF_75: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_1); + + FF_74: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_2); + + FF_73: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_3); + + FF_72: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_4); + + FF_71: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_5); + + FF_70: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_6); + + FF_69: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_7); + + FF_68: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_0); + + FF_67: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_1); + + FF_66: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_2); + + FF_65: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_3); + + FF_64: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_4); + + FF_63: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_5); + + FF_62: FD1P3DX + port map (D=>wcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_6); + + FF_61: FD1P3DX + port map (D=>wcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_7); + + FF_60: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_0); + + FF_59: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_1); + + FF_58: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_2); + + FF_57: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_3); + + FF_56: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_4); + + FF_55: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_5); + + FF_54: FD1P3DX + port map (D=>rcount_6, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_6); + + FF_53: FD1P3DX + port map (D=>rcount_7, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_7); + + FF_52: FD1P3DX + port map (D=>ffidata_0, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(0)); + + FF_51: FD1P3DX + port map (D=>ffidata_1, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(1)); + + FF_50: FD1P3DX + port map (D=>ffidata_2, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(2)); + + FF_49: FD1P3DX + port map (D=>ffidata_3, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(3)); + + FF_48: FD1P3DX + port map (D=>ffidata_4, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(4)); + + FF_47: FD1P3DX + port map (D=>ffidata_5, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(5)); + + FF_46: FD1P3DX + port map (D=>ffidata_6, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(6)); + + FF_45: FD1P3DX + port map (D=>ffidata_7, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(7)); + + FF_44: FD1P3DX + port map (D=>ffidata_8, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(8)); + + FF_43: FD1P3DX + port map (D=>ffidata_9, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(9)); + + FF_42: FD1P3DX + port map (D=>ffidata_10, SP=>RdEn, CK=>Clock, CD=>Reset, + Q=>Q(10)); + + FF_41: FD1P3DX + port map (D=>ffidata_11, SP=>RdEn, CK=>Clock, CD=>Reset, + Q=>Q(11)); + + FF_40: FD1P3DX + port map (D=>ffidata_12, SP=>RdEn, CK=>Clock, CD=>Reset, + Q=>Q(12)); + + FF_39: FD1P3DX + port map (D=>ffidata_13, SP=>RdEn, CK=>Clock, CD=>Reset, + Q=>Q(13)); + + FF_38: FD1P3DX + port map (D=>ffidata_14, SP=>RdEn, CK=>Clock, CD=>Reset, + Q=>Q(14)); + + FF_37: FD1P3DX + port map (D=>ffidata_15, SP=>RdEn, CK=>Clock, CD=>Reset, + Q=>Q(15)); + + FF_36: FD1P3DX + port map (D=>ffidata_16, SP=>RdEn, CK=>Clock, CD=>Reset, + Q=>Q(16)); + + FF_35: FD1P3DX + port map (D=>ffidata_17, SP=>RdEn, CK=>Clock, CD=>Reset, + Q=>Q(17)); + + FF_34: FD1P3DX + port map (D=>ffidata_18, SP=>RdEn, CK=>Clock, CD=>Reset, + Q=>Q(18)); + + FF_33: FD1P3DX + port map (D=>ffidata_19, SP=>RdEn, CK=>Clock, CD=>Reset, + Q=>Q(19)); + + FF_32: FD1P3DX + port map (D=>ffidata_20, SP=>RdEn, CK=>Clock, CD=>Reset, + Q=>Q(20)); + + FF_31: FD1P3DX + port map (D=>ffidata_21, SP=>RdEn, CK=>Clock, CD=>Reset, + Q=>Q(21)); + + FF_30: FD1P3DX + port map (D=>ffidata_22, SP=>RdEn, CK=>Clock, CD=>Reset, + Q=>Q(22)); + + FF_29: FD1P3DX + port map (D=>ffidata_23, SP=>RdEn, CK=>Clock, CD=>Reset, + Q=>Q(23)); + + FF_28: FD1P3DX + port map (D=>ffidata_24, SP=>RdEn, CK=>Clock, CD=>Reset, + Q=>Q(24)); + + FF_27: FD1P3DX + port map (D=>ffidata_25, SP=>RdEn, CK=>Clock, CD=>Reset, + Q=>Q(25)); + + FF_26: FD1P3DX + port map (D=>ffidata_26, SP=>RdEn, CK=>Clock, CD=>Reset, + Q=>Q(26)); + + FF_25: FD1P3DX + port map (D=>ffidata_27, SP=>RdEn, CK=>Clock, CD=>Reset, + Q=>Q(27)); + + FF_24: FD1P3DX + port map (D=>ffidata_28, SP=>RdEn, CK=>Clock, CD=>Reset, + Q=>Q(28)); + + FF_23: FD1P3DX + port map (D=>ffidata_29, SP=>RdEn, CK=>Clock, CD=>Reset, + Q=>Q(29)); + + FF_22: FD1P3DX + port map (D=>ffidata_30, SP=>RdEn, CK=>Clock, CD=>Reset, + Q=>Q(30)); + + FF_21: FD1P3DX + port map (D=>ffidata_31, SP=>RdEn, CK=>Clock, CD=>Reset, + Q=>Q(31)); + + FF_20: FD1P3DX + port map (D=>ffidata_32, SP=>RdEn, CK=>Clock, CD=>Reset, + Q=>Q(32)); + + FF_19: FD1P3DX + port map (D=>ffidata_33, SP=>RdEn, CK=>Clock, CD=>Reset, + Q=>Q(33)); + + FF_18: FD1P3DX + port map (D=>ffidata_34, SP=>RdEn, CK=>Clock, CD=>Reset, + Q=>Q(34)); + + FF_17: FD1P3DX + port map (D=>ffidata_35, SP=>RdEn, CK=>Clock, CD=>Reset, + Q=>Q(35)); + + FF_16: FD1P3DX + port map (D=>ffidata_36, SP=>RdEn, CK=>Clock, CD=>Reset, + Q=>Q(36)); + + FF_15: FD1P3DX + port map (D=>ffidata_37, SP=>RdEn, CK=>Clock, CD=>Reset, + Q=>Q(37)); + + FF_14: FD1P3DX + port map (D=>ffidata_38, SP=>RdEn, CK=>Clock, CD=>Reset, + Q=>Q(38)); + + FF_13: FD1P3DX + port map (D=>ffidata_39, SP=>RdEn, CK=>Clock, CD=>Reset, + Q=>Q(39)); + + FF_12: FD1P3DX + port map (D=>ffidata_40, SP=>RdEn, CK=>Clock, CD=>Reset, + Q=>Q(40)); + + FF_11: FD1P3DX + port map (D=>ffidata_41, SP=>RdEn, CK=>Clock, CD=>Reset, + Q=>Q(41)); + + FF_10: FD1P3DX + port map (D=>ffidata_42, SP=>RdEn, CK=>Clock, CD=>Reset, + Q=>Q(42)); + + FF_9: FD1P3DX + port map (D=>ffidata_43, SP=>RdEn, CK=>Clock, CD=>Reset, + Q=>Q(43)); + + FF_8: FD1S3DX + port map (D=>rcnt_sub_0, CK=>Clock, CD=>Reset, Q=>rcnt_reg_0); + + FF_7: FD1S3DX + port map (D=>rcnt_sub_1, CK=>Clock, CD=>Reset, Q=>rcnt_reg_1); + + FF_6: FD1S3DX + port map (D=>rcnt_sub_2, CK=>Clock, CD=>Reset, Q=>rcnt_reg_2); + + FF_5: FD1S3DX + port map (D=>rcnt_sub_3, CK=>Clock, CD=>Reset, Q=>rcnt_reg_3); + + FF_4: FD1S3DX + port map (D=>rcnt_sub_4, CK=>Clock, CD=>Reset, Q=>rcnt_reg_4); + + FF_3: FD1S3DX + port map (D=>rcnt_sub_5, CK=>Clock, CD=>Reset, Q=>rcnt_reg_5); + + FF_2: FD1S3DX + port map (D=>rcnt_sub_6, CK=>Clock, CD=>Reset, Q=>rcnt_reg_6); + + FF_1: FD1S3DX + port map (D=>rcnt_sub_7, CK=>Clock, CD=>Reset, Q=>rcnt_reg_7); + + FF_0: FD1S3BX + port map (D=>ae_set_d, CK=>Clock, PD=>Reset, Q=>AlmostEmpty); + + bdcnt_bctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, + CI=>scuba_vlo, COUT=>bdcnt_bctr_ci, S0=>open, S1=>open); + + bdcnt_bctr_0: CB2 + port map (CI=>bdcnt_bctr_ci, PC0=>fcount_0, PC1=>fcount_1, + CON=>cnt_con, CO=>co0, NC0=>ifcount_0, NC1=>ifcount_1); + + bdcnt_bctr_1: CB2 + port map (CI=>co0, PC0=>fcount_2, PC1=>fcount_3, CON=>cnt_con, + CO=>co1, NC0=>ifcount_2, NC1=>ifcount_3); + + bdcnt_bctr_2: CB2 + port map (CI=>co1, PC0=>fcount_4, PC1=>fcount_5, CON=>cnt_con, + CO=>co2, NC0=>ifcount_4, NC1=>ifcount_5); + + bdcnt_bctr_3: CB2 + port map (CI=>co2, PC0=>fcount_6, PC1=>fcount_7, CON=>cnt_con, + CO=>co3, NC0=>ifcount_6, NC1=>ifcount_7); + + e_cmp_ci_a: FADD2B + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, + S1=>open); + + e_cmp_0: ALEB2 + port map (A0=>fcount_0, A1=>fcount_1, B0=>rden_i, B1=>scuba_vlo, + CI=>cmp_ci, LE=>co0_1); + + e_cmp_1: ALEB2 + port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co0_1, LE=>co1_1); + + e_cmp_2: ALEB2 + port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co1_1, LE=>co2_1); + + e_cmp_3: ALEB2 + port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co2_1, LE=>cmp_le_1_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>cmp_le_1_c, COUT=>open, S0=>cmp_le_1, + S1=>open); + + g_cmp_ci_a: FADD2B + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, + S1=>open); + + g_cmp_0: AGEB2 + port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i, + CI=>cmp_ci_1, GE=>co0_2); + + g_cmp_1: AGEB2 + port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i, + CI=>co0_2, GE=>co1_2); + + g_cmp_2: AGEB2 + port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i, + CI=>co1_2, GE=>co2_2); + + g_cmp_3: AGEB2 + port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i_inv, + CI=>co2_2, GE=>cmp_ge_d1_c); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>cmp_ge_d1_c, COUT=>open, S0=>cmp_ge_d1, + S1=>open); + + w_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_ctr_ci, S0=>open, + S1=>open); + + w_ctr_0: CU2 + port map (CI=>w_ctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0_3, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_ctr_1: CU2 + port map (CI=>co0_3, PC0=>wcount_2, PC1=>wcount_3, CO=>co1_3, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_ctr_2: CU2 + port map (CI=>co1_3, PC0=>wcount_4, PC1=>wcount_5, CO=>co2_3, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_ctr_3: CU2 + port map (CI=>co2_3, PC0=>wcount_6, PC1=>wcount_7, CO=>co3_1, + NC0=>iwcount_6, NC1=>iwcount_7); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + r_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_ctr_ci, S0=>open, + S1=>open); + + r_ctr_0: CU2 + port map (CI=>r_ctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_4, + NC0=>ircount_0, NC1=>ircount_1); + + r_ctr_1: CU2 + port map (CI=>co0_4, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_4, + NC0=>ircount_2, NC1=>ircount_3); + + r_ctr_2: CU2 + port map (CI=>co1_4, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_4, + NC0=>ircount_4, NC1=>ircount_5); + + r_ctr_3: CU2 + port map (CI=>co2_4, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_2, + NC0=>ircount_6, NC1=>ircount_7); + + rcnt_0: FSUB2B + port map (A0=>r_nw_inv, A1=>wcount_0, B0=>r_nw_inv_inv, + B1=>rcount_0, BI=>scuba_vlo, BOUT=>co0_5, S0=>open, + S1=>rcnt_sub_0); + + rcnt_1: FSUB2B + port map (A0=>wcount_1, A1=>wcount_2, B0=>rcount_1, B1=>rcount_2, + BI=>co0_5, BOUT=>co1_5, S0=>rcnt_sub_1, S1=>rcnt_sub_2); + + rcnt_2: FSUB2B + port map (A0=>wcount_3, A1=>wcount_4, B0=>rcount_3, B1=>rcount_4, + BI=>co1_5, BOUT=>co2_5, S0=>rcnt_sub_3, S1=>rcnt_sub_4); + + rcnt_3: FSUB2B + port map (A0=>wcount_5, A1=>wcount_6, B0=>rcount_5, B1=>rcount_6, + BI=>co2_5, BOUT=>co3_3, S0=>rcnt_sub_5, S1=>rcnt_sub_6); + + rcnt_4: FSUB2B + port map (A0=>rcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, BI=>co3_3, BOUT=>open, S0=>rcnt_sub_7, + S1=>open); + + ae_set_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open); + + ae_set_cmp_0: AGEB2 + port map (A0=>AmEmptyThresh(0), A1=>AmEmptyThresh(1), + B0=>rcnt_reg_0, B1=>rcnt_reg_1, CI=>cmp_ci_2, GE=>co0_6); + + ae_set_cmp_1: AGEB2 + port map (A0=>AmEmptyThresh(2), A1=>AmEmptyThresh(3), + B0=>rcnt_reg_2, B1=>rcnt_reg_3, CI=>co0_6, GE=>co1_6); + + ae_set_cmp_2: AGEB2 + port map (A0=>AmEmptyThresh(4), A1=>AmEmptyThresh(5), + B0=>rcnt_reg_4, B1=>rcnt_reg_5, CI=>co1_6, GE=>co2_6); + + ae_set_cmp_3: AGEB2 + port map (A0=>AmEmptyThresh(6), A1=>ae_set_setsig, + B0=>rcnt_reg_6, B1=>ae_set_clrsig, CI=>co2_6, GE=>ae_set_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a2: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>ae_set_d_c, COUT=>open, S0=>ae_set_d, + S1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of fifo_44_data_delay is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:ALEB2 use entity ecp3.ALEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:CB2 use entity ecp3.CB2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FSUB2B use entity ecp3.FSUB2B(V); end for; + for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/nxyter/cores/fifo_ts_32to32_dc.ipx b/nxyter/cores/fifo_ts_32to32_dc.ipx index a05b4f1..e05a57e 100644 --- a/nxyter/cores/fifo_ts_32to32_dc.ipx +++ b/nxyter/cores/fifo_ts_32to32_dc.ipx @@ -1,9 +1,9 @@ - + - - - - + + + + diff --git a/nxyter/cores/fifo_ts_32to32_dc.lpc b/nxyter/cores/fifo_ts_32to32_dc.lpc index 996fcfb..8ac080e 100644 --- a/nxyter/cores/fifo_ts_32to32_dc.lpc +++ b/nxyter/cores/fifo_ts_32to32_dc.lpc @@ -16,8 +16,8 @@ CoreRevision=5.4 ModuleName=fifo_ts_32to32_dc SourceFormat=VHDL ParameterFileVersion=1.0 -Date=06/02/2013 -Time=03:59:31 +Date=08/16/2013 +Time=20:07:49 [Parameters] Verilog=0 @@ -28,15 +28,15 @@ Expression=BusA(0 to 7) Order=Big Endian [MSB:LSB] IO=0 FIFOImp=EBR Based -Depth=32 +Depth=4 Width=32 -RDepth=32 +RDepth=4 RWidth=32 regout=1 CtrlByRdEn=1 -EmpFlg=1 -PeMode=Dynamic - Single Threshold -PeAssert=10 +EmpFlg=0 +PeMode=Static - Single Threshold +PeAssert=2 PeDeassert=12 FullFlg=0 PfMode=Static - Dual Threshold diff --git a/nxyter/cores/fifo_ts_32to32_dc.vhd b/nxyter/cores/fifo_ts_32to32_dc.vhd index 8a4c217..54d37b1 100644 --- a/nxyter/cores/fifo_ts_32to32_dc.vhd +++ b/nxyter/cores/fifo_ts_32to32_dc.vhd @@ -1,8 +1,8 @@ -- VHDL netlist generated by SCUBA Diamond_2.1_Production (100) -- Module Version: 5.4 ---/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 32 -width 32 -depth 32 -rdata_width 32 -regout -pe 0 -pf -1 -e +--/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 4 -width 32 -depth 4 -rdata_width 32 -regout -pe -1 -pf -1 -e --- Sun Jun 2 03:59:31 2013 +-- Fri Aug 16 20:07:50 2013 library IEEE; use IEEE.std_logic_1164.all; @@ -20,11 +20,9 @@ entity fifo_ts_32to32_dc is RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; - AmEmptyThresh: in std_logic_vector(4 downto 0); Q: out std_logic_vector(31 downto 0); Empty: out std_logic; - Full: out std_logic; - AlmostEmpty: out std_logic); + Full: out std_logic); end fifo_ts_32to32_dc; architecture Structure of fifo_ts_32to32_dc is @@ -32,29 +30,16 @@ architecture Structure of fifo_ts_32to32_dc is -- internal signal declarations signal invout_1: std_logic; signal invout_0: std_logic; - signal rcnt_reg_4_inv: std_logic; signal w_gdata_0: std_logic; signal w_gdata_1: std_logic; - signal w_gdata_2: std_logic; - signal w_gdata_3: std_logic; - signal w_gdata_4: std_logic; signal wptr_0: std_logic; signal wptr_1: std_logic; signal wptr_2: std_logic; - signal wptr_3: std_logic; - signal wptr_4: std_logic; - signal wptr_5: std_logic; signal r_gdata_0: std_logic; signal r_gdata_1: std_logic; - signal r_gdata_2: std_logic; - signal r_gdata_3: std_logic; - signal r_gdata_4: std_logic; signal rptr_0: std_logic; signal rptr_1: std_logic; signal rptr_2: std_logic; - signal rptr_3: std_logic; - signal rptr_4: std_logic; - signal rptr_5: std_logic; signal ffidata_0: std_logic; signal ffidata_1: std_logic; signal ffidata_2: std_logic; @@ -90,90 +75,47 @@ architecture Structure of fifo_ts_32to32_dc is signal w_gcount_0: std_logic; signal w_gcount_1: std_logic; signal w_gcount_2: std_logic; - signal w_gcount_3: std_logic; - signal w_gcount_4: std_logic; - signal w_gcount_5: std_logic; signal r_gcount_0: std_logic; signal r_gcount_1: std_logic; signal r_gcount_2: std_logic; - signal r_gcount_3: std_logic; - signal r_gcount_4: std_logic; - signal r_gcount_5: std_logic; signal w_gcount_r20: std_logic; signal w_gcount_r0: std_logic; signal w_gcount_r21: std_logic; signal w_gcount_r1: std_logic; signal w_gcount_r22: std_logic; signal w_gcount_r2: std_logic; - signal w_gcount_r23: std_logic; - signal w_gcount_r3: std_logic; - signal w_gcount_r24: std_logic; - signal w_gcount_r4: std_logic; - signal w_gcount_r25: std_logic; - signal w_gcount_r5: std_logic; signal r_gcount_w20: std_logic; signal r_gcount_w0: std_logic; signal r_gcount_w21: std_logic; signal r_gcount_w1: std_logic; signal r_gcount_w22: std_logic; signal r_gcount_w2: std_logic; - signal r_gcount_w23: std_logic; - signal r_gcount_w3: std_logic; - signal r_gcount_w24: std_logic; - signal r_gcount_w4: std_logic; - signal r_gcount_w25: std_logic; - signal r_gcount_w5: std_logic; - signal rcnt_reg_5: std_logic; signal empty_i: std_logic; - signal full_i: std_logic; signal rRst: std_logic; + signal full_i: std_logic; signal iwcount_0: std_logic; signal iwcount_1: std_logic; signal w_gctr_ci: std_logic; signal iwcount_2: std_logic; - signal iwcount_3: std_logic; - signal co0: std_logic; - signal iwcount_4: std_logic; - signal iwcount_5: std_logic; - signal co2: std_logic; - signal wcount_5: std_logic; signal co1: std_logic; + signal wcount_2: std_logic; + signal co0: std_logic; + signal scuba_vhi: std_logic; signal ircount_0: std_logic; signal ircount_1: std_logic; signal r_gctr_ci: std_logic; signal ircount_2: std_logic; - signal ircount_3: std_logic; - signal co0_1: std_logic; - signal ircount_4: std_logic; - signal ircount_5: std_logic; - signal co2_1: std_logic; - signal rcount_5: std_logic; signal co1_1: std_logic; - signal rcnt_sub_0: std_logic; - signal scuba_vhi: std_logic; - signal rcnt_sub_1: std_logic; - signal rcnt_sub_2: std_logic; - signal co0_2: std_logic; - signal rcnt_sub_3: std_logic; - signal rcnt_sub_4: std_logic; - signal co1_2: std_logic; - signal rcnt_sub_5: std_logic; - signal co2_2: std_logic; - signal rcnt_sub_msb: std_logic; + signal rcount_2: std_logic; + signal co0_1: std_logic; + signal rden_i: std_logic; signal cmp_ci: std_logic; signal wcount_r0: std_logic; signal wcount_r1: std_logic; signal rcount_0: std_logic; signal rcount_1: std_logic; - signal co0_3: std_logic; - signal w_g2b_xor_cluster_0: std_logic; - signal wcount_r3: std_logic; - signal rcount_2: std_logic; - signal rcount_3: std_logic; - signal co1_3: std_logic; - signal wcount_r4: std_logic; + signal co0_2: std_logic; signal empty_cmp_clr: std_logic; - signal rcount_4: std_logic; signal empty_cmp_set: std_logic; signal empty_d: std_logic; signal empty_d_c: std_logic; @@ -183,31 +125,11 @@ architecture Structure of fifo_ts_32to32_dc is signal rcount_w1: std_logic; signal wcount_0: std_logic; signal wcount_1: std_logic; - signal co0_4: std_logic; - signal r_g2b_xor_cluster_0: std_logic; - signal rcount_w3: std_logic; - signal wcount_2: std_logic; - signal wcount_3: std_logic; - signal co1_4: std_logic; - signal rcount_w4: std_logic; + signal co0_3: std_logic; signal full_cmp_clr: std_logic; - signal wcount_4: std_logic; signal full_cmp_set: std_logic; signal full_d: std_logic; signal full_d_c: std_logic; - signal rden_i: std_logic; - signal cmp_ci_2: std_logic; - signal rcnt_reg_0: std_logic; - signal rcnt_reg_1: std_logic; - signal co0_5: std_logic; - signal rcnt_reg_2: std_logic; - signal rcnt_reg_3: std_logic; - signal co1_5: std_logic; - signal rcnt_reg_4: std_logic; - signal ae_clrsig: std_logic; - signal ae_setsig: std_logic; - signal ae_d: std_logic; - signal ae_d_c: std_logic; signal scuba_vlo: std_logic; -- local component declarations @@ -227,11 +149,6 @@ architecture Structure of fifo_ts_32to32_dc is B1: in std_logic; CI: in std_logic; COUT: out std_logic; S0: out std_logic; S1: out std_logic); end component; - component FSUB2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; BI: in std_logic; BOUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; component FD1P3BX port (D: in std_logic; SP: in std_logic; CK: in std_logic; PD: in std_logic; Q: out std_logic); @@ -331,43 +248,6 @@ architecture Structure of fifo_ts_32to32_dc is attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_ts_32to32_dc.lpc"; attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC"; - attribute GSR of FF_100 : label is "ENABLED"; - attribute GSR of FF_99 : label is "ENABLED"; - attribute GSR of FF_98 : label is "ENABLED"; - attribute GSR of FF_97 : label is "ENABLED"; - attribute GSR of FF_96 : label is "ENABLED"; - attribute GSR of FF_95 : label is "ENABLED"; - attribute GSR of FF_94 : label is "ENABLED"; - attribute GSR of FF_93 : label is "ENABLED"; - attribute GSR of FF_92 : label is "ENABLED"; - attribute GSR of FF_91 : label is "ENABLED"; - attribute GSR of FF_90 : label is "ENABLED"; - attribute GSR of FF_89 : label is "ENABLED"; - attribute GSR of FF_88 : label is "ENABLED"; - attribute GSR of FF_87 : label is "ENABLED"; - attribute GSR of FF_86 : label is "ENABLED"; - attribute GSR of FF_85 : label is "ENABLED"; - attribute GSR of FF_84 : label is "ENABLED"; - attribute GSR of FF_83 : label is "ENABLED"; - attribute GSR of FF_82 : label is "ENABLED"; - attribute GSR of FF_81 : label is "ENABLED"; - attribute GSR of FF_80 : label is "ENABLED"; - attribute GSR of FF_79 : label is "ENABLED"; - attribute GSR of FF_78 : label is "ENABLED"; - attribute GSR of FF_77 : label is "ENABLED"; - attribute GSR of FF_76 : label is "ENABLED"; - attribute GSR of FF_75 : label is "ENABLED"; - attribute GSR of FF_74 : label is "ENABLED"; - attribute GSR of FF_73 : label is "ENABLED"; - attribute GSR of FF_72 : label is "ENABLED"; - attribute GSR of FF_71 : label is "ENABLED"; - attribute GSR of FF_70 : label is "ENABLED"; - attribute GSR of FF_69 : label is "ENABLED"; - attribute GSR of FF_68 : label is "ENABLED"; - attribute GSR of FF_67 : label is "ENABLED"; - attribute GSR of FF_66 : label is "ENABLED"; - attribute GSR of FF_65 : label is "ENABLED"; - attribute GSR of FF_64 : label is "ENABLED"; attribute GSR of FF_63 : label is "ENABLED"; attribute GSR of FF_62 : label is "ENABLED"; attribute GSR of FF_61 : label is "ENABLED"; @@ -438,135 +318,73 @@ architecture Structure of fifo_ts_32to32_dc is begin -- component instantiation statements - AND2_t15: AND2 + AND2_t6: AND2 port map (A=>WrEn, B=>invout_1, Z=>wren_i); - INV_2: INV + INV_1: INV port map (A=>full_i, Z=>invout_1); - AND2_t14: AND2 + AND2_t5: AND2 port map (A=>RdEn, B=>invout_0, Z=>rden_i); - INV_1: INV + INV_0: INV port map (A=>empty_i, Z=>invout_0); - OR2_t13: OR2 + OR2_t4: OR2 port map (A=>Reset, B=>RPReset, Z=>rRst); - XOR2_t12: XOR2 + XOR2_t3: XOR2 port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - XOR2_t11: XOR2 + XOR2_t2: XOR2 port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - XOR2_t10: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t9: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - - XOR2_t8: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - - XOR2_t7: XOR2 + XOR2_t1: XOR2 port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - XOR2_t6: XOR2 + XOR2_t0: XOR2 port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - XOR2_t5: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - XOR2_t4: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - - XOR2_t3: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - - LUT4_13: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, - AD1=>w_gcount_r24, AD0=>w_gcount_r25, - DO0=>w_g2b_xor_cluster_0); - - LUT4_12: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r4); - - LUT4_11: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, - AD1=>w_gcount_r25, AD0=>scuba_vlo, DO0=>wcount_r3); - - LUT4_10: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, - AD1=>w_gcount_r23, AD0=>wcount_r4, DO0=>wcount_r1); - - LUT4_9: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, - AD1=>w_gcount_r22, AD0=>wcount_r3, DO0=>wcount_r0); - - LUT4_8: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, - AD1=>r_gcount_w24, AD0=>r_gcount_w25, - DO0=>r_g2b_xor_cluster_0); - LUT4_7: ROM16X1A generic map (initval=> X"6996") - port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w4); + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r1); LUT4_6: ROM16X1A generic map (initval=> X"6996") - port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, - AD1=>r_gcount_w25, AD0=>scuba_vlo, DO0=>rcount_w3); + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, + AD1=>w_gcount_r22, AD0=>scuba_vlo, DO0=>wcount_r0); LUT4_5: ROM16X1A generic map (initval=> X"6996") - port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, - AD1=>r_gcount_w23, AD0=>rcount_w4, DO0=>rcount_w1); + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w1); LUT4_4: ROM16X1A generic map (initval=> X"6996") port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, - AD1=>r_gcount_w22, AD0=>rcount_w3, DO0=>rcount_w0); - - XOR2_t2: XOR2 - port map (A=>w_gcount_r25, B=>rcount_5, Z=>rcnt_sub_msb); + AD1=>r_gcount_w22, AD0=>scuba_vlo, DO0=>rcount_w0); LUT4_3: ROM16X1A generic map (initval=> X"0410") - port map (AD3=>rptr_5, AD2=>rcount_5, AD1=>w_gcount_r25, + port map (AD3=>rptr_2, AD2=>rcount_2, AD1=>w_gcount_r22, AD0=>scuba_vlo, DO0=>empty_cmp_set); LUT4_2: ROM16X1A generic map (initval=> X"1004") - port map (AD3=>rptr_5, AD2=>rcount_5, AD1=>w_gcount_r25, + port map (AD3=>rptr_2, AD2=>rcount_2, AD1=>w_gcount_r22, AD0=>scuba_vlo, DO0=>empty_cmp_clr); LUT4_1: ROM16X1A generic map (initval=> X"0140") - port map (AD3=>wptr_5, AD2=>wcount_5, AD1=>r_gcount_w25, + port map (AD3=>wptr_2, AD2=>wcount_2, AD1=>r_gcount_w22, AD0=>scuba_vlo, DO0=>full_cmp_set); LUT4_0: ROM16X1A generic map (initval=> X"4001") - port map (AD3=>wptr_5, AD2=>wcount_5, AD1=>r_gcount_w25, + port map (AD3=>wptr_2, AD2=>wcount_2, AD1=>r_gcount_w22, AD0=>scuba_vlo, DO0=>full_cmp_clr); - INV_0: INV - port map (A=>rcnt_reg_4, Z=>rcnt_reg_4_inv); - - AND2_t1: AND2 - port map (A=>rcnt_reg_5, B=>rcnt_reg_4_inv, Z=>ae_clrsig); - - AND2_t0: AND2 - port map (A=>rcnt_reg_5, B=>rcnt_reg_4, Z=>ae_setsig); - pdp_ram_0_0_0: PDPW16KC generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", REGMODE=> "NOREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) @@ -581,15 +399,15 @@ begin DI27=>Data(27), DI28=>Data(28), DI29=>Data(29), DI30=>Data(30), DI31=>Data(31), DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo, - ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3, - ADW4=>wptr_4, ADW5=>scuba_vlo, ADW6=>scuba_vlo, + ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>scuba_vlo, ADW3=>scuba_vlo, + ADW4=>scuba_vlo, ADW5=>scuba_vlo, ADW6=>scuba_vlo, ADW7=>scuba_vlo, ADW8=>scuba_vlo, BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, CSW0=>scuba_vhi, CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo, ADR4=>scuba_vlo, - ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2, ADR8=>rptr_3, - ADR9=>rptr_4, ADR10=>scuba_vlo, ADR11=>scuba_vlo, + ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>scuba_vlo, ADR8=>scuba_vlo, + ADR9=>scuba_vlo, ADR10=>scuba_vlo, ADR11=>scuba_vlo, ADR12=>scuba_vlo, ADR13=>scuba_vlo, CER=>rden_i, CLKR=>RdClock, CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo, RST=>Reset, DO0=>ffidata_18, @@ -606,373 +424,241 @@ begin DO32=>ffidata_14, DO33=>ffidata_15, DO34=>ffidata_16, DO35=>ffidata_17); - FF_100: FD1P3BX + FF_63: FD1P3BX port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, Q=>wcount_0); - FF_99: FD1P3DX + FF_62: FD1P3DX port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_1); - FF_98: FD1P3DX + FF_61: FD1P3DX port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_2); - FF_97: FD1P3DX - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_96: FD1P3DX - port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_4); - - FF_95: FD1P3DX - port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_5); - - FF_94: FD1P3DX + FF_60: FD1P3DX port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_0); - FF_93: FD1P3DX + FF_59: FD1P3DX port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_1); - FF_92: FD1P3DX - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + FF_58: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_2); - FF_91: FD1P3DX - port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_90: FD1P3DX - port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_4); - - FF_89: FD1P3DX - port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_5); - - FF_88: FD1P3DX + FF_57: FD1P3DX port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_0); - FF_87: FD1P3DX + FF_56: FD1P3DX port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_1); - FF_86: FD1P3DX + FF_55: FD1P3DX port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_2); - FF_85: FD1P3DX - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_84: FD1P3DX - port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_4); - - FF_83: FD1P3DX - port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_5); - - FF_82: FD1P3BX + FF_54: FD1P3BX port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, Q=>rcount_0); - FF_81: FD1P3DX + FF_53: FD1P3DX port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_1); - FF_80: FD1P3DX + FF_52: FD1P3DX port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_2); - FF_79: FD1P3DX - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_78: FD1P3DX - port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_4); - - FF_77: FD1P3DX - port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_5); - - FF_76: FD1P3DX + FF_51: FD1P3DX port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_0); - FF_75: FD1P3DX + FF_50: FD1P3DX port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_1); - FF_74: FD1P3DX - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + FF_49: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_2); - FF_73: FD1P3DX - port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_72: FD1P3DX - port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_4); - - FF_71: FD1P3DX - port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_5); - - FF_70: FD1P3DX + FF_48: FD1P3DX port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_0); - FF_69: FD1P3DX + FF_47: FD1P3DX port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_1); - FF_68: FD1P3DX + FF_46: FD1P3DX port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_2); - FF_67: FD1P3DX - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_66: FD1P3DX - port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_4); - - FF_65: FD1P3DX - port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_5); - - FF_64: FD1P3DX + FF_45: FD1P3DX port map (D=>ffidata_0, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(0)); - FF_63: FD1P3DX + FF_44: FD1P3DX port map (D=>ffidata_1, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(1)); - FF_62: FD1P3DX + FF_43: FD1P3DX port map (D=>ffidata_2, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(2)); - FF_61: FD1P3DX + FF_42: FD1P3DX port map (D=>ffidata_3, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(3)); - FF_60: FD1P3DX + FF_41: FD1P3DX port map (D=>ffidata_4, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(4)); - FF_59: FD1P3DX + FF_40: FD1P3DX port map (D=>ffidata_5, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(5)); - FF_58: FD1P3DX + FF_39: FD1P3DX port map (D=>ffidata_6, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(6)); - FF_57: FD1P3DX + FF_38: FD1P3DX port map (D=>ffidata_7, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(7)); - FF_56: FD1P3DX + FF_37: FD1P3DX port map (D=>ffidata_8, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(8)); - FF_55: FD1P3DX + FF_36: FD1P3DX port map (D=>ffidata_9, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(9)); - FF_54: FD1P3DX + FF_35: FD1P3DX port map (D=>ffidata_10, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(10)); - FF_53: FD1P3DX + FF_34: FD1P3DX port map (D=>ffidata_11, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(11)); - FF_52: FD1P3DX + FF_33: FD1P3DX port map (D=>ffidata_12, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(12)); - FF_51: FD1P3DX + FF_32: FD1P3DX port map (D=>ffidata_13, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(13)); - FF_50: FD1P3DX + FF_31: FD1P3DX port map (D=>ffidata_14, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(14)); - FF_49: FD1P3DX + FF_30: FD1P3DX port map (D=>ffidata_15, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(15)); - FF_48: FD1P3DX + FF_29: FD1P3DX port map (D=>ffidata_16, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(16)); - FF_47: FD1P3DX + FF_28: FD1P3DX port map (D=>ffidata_17, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(17)); - FF_46: FD1P3DX + FF_27: FD1P3DX port map (D=>ffidata_18, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(18)); - FF_45: FD1P3DX + FF_26: FD1P3DX port map (D=>ffidata_19, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(19)); - FF_44: FD1P3DX + FF_25: FD1P3DX port map (D=>ffidata_20, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(20)); - FF_43: FD1P3DX + FF_24: FD1P3DX port map (D=>ffidata_21, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(21)); - FF_42: FD1P3DX + FF_23: FD1P3DX port map (D=>ffidata_22, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(22)); - FF_41: FD1P3DX + FF_22: FD1P3DX port map (D=>ffidata_23, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(23)); - FF_40: FD1P3DX + FF_21: FD1P3DX port map (D=>ffidata_24, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(24)); - FF_39: FD1P3DX + FF_20: FD1P3DX port map (D=>ffidata_25, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(25)); - FF_38: FD1P3DX + FF_19: FD1P3DX port map (D=>ffidata_26, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(26)); - FF_37: FD1P3DX + FF_18: FD1P3DX port map (D=>ffidata_27, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(27)); - FF_36: FD1P3DX + FF_17: FD1P3DX port map (D=>ffidata_28, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(28)); - FF_35: FD1P3DX + FF_16: FD1P3DX port map (D=>ffidata_29, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(29)); - FF_34: FD1P3DX + FF_15: FD1P3DX port map (D=>ffidata_30, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(30)); - FF_33: FD1P3DX + FF_14: FD1P3DX port map (D=>ffidata_31, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(31)); - FF_32: FD1S3DX + FF_13: FD1S3DX port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - FF_31: FD1S3DX + FF_12: FD1S3DX port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - FF_30: FD1S3DX + FF_11: FD1S3DX port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - FF_29: FD1S3DX - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_28: FD1S3DX - port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - - FF_27: FD1S3DX - port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - - FF_26: FD1S3DX + FF_10: FD1S3DX port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - FF_25: FD1S3DX + FF_9: FD1S3DX port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - FF_24: FD1S3DX + FF_8: FD1S3DX port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - FF_23: FD1S3DX - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_22: FD1S3DX - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - - FF_21: FD1S3DX - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - - FF_20: FD1S3DX + FF_7: FD1S3DX port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r20); - FF_19: FD1S3DX + FF_6: FD1S3DX port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r21); - FF_18: FD1S3DX + FF_5: FD1S3DX port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r22); - FF_17: FD1S3DX - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_16: FD1S3DX - port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r24); - - FF_15: FD1S3DX - port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r25); - - FF_14: FD1S3DX + FF_4: FD1S3DX port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - FF_13: FD1S3DX + FF_3: FD1S3DX port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - FF_12: FD1S3DX + FF_2: FD1S3DX port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - FF_11: FD1S3DX - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_10: FD1S3DX - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); - - FF_9: FD1S3DX - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - - FF_8: FD1S3DX - port map (D=>rcnt_sub_0, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_0); - - FF_7: FD1S3DX - port map (D=>rcnt_sub_1, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_1); - - FF_6: FD1S3DX - port map (D=>rcnt_sub_2, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_2); - - FF_5: FD1S3DX - port map (D=>rcnt_sub_3, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_3); - - FF_4: FD1S3DX - port map (D=>rcnt_sub_4, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_4); - - FF_3: FD1S3DX - port map (D=>rcnt_sub_5, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_5); - - FF_2: FD1S3BX + FF_1: FD1S3BX port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - FF_1: FD1S3DX + FF_0: FD1S3DX port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - FF_0: FD1S3BX - port map (D=>ae_d, CK=>RdClock, PD=>rRst, Q=>AlmostEmpty); - w_gctr_cia: FADD2B port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, @@ -983,12 +669,11 @@ begin NC0=>iwcount_0, NC1=>iwcount_1); w_gctr_1: CU2 - port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, - NC0=>iwcount_2, NC1=>iwcount_3); + port map (CI=>co0, PC0=>wcount_2, PC1=>scuba_vlo, CO=>co1, + NC0=>iwcount_2, NC1=>open); - w_gctr_2: CU2 - port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, - NC0=>iwcount_4, NC1=>iwcount_5); + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); r_gctr_cia: FADD2B port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, @@ -1000,35 +685,8 @@ begin NC0=>ircount_0, NC1=>ircount_1); r_gctr_1: CU2 - port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, - NC0=>ircount_2, NC1=>ircount_3); - - r_gctr_2: CU2 - port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, - NC0=>ircount_4, NC1=>ircount_5); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - rcnt_0: FSUB2B - port map (A0=>scuba_vhi, A1=>wcount_r0, B0=>scuba_vlo, - B1=>rcount_0, BI=>scuba_vlo, BOUT=>co0_2, S0=>open, - S1=>rcnt_sub_0); - - rcnt_1: FSUB2B - port map (A0=>wcount_r1, A1=>w_g2b_xor_cluster_0, B0=>rcount_1, - B1=>rcount_2, BI=>co0_2, BOUT=>co1_2, S0=>rcnt_sub_1, - S1=>rcnt_sub_2); - - rcnt_2: FSUB2B - port map (A0=>wcount_r3, A1=>wcount_r4, B0=>rcount_3, - B1=>rcount_4, BI=>co1_2, BOUT=>co2_2, S0=>rcnt_sub_3, - S1=>rcnt_sub_4); - - rcnt_3: FSUB2B - port map (A0=>rcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, BI=>co2_2, BOUT=>open, S0=>rcnt_sub_5, - S1=>open); + port map (CI=>co0_1, PC0=>rcount_2, PC1=>scuba_vlo, CO=>co1_1, + NC0=>ircount_2, NC1=>open); empty_cmp_ci_a: FADD2B port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, @@ -1036,15 +694,11 @@ begin empty_cmp_0: AGEB2 port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, - B1=>wcount_r1, CI=>cmp_ci, GE=>co0_3); + B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>w_g2b_xor_cluster_0, - B1=>wcount_r3, CI=>co0_3, GE=>co1_3); - - empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>empty_cmp_set, B0=>wcount_r4, - B1=>empty_cmp_clr, CI=>co1_3, GE=>empty_d_c); + port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, + B1=>scuba_vlo, CI=>co0_2, GE=>empty_d_c); a0: FADD2B port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, @@ -1057,44 +711,20 @@ begin full_cmp_0: AGEB2 port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, - B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_4); + B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>r_g2b_xor_cluster_0, - B1=>rcount_w3, CI=>co0_4, GE=>co1_4); + port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, + B1=>scuba_vlo, CI=>co0_3, GE=>full_d_c); - full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>full_cmp_set, B0=>rcount_w4, - B1=>full_cmp_clr, CI=>co1_4, GE=>full_d_c); + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); a1: FADD2B port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, S1=>open); - ae_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open); - - ae_cmp_0: AGEB2 - port map (A0=>AmEmptyThresh(0), A1=>AmEmptyThresh(1), - B0=>rcnt_reg_0, B1=>rcnt_reg_1, CI=>cmp_ci_2, GE=>co0_5); - - ae_cmp_1: AGEB2 - port map (A0=>AmEmptyThresh(2), A1=>AmEmptyThresh(3), - B0=>rcnt_reg_2, B1=>rcnt_reg_3, CI=>co0_5, GE=>co1_5); - - ae_cmp_2: AGEB2 - port map (A0=>AmEmptyThresh(4), A1=>ae_setsig, B0=>rcnt_reg_4, - B1=>ae_clrsig, CI=>co1_5, GE=>ae_d_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - a2: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>ae_d_c, COUT=>open, S0=>ae_d, S1=>open); - Empty <= empty_i; Full <= full_i; end Structure; @@ -1107,7 +737,6 @@ configuration Structure_CON of fifo_ts_32to32_dc is for all:AND2 use entity ecp3.AND2(V); end for; for all:CU2 use entity ecp3.CU2(V); end for; for all:FADD2B use entity ecp3.FADD2B(V); end for; - for all:FSUB2B use entity ecp3.FSUB2B(V); end for; for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; diff --git a/nxyter/source/adc_spi_master.vhd b/nxyter/source/adc_spi_master.vhd index 504b630..9b73513 100644 --- a/nxyter/source/adc_spi_master.vhd +++ b/nxyter/source/adc_spi_master.vhd @@ -1,451 +1,451 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.nxyter_components.all; - -entity adc_spi_master is - generic ( - SPI_SPEED : unsigned(7 downto 0) := x"32" - ); - port( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - - -- SPI connections - SCLK_OUT : out std_logic; - SDIO_INOUT : inout std_logic; - CSB_OUT : out std_logic; - - -- Internal Interface - INTERNAL_COMMAND_IN : in std_logic_vector(31 downto 0); - COMMAND_ACK_OUT : out std_logic; - SPI_DATA : out std_logic_vector(31 downto 0); - SPI_LOCK_IN : in std_logic; - - -- Slave bus - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_ACK_OUT : out std_logic; - SLV_NO_MORE_DATA_OUT : out std_logic; - SLV_UNKNOWN_ADDR_OUT : out std_logic; - - -- Debug Line - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); -end entity; - -architecture Behavioral of adc_spi_master is - - signal sdio_i : std_logic; - signal sdio_x : std_logic; - signal sdio : std_logic; - - signal sclk_o : std_logic; - signal command_ack_o : std_logic; - - -- SPI Master - signal csb_o : std_logic; - signal spi_start : std_logic; - - signal spi_busy : std_logic; - signal takeover_sdio : std_logic; - signal wait_timer_init : unsigned(7 downto 0); - signal sendbyte_seq_start : std_logic; - signal readbyte_seq_start : std_logic; - signal sendbyte_byte : std_logic_vector(7 downto 0); - signal read_seq_ctr : std_logic; - signal reg_data : std_logic_vector(31 downto 0); - - signal spi_busy_x : std_logic; - signal wait_timer_init_x : unsigned(7 downto 0); - signal sendbyte_seq_start_x : std_logic; - signal sendbyte_byte_x : std_logic_vector(7 downto 0); - signal readbyte_seq_start_x : std_logic; - signal read_seq_ctr_x : std_logic; - signal reg_data_x : std_logic_vector(31 downto 0); - - signal sdio_sendbyte : std_logic; - signal sclk_sendbyte : std_logic; - signal sendbyte_done : std_logic; - - signal sclk_readbyte : std_logic; - signal readbyte_byte : std_logic_vector(7 downto 0); - signal readbyte_done : std_logic; - - type STATES is (S_RESET, - S_IDLE, - S_START, - S_START_WAIT, - - S_SEND_CMD_A, - S_SEND_CMD_A_WAIT, - S_SEND_CMD_B, - S_SEND_CMD_B_WAIT, - - S_SEND_DATA, - S_SEND_DATA_WAIT, - S_GET_DATA, - S_GET_DATA_WAIT, - - S_STOP, - S_STOP_WAIT - ); - signal STATE, NEXT_STATE : STATES; - - -- SPI Timer - signal wait_timer_done : std_logic; - - -- TRBNet Slave Bus - signal slv_data_out_o : std_logic_vector(31 downto 0); - signal slv_no_more_data_o : std_logic; - signal slv_unknown_addr_o : std_logic; - signal slv_ack_o : std_logic; - signal spi_chipid : std_logic_vector(6 downto 0); - signal spi_rw_bit : std_logic; - signal spi_registerid : std_logic_vector(12 downto 0); - signal spi_register_data : std_logic_vector(7 downto 0); - signal spi_register_value_read : std_logic_vector(7 downto 0); - -begin - - -- Timer - nx_timer_1: nx_timer - generic map ( - CTR_WIDTH => 8 - ) - port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - TIMER_START_IN => wait_timer_init, - TIMER_DONE_OUT => wait_timer_done - ); - - adc_spi_sendbyte_1: adc_spi_sendbyte - generic map ( - SPI_SPEED => SPI_SPEED - ) - port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - START_IN => sendbyte_seq_start, - BYTE_IN => sendbyte_byte, - SEQUENCE_DONE_OUT => sendbyte_done, - SDIO_OUT => sdio_sendbyte, - SCLK_OUT => sclk_sendbyte - ); - - adc_spi_readbyte_1: adc_spi_readbyte - generic map ( - SPI_SPEED => SPI_SPEED - ) - port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - START_IN => readbyte_seq_start, - BYTE_OUT => readbyte_byte, - SEQUENCE_DONE_OUT => readbyte_done, - SDIO_IN => sdio, - SCLK_OUT => sclk_readbyte - ); - - -- Debug Line - - DEBUG_OUT(0) <= CLK_IN; - DEBUG_OUT(1) <= SCLK_OUT; - DEBUG_OUT(2) <= SDIO_INOUT; - DEBUG_OUT(3) <= CSB_OUT; - DEBUG_OUT(4) <= spi_busy; - DEBUG_OUT(5) <= wait_timer_done; - DEBUG_OUT(6) <= sendbyte_seq_start; - DEBUG_OUT(7) <= sendbyte_done; - DEBUG_OUT(8) <= sclk_sendbyte; - DEBUG_OUT(9) <= sdio_sendbyte; - DEBUG_OUT(10) <= sclk_readbyte; - DEBUG_OUT(11) <= takeover_sdio; - - -- Sync SPI SDIO Line - sdio_i <= SDIO_INOUT; - - PROC_I2C_LINES_SYNC: process(CLK_IN) - begin - if( rising_edge(CLK_IN) ) then - if( RESET_IN = '1' ) then - sdio_x <= '1'; - sdio <= '1'; - else - sdio_x <= sdio_i; - sdio <= sdio_x; - end if; - end if; - end process PROC_I2C_LINES_SYNC; - - PROC_I2C_MASTER_TRANSFER: process(CLK_IN) - begin - if( rising_edge(CLK_IN) ) then - if( RESET_IN = '1' ) then - spi_busy <= '1'; - sendbyte_seq_start <= '0'; - readbyte_seq_start <= '0'; - sendbyte_byte <= (others => '0'); - wait_timer_init <= (others => '0'); - reg_data <= (others => '0'); - read_seq_ctr <= '0'; - STATE <= S_RESET; - else - spi_busy <= spi_busy_x; - sendbyte_seq_start <= sendbyte_seq_start_x; - readbyte_seq_start <= readbyte_seq_start_x; - sendbyte_byte <= sendbyte_byte_x; - wait_timer_init <= wait_timer_init_x; - reg_data <= reg_data_x; - read_seq_ctr <= read_seq_ctr_x; - STATE <= NEXT_STATE; - end if; - end if; - end process PROC_I2C_MASTER_TRANSFER; - - - PROC_I2C_MASTER: process(STATE, - spi_start, - wait_timer_done, - sendbyte_done, - readbyte_done - ) - - begin - -- Defaults - takeover_sdio <= '0'; - sclk_o <= '0'; - csb_o <= '0'; - spi_busy_x <= '1'; - sendbyte_seq_start_x <= '0'; - sendbyte_byte_x <= (others => '0'); - readbyte_seq_start_x <= '0'; - wait_timer_init_x <= (others => '0'); - reg_data_x <= reg_data; - read_seq_ctr_x <= read_seq_ctr; - - case STATE is - - when S_RESET => - reg_data_x <= (others => '0'); - NEXT_STATE <= S_IDLE; - - when S_IDLE => - csb_o <= '1'; - if (spi_start = '1') then - reg_data_x <= x"8000_0000"; -- Set Running , clear all other bits - NEXT_STATE <= S_START; - else - spi_busy_x <= '0'; - reg_data_x <= reg_data and x"7fff_ffff"; -- clear running bit; - read_seq_ctr_x <= '0'; - NEXT_STATE <= S_IDLE; - end if; - - -- SPI START Sequence - when S_START => - wait_timer_init_x <= SPI_SPEED srl 2; - NEXT_STATE <= S_START_WAIT; - - when S_START_WAIT => - if (wait_timer_done = '0') then - NEXT_STATE <= S_START_WAIT; - else - takeover_sdio <= '1'; - NEXT_STATE <= S_SEND_CMD_A; - end if; - - -- I2C SEND CMD Part1 - when S_SEND_CMD_A => - takeover_sdio <= '1'; - sendbyte_byte_x(7) <= spi_rw_bit; - sendbyte_byte_x(6 downto 5) <= "00"; - sendbyte_byte_x(4 downto 0) <= spi_registerid(12 downto 8); - sendbyte_seq_start_x <= '1'; - NEXT_STATE <= S_SEND_CMD_A_WAIT; - - when S_SEND_CMD_A_WAIT => - takeover_sdio <= '1'; - if (sendbyte_done = '0') then - NEXT_STATE <= S_SEND_CMD_A_WAIT; - else - NEXT_STATE <= S_SEND_CMD_B; - end if; - - -- I2C SEND CMD Part1 - when S_SEND_CMD_B => - takeover_sdio <= '1'; - sendbyte_byte_x(7 downto 0) <= spi_registerid(7 downto 0); - sendbyte_seq_start_x <= '1'; - NEXT_STATE <= S_SEND_CMD_B_WAIT; - - when S_SEND_CMD_B_WAIT => - takeover_sdio <= '1'; - if (sendbyte_done = '0') then - NEXT_STATE <= S_SEND_CMD_B_WAIT; - else - if (spi_rw_bit = '1') then - NEXT_STATE <= S_GET_DATA; - else - NEXT_STATE <= S_SEND_DATA; - end if; - end if; - - -- I2C SEND DataWord - when S_SEND_DATA => - takeover_sdio <= '1'; - sendbyte_byte_x <= spi_register_data; - sendbyte_seq_start_x <= '1'; - NEXT_STATE <= S_SEND_DATA_WAIT; - - when S_SEND_DATA_WAIT => - takeover_sdio <= '1'; - if (sendbyte_done = '0') then - NEXT_STATE <= S_SEND_DATA_WAIT; - else - NEXT_STATE <= S_STOP; - end if; - - -- I2C GET DataWord - when S_GET_DATA => - readbyte_seq_start_x <= '1'; - NEXT_STATE <= S_GET_DATA_WAIT; - - when S_GET_DATA_WAIT => - if (readbyte_done = '0') then - NEXT_STATE <= S_GET_DATA_WAIT; - else - reg_data_x(7 downto 0) <= readbyte_byte; - NEXT_STATE <= S_STOP; - end if; - - -- SPI STOP Sequence - when S_STOP => - wait_timer_init_x <= SPI_SPEED srl 2; - NEXT_STATE <= S_STOP_WAIT; - - when S_STOP_WAIT => - if (wait_timer_done = '0') then - NEXT_STATE <= S_STOP_WAIT; - else - reg_data_x <= reg_data or x"4000_0000"; -- Set DONE Bit - NEXT_STATE <= S_IDLE; - end if; - - end case; - end process PROC_I2C_MASTER; - - ----------------------------------------------------------------------------- - -- TRBNet Slave Bus - ----------------------------------------------------------------------------- - -- - -- Write bit definition - -- ==================== - -- - -- D[31] SPI_GO 0 => don't do anything on SPI, - -- 1 => start SPI access - -- D[30] SPI_ACTION 0 => write byte, 1 => read byte - -- D[20:8] SPI_CMD SPI Register Id - -- D[7:0] SPI_DATA data to be written - -- - -- Read bit definition - -- =================== - -- - -- D[31] RUNNING whatever - -- D[30] SPI_DONE whatever - -- D[29:21] reserved reserved - -- D[20:16] debug subject to change, don't use - -- D[15:8] reserved reserved - -- D[7:0] SPI_DATA result of SPI read operation - -- - - PROC_SLAVE_BUS: process(CLK_IN) - begin - if( rising_edge(CLK_IN) ) then - if( RESET_IN = '1' ) then - slv_data_out_o <= (others => '0'); - slv_no_more_data_o <= '0'; - slv_unknown_addr_o <= '0'; - slv_ack_o <= '0'; - spi_start <= '0'; - command_ack_o <= '0'; - - spi_chipid <= (others => '0'); - spi_rw_bit <= '0'; - spi_registerid <= (others => '0'); - spi_register_data <= (others => '0'); - spi_register_value_read <= (others => '0'); - - else - slv_data_out_o <= (others => '0'); - slv_unknown_addr_o <= '0'; - slv_no_more_data_o <= '0'; - - spi_start <= '0'; - command_ack_o <= '0'; - - --if (spi_busy = '0' and INTERNAL_COMMAND_IN(31) = '1') then - -- spi_rw_bit <= INTERNAL_COMMAND_IN(30); - -- spi_registerid <= INTERNAL_COMMAND_IN(20 downto 8); - -- spi_register_data <= INTERNAL_COMMAND_IN(7 downto 0); - -- spi_start <= '1'; - -- command_ack_o <= '1'; - -- slv_ack_o <= '1'; - -- - --elsif (SLV_WRITE_IN = '1') then - if (SLV_WRITE_IN = '1') then - if (spi_busy = '0' and SLV_DATA_IN(31) = '1') then - spi_rw_bit <= SLV_DATA_IN(30); - spi_registerid <= SLV_DATA_IN(20 downto 8); - spi_register_data <= SLV_DATA_IN(7 downto 0); - spi_start <= '1'; - slv_ack_o <= '1'; - else - slv_ack_o <= '1'; - end if; - - elsif (SLV_READ_IN = '1') then - if (spi_busy = '1') then - slv_no_more_data_o <= '1'; - slv_ack_o <= '0'; - else - slv_data_out_o <= reg_data; - slv_ack_o <= '1'; - end if; - - else - slv_ack_o <= '0'; - end if; - - end if; - end if; - end process PROC_SLAVE_BUS; - - - ----------------------------------------------------------------------------- - -- Output Signals - ----------------------------------------------------------------------------- - - -- SPI Outputs - SDIO_INOUT <= sdio_sendbyte when (takeover_sdio = '1') - else 'Z'; - - SCLK_OUT <= sclk_o or - sclk_sendbyte or - sclk_readbyte; - - CSB_OUT <= csb_o; - COMMAND_ACK_OUT <= command_ack_o; - - -- Slave Bus - SLV_DATA_OUT <= slv_data_out_o; - SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; - SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o; - SLV_ACK_OUT <= slv_ack_o; - -end Behavioral; +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.nxyter_components.all; + +entity adc_spi_master is + generic ( + SPI_SPEED : unsigned(7 downto 0) := x"32" + ); + port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + + -- SPI connections + SCLK_OUT : out std_logic; + SDIO_INOUT : inout std_logic; + CSB_OUT : out std_logic; + + -- Internal Interface + INTERNAL_COMMAND_IN : in std_logic_vector(31 downto 0); + COMMAND_ACK_OUT : out std_logic; + SPI_DATA : out std_logic_vector(31 downto 0); + SPI_LOCK_IN : in std_logic; + + -- Slave bus + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic; + + -- Debug Line + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); +end entity; + +architecture Behavioral of adc_spi_master is + + signal sdio_i : std_logic; + signal sdio_x : std_logic; + signal sdio : std_logic; + + signal sclk_o : std_logic; + signal command_ack_o : std_logic; + + -- SPI Master + signal csb_o : std_logic; + signal spi_start : std_logic; + + signal spi_busy : std_logic; + signal takeover_sdio : std_logic; + signal wait_timer_init : unsigned(7 downto 0); + signal sendbyte_seq_start : std_logic; + signal readbyte_seq_start : std_logic; + signal sendbyte_byte : std_logic_vector(7 downto 0); + signal read_seq_ctr : std_logic; + signal reg_data : std_logic_vector(31 downto 0); + + signal spi_busy_x : std_logic; + signal wait_timer_init_x : unsigned(7 downto 0); + signal sendbyte_seq_start_x : std_logic; + signal sendbyte_byte_x : std_logic_vector(7 downto 0); + signal readbyte_seq_start_x : std_logic; + signal read_seq_ctr_x : std_logic; + signal reg_data_x : std_logic_vector(31 downto 0); + + signal sdio_sendbyte : std_logic; + signal sclk_sendbyte : std_logic; + signal sendbyte_done : std_logic; + + signal sclk_readbyte : std_logic; + signal readbyte_byte : std_logic_vector(7 downto 0); + signal readbyte_done : std_logic; + + type STATES is (S_RESET, + S_IDLE, + S_START, + S_START_WAIT, + + S_SEND_CMD_A, + S_SEND_CMD_A_WAIT, + S_SEND_CMD_B, + S_SEND_CMD_B_WAIT, + + S_SEND_DATA, + S_SEND_DATA_WAIT, + S_GET_DATA, + S_GET_DATA_WAIT, + + S_STOP, + S_STOP_WAIT + ); + signal STATE, NEXT_STATE : STATES; + + -- SPI Timer + signal wait_timer_done : std_logic; + + -- TRBNet Slave Bus + signal slv_data_out_o : std_logic_vector(31 downto 0); + signal slv_no_more_data_o : std_logic; + signal slv_unknown_addr_o : std_logic; + signal slv_ack_o : std_logic; + signal spi_chipid : std_logic_vector(6 downto 0); + signal spi_rw_bit : std_logic; + signal spi_registerid : std_logic_vector(12 downto 0); + signal spi_register_data : std_logic_vector(7 downto 0); + signal spi_register_value_read : std_logic_vector(7 downto 0); + +begin + + -- Timer + nx_timer_1: nx_timer + generic map ( + CTR_WIDTH => 8 + ) + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + TIMER_START_IN => wait_timer_init, + TIMER_DONE_OUT => wait_timer_done + ); + + adc_spi_sendbyte_1: adc_spi_sendbyte + generic map ( + SPI_SPEED => SPI_SPEED + ) + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + START_IN => sendbyte_seq_start, + BYTE_IN => sendbyte_byte, + SEQUENCE_DONE_OUT => sendbyte_done, + SDIO_OUT => sdio_sendbyte, + SCLK_OUT => sclk_sendbyte + ); + + adc_spi_readbyte_1: adc_spi_readbyte + generic map ( + SPI_SPEED => SPI_SPEED + ) + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + START_IN => readbyte_seq_start, + BYTE_OUT => readbyte_byte, + SEQUENCE_DONE_OUT => readbyte_done, + SDIO_IN => sdio, + SCLK_OUT => sclk_readbyte + ); + + -- Debug Line + + DEBUG_OUT(0) <= CLK_IN; + DEBUG_OUT(1) <= SCLK_OUT; + DEBUG_OUT(2) <= SDIO_INOUT; + DEBUG_OUT(3) <= CSB_OUT; + DEBUG_OUT(4) <= spi_busy; + DEBUG_OUT(5) <= wait_timer_done; + DEBUG_OUT(6) <= sendbyte_seq_start; + DEBUG_OUT(7) <= sendbyte_done; + DEBUG_OUT(8) <= sclk_sendbyte; + DEBUG_OUT(9) <= sdio_sendbyte; + DEBUG_OUT(10) <= sclk_readbyte; + DEBUG_OUT(11) <= takeover_sdio; + + -- Sync SPI SDIO Line + sdio_i <= SDIO_INOUT; + + PROC_I2C_LINES_SYNC: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + sdio_x <= '1'; + sdio <= '1'; + else + sdio_x <= sdio_i; + sdio <= sdio_x; + end if; + end if; + end process PROC_I2C_LINES_SYNC; + + PROC_I2C_MASTER_TRANSFER: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + spi_busy <= '1'; + sendbyte_seq_start <= '0'; + readbyte_seq_start <= '0'; + sendbyte_byte <= (others => '0'); + wait_timer_init <= (others => '0'); + reg_data <= (others => '0'); + read_seq_ctr <= '0'; + STATE <= S_RESET; + else + spi_busy <= spi_busy_x; + sendbyte_seq_start <= sendbyte_seq_start_x; + readbyte_seq_start <= readbyte_seq_start_x; + sendbyte_byte <= sendbyte_byte_x; + wait_timer_init <= wait_timer_init_x; + reg_data <= reg_data_x; + read_seq_ctr <= read_seq_ctr_x; + STATE <= NEXT_STATE; + end if; + end if; + end process PROC_I2C_MASTER_TRANSFER; + + + PROC_I2C_MASTER: process(STATE, + spi_start, + wait_timer_done, + sendbyte_done, + readbyte_done + ) + + begin + -- Defaults + takeover_sdio <= '0'; + sclk_o <= '0'; + csb_o <= '0'; + spi_busy_x <= '1'; + sendbyte_seq_start_x <= '0'; + sendbyte_byte_x <= (others => '0'); + readbyte_seq_start_x <= '0'; + wait_timer_init_x <= (others => '0'); + reg_data_x <= reg_data; + read_seq_ctr_x <= read_seq_ctr; + + case STATE is + + when S_RESET => + reg_data_x <= (others => '0'); + NEXT_STATE <= S_IDLE; + + when S_IDLE => + csb_o <= '1'; + if (spi_start = '1') then + reg_data_x <= x"8000_0000"; -- Set Running , clear all other bits + NEXT_STATE <= S_START; + else + spi_busy_x <= '0'; + reg_data_x <= reg_data and x"7fff_ffff"; -- clear running bit; + read_seq_ctr_x <= '0'; + NEXT_STATE <= S_IDLE; + end if; + + -- SPI START Sequence + when S_START => + wait_timer_init_x <= SPI_SPEED srl 2; + NEXT_STATE <= S_START_WAIT; + + when S_START_WAIT => + if (wait_timer_done = '0') then + NEXT_STATE <= S_START_WAIT; + else + takeover_sdio <= '1'; + NEXT_STATE <= S_SEND_CMD_A; + end if; + + -- I2C SEND CMD Part1 + when S_SEND_CMD_A => + takeover_sdio <= '1'; + sendbyte_byte_x(7) <= spi_rw_bit; + sendbyte_byte_x(6 downto 5) <= "00"; + sendbyte_byte_x(4 downto 0) <= spi_registerid(12 downto 8); + sendbyte_seq_start_x <= '1'; + NEXT_STATE <= S_SEND_CMD_A_WAIT; + + when S_SEND_CMD_A_WAIT => + takeover_sdio <= '1'; + if (sendbyte_done = '0') then + NEXT_STATE <= S_SEND_CMD_A_WAIT; + else + NEXT_STATE <= S_SEND_CMD_B; + end if; + + -- I2C SEND CMD Part1 + when S_SEND_CMD_B => + takeover_sdio <= '1'; + sendbyte_byte_x(7 downto 0) <= spi_registerid(7 downto 0); + sendbyte_seq_start_x <= '1'; + NEXT_STATE <= S_SEND_CMD_B_WAIT; + + when S_SEND_CMD_B_WAIT => + takeover_sdio <= '1'; + if (sendbyte_done = '0') then + NEXT_STATE <= S_SEND_CMD_B_WAIT; + else + if (spi_rw_bit = '1') then + NEXT_STATE <= S_GET_DATA; + else + NEXT_STATE <= S_SEND_DATA; + end if; + end if; + + -- I2C SEND DataWord + when S_SEND_DATA => + takeover_sdio <= '1'; + sendbyte_byte_x <= spi_register_data; + sendbyte_seq_start_x <= '1'; + NEXT_STATE <= S_SEND_DATA_WAIT; + + when S_SEND_DATA_WAIT => + takeover_sdio <= '1'; + if (sendbyte_done = '0') then + NEXT_STATE <= S_SEND_DATA_WAIT; + else + NEXT_STATE <= S_STOP; + end if; + + -- I2C GET DataWord + when S_GET_DATA => + readbyte_seq_start_x <= '1'; + NEXT_STATE <= S_GET_DATA_WAIT; + + when S_GET_DATA_WAIT => + if (readbyte_done = '0') then + NEXT_STATE <= S_GET_DATA_WAIT; + else + reg_data_x(7 downto 0) <= readbyte_byte; + NEXT_STATE <= S_STOP; + end if; + + -- SPI STOP Sequence + when S_STOP => + wait_timer_init_x <= SPI_SPEED srl 2; + NEXT_STATE <= S_STOP_WAIT; + + when S_STOP_WAIT => + if (wait_timer_done = '0') then + NEXT_STATE <= S_STOP_WAIT; + else + reg_data_x <= reg_data or x"4000_0000"; -- Set DONE Bit + NEXT_STATE <= S_IDLE; + end if; + + end case; + end process PROC_I2C_MASTER; + + ----------------------------------------------------------------------------- + -- TRBNet Slave Bus + ----------------------------------------------------------------------------- + -- + -- Write bit definition + -- ==================== + -- + -- D[31] SPI_GO 0 => don't do anything on SPI, + -- 1 => start SPI access + -- D[30] SPI_ACTION 0 => write byte, 1 => read byte + -- D[20:8] SPI_CMD SPI Register Id + -- D[7:0] SPI_DATA data to be written + -- + -- Read bit definition + -- =================== + -- + -- D[31] RUNNING whatever + -- D[30] SPI_DONE whatever + -- D[29:21] reserved reserved + -- D[20:16] debug subject to change, don't use + -- D[15:8] reserved reserved + -- D[7:0] SPI_DATA result of SPI read operation + -- + + PROC_SLAVE_BUS: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + slv_data_out_o <= (others => '0'); + slv_no_more_data_o <= '0'; + slv_unknown_addr_o <= '0'; + slv_ack_o <= '0'; + spi_start <= '0'; + command_ack_o <= '0'; + + spi_chipid <= (others => '0'); + spi_rw_bit <= '0'; + spi_registerid <= (others => '0'); + spi_register_data <= (others => '0'); + spi_register_value_read <= (others => '0'); + + else + slv_data_out_o <= (others => '0'); + slv_unknown_addr_o <= '0'; + slv_no_more_data_o <= '0'; + + spi_start <= '0'; + command_ack_o <= '0'; + + --if (spi_busy = '0' and INTERNAL_COMMAND_IN(31) = '1') then + -- spi_rw_bit <= INTERNAL_COMMAND_IN(30); + -- spi_registerid <= INTERNAL_COMMAND_IN(20 downto 8); + -- spi_register_data <= INTERNAL_COMMAND_IN(7 downto 0); + -- spi_start <= '1'; + -- command_ack_o <= '1'; + -- slv_ack_o <= '1'; + -- + --elsif (SLV_WRITE_IN = '1') then + if (SLV_WRITE_IN = '1') then + if (spi_busy = '0' and SLV_DATA_IN(31) = '1') then + spi_rw_bit <= SLV_DATA_IN(30); + spi_registerid <= SLV_DATA_IN(20 downto 8); + spi_register_data <= SLV_DATA_IN(7 downto 0); + spi_start <= '1'; + slv_ack_o <= '1'; + else + slv_ack_o <= '1'; + end if; + + elsif (SLV_READ_IN = '1') then + if (spi_busy = '1') then + slv_no_more_data_o <= '1'; + slv_ack_o <= '0'; + else + slv_data_out_o <= reg_data; + slv_ack_o <= '1'; + end if; + + else + slv_ack_o <= '0'; + end if; + + end if; + end if; + end process PROC_SLAVE_BUS; + + + ----------------------------------------------------------------------------- + -- Output Signals + ----------------------------------------------------------------------------- + + -- SPI Outputs + SDIO_INOUT <= sdio_sendbyte when (takeover_sdio = '1') + else 'Z'; + + SCLK_OUT <= sclk_o or + sclk_sendbyte or + sclk_readbyte; + + CSB_OUT <= csb_o; + COMMAND_ACK_OUT <= command_ack_o; + + -- Slave Bus + SLV_DATA_OUT <= slv_data_out_o; + SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; + SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o; + SLV_ACK_OUT <= slv_ack_o; + +end Behavioral; diff --git a/nxyter/source/adc_spi_readbyte.vhd b/nxyter/source/adc_spi_readbyte.vhd index ab125a3..539f18a 100644 --- a/nxyter/source/adc_spi_readbyte.vhd +++ b/nxyter/source/adc_spi_readbyte.vhd @@ -1,172 +1,172 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.nxyter_components.all; - - -entity adc_spi_readbyte is - generic ( - SPI_SPEED : unsigned(7 downto 0) := x"32" - ); - port( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - - START_IN : in std_logic; - BYTE_OUT : out std_logic_vector(7 downto 0); - SEQUENCE_DONE_OUT : out std_logic; - - -- SPI connections - SDIO_IN : in std_logic; - SCLK_OUT : out std_logic - ); -end entity; - -architecture Behavioral of adc_spi_readbyte is - - -- Send Byte - signal sclk_o : std_logic; - signal spi_start : std_logic; - - signal sequence_done_o : std_logic; - signal spi_byte : unsigned(7 downto 0); - signal bit_ctr : unsigned(3 downto 0); - signal spi_ack_o : std_logic; - signal wait_timer_init : unsigned(7 downto 0); - - signal sequence_done_o_x : std_logic; - signal spi_byte_x : unsigned(7 downto 0); - signal bit_ctr_x : unsigned(3 downto 0); - signal spi_ack_o_x : std_logic; - signal wait_timer_init_x : unsigned(7 downto 0); - - type STATES is (S_IDLE, - S_UNSET_SCKL, - S_UNSET_SCKL_HOLD, - S_GET_BIT, - S_SET_SCKL, - S_NEXT_BIT, - S_DONE - ); - signal STATE, NEXT_STATE : STATES; - - -- Wait Timer - signal wait_timer_done : std_logic; - -begin - - -- Timer - nx_timer_1: nx_timer - generic map( - CTR_WIDTH => 8 - ) - port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - TIMER_START_IN => wait_timer_init, - TIMER_DONE_OUT => wait_timer_done - ); - - - PROC_READ_BYTE_TRANSFER: process(CLK_IN) - begin - if( rising_edge(CLK_IN) ) then - if( RESET_IN = '1' ) then - sequence_done_o <= '0'; - bit_ctr <= (others => '0'); - spi_ack_o <= '0'; - wait_timer_init <= (others => '0'); - STATE <= S_IDLE; - else - sequence_done_o <= sequence_done_o_x; - spi_byte <= spi_byte_x; - bit_ctr <= bit_ctr_x; - spi_ack_o <= spi_ack_o_x; - wait_timer_init <= wait_timer_init_x; - STATE <= NEXT_STATE; - end if; - end if; - end process PROC_READ_BYTE_TRANSFER; - - PROC_READ_BYTE: process(STATE, - START_IN, - wait_timer_done, - bit_ctr - ) - begin - sclk_o <= '0'; - sequence_done_o_x <= '0'; - spi_byte_x <= spi_byte; - bit_ctr_x <= bit_ctr; - spi_ack_o_x <= spi_ack_o; - wait_timer_init_x <= (others => '0'); - - case STATE is - when S_IDLE => - if (START_IN = '1') then - spi_byte_x <= (others => '0'); - bit_ctr_x <= x"7"; - wait_timer_init_x <= SPI_SPEED srl 1; - NEXT_STATE <= S_UNSET_SCKL; - else - NEXT_STATE <= S_IDLE; - end if; - - -- SPI Read byte - when S_UNSET_SCKL => - wait_timer_init_x <= SPI_SPEED srl 1; - NEXT_STATE <= S_UNSET_SCKL_HOLD; - - when S_UNSET_SCKL_HOLD => - if (wait_timer_done = '0') then - NEXT_STATE <= S_UNSET_SCKL_HOLD; - else - NEXT_STATE <= S_GET_BIT; - end if; - - when S_GET_BIT => - spi_byte_x(0) <= SDIO_IN; - wait_timer_init_x <= SPI_SPEED srl 1; - NEXT_STATE <= S_SET_SCKL; - - when S_SET_SCKL => - sclk_o <= '1'; - if (wait_timer_done = '0') then - NEXT_STATE <= S_SET_SCKL; - else - wait_timer_init_x <= SPI_SPEED srl 1; - NEXT_STATE <= S_NEXT_BIT; - end if; - - when S_NEXT_BIT => - sclk_o <= '1'; - if (bit_ctr > 0) then - bit_ctr_x <= bit_ctr - 1; - spi_byte_x <= spi_byte sll 1; - wait_timer_init_x <= SPI_SPEED srl 1; - NEXT_STATE <= S_UNSET_SCKL; - else - NEXT_STATE <= S_DONE; - end if; - - when S_DONE => - sclk_o <= '1'; - sequence_done_o_x <= '1'; - NEXT_STATE <= S_IDLE; - - end case; - end process PROC_READ_BYTE; - - ----------------------------------------------------------------------------- - -- Output Signals - ----------------------------------------------------------------------------- - - SEQUENCE_DONE_OUT <= sequence_done_o; - BYTE_OUT <= spi_byte; - - -- I2c Outputs - SCLK_OUT <= sclk_o; - -end Behavioral; +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.nxyter_components.all; + + +entity adc_spi_readbyte is + generic ( + SPI_SPEED : unsigned(7 downto 0) := x"32" + ); + port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + + START_IN : in std_logic; + BYTE_OUT : out std_logic_vector(7 downto 0); + SEQUENCE_DONE_OUT : out std_logic; + + -- SPI connections + SDIO_IN : in std_logic; + SCLK_OUT : out std_logic + ); +end entity; + +architecture Behavioral of adc_spi_readbyte is + + -- Send Byte + signal sclk_o : std_logic; + signal spi_start : std_logic; + + signal sequence_done_o : std_logic; + signal spi_byte : unsigned(7 downto 0); + signal bit_ctr : unsigned(3 downto 0); + signal spi_ack_o : std_logic; + signal wait_timer_init : unsigned(7 downto 0); + + signal sequence_done_o_x : std_logic; + signal spi_byte_x : unsigned(7 downto 0); + signal bit_ctr_x : unsigned(3 downto 0); + signal spi_ack_o_x : std_logic; + signal wait_timer_init_x : unsigned(7 downto 0); + + type STATES is (S_IDLE, + S_UNSET_SCKL, + S_UNSET_SCKL_HOLD, + S_GET_BIT, + S_SET_SCKL, + S_NEXT_BIT, + S_DONE + ); + signal STATE, NEXT_STATE : STATES; + + -- Wait Timer + signal wait_timer_done : std_logic; + +begin + + -- Timer + nx_timer_1: nx_timer + generic map( + CTR_WIDTH => 8 + ) + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + TIMER_START_IN => wait_timer_init, + TIMER_DONE_OUT => wait_timer_done + ); + + + PROC_READ_BYTE_TRANSFER: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + sequence_done_o <= '0'; + bit_ctr <= (others => '0'); + spi_ack_o <= '0'; + wait_timer_init <= (others => '0'); + STATE <= S_IDLE; + else + sequence_done_o <= sequence_done_o_x; + spi_byte <= spi_byte_x; + bit_ctr <= bit_ctr_x; + spi_ack_o <= spi_ack_o_x; + wait_timer_init <= wait_timer_init_x; + STATE <= NEXT_STATE; + end if; + end if; + end process PROC_READ_BYTE_TRANSFER; + + PROC_READ_BYTE: process(STATE, + START_IN, + wait_timer_done, + bit_ctr + ) + begin + sclk_o <= '0'; + sequence_done_o_x <= '0'; + spi_byte_x <= spi_byte; + bit_ctr_x <= bit_ctr; + spi_ack_o_x <= spi_ack_o; + wait_timer_init_x <= (others => '0'); + + case STATE is + when S_IDLE => + if (START_IN = '1') then + spi_byte_x <= (others => '0'); + bit_ctr_x <= x"7"; + wait_timer_init_x <= SPI_SPEED srl 1; + NEXT_STATE <= S_UNSET_SCKL; + else + NEXT_STATE <= S_IDLE; + end if; + + -- SPI Read byte + when S_UNSET_SCKL => + wait_timer_init_x <= SPI_SPEED srl 1; + NEXT_STATE <= S_UNSET_SCKL_HOLD; + + when S_UNSET_SCKL_HOLD => + if (wait_timer_done = '0') then + NEXT_STATE <= S_UNSET_SCKL_HOLD; + else + NEXT_STATE <= S_GET_BIT; + end if; + + when S_GET_BIT => + spi_byte_x(0) <= SDIO_IN; + wait_timer_init_x <= SPI_SPEED srl 1; + NEXT_STATE <= S_SET_SCKL; + + when S_SET_SCKL => + sclk_o <= '1'; + if (wait_timer_done = '0') then + NEXT_STATE <= S_SET_SCKL; + else + wait_timer_init_x <= SPI_SPEED srl 1; + NEXT_STATE <= S_NEXT_BIT; + end if; + + when S_NEXT_BIT => + sclk_o <= '1'; + if (bit_ctr > 0) then + bit_ctr_x <= bit_ctr - 1; + spi_byte_x <= spi_byte sll 1; + wait_timer_init_x <= SPI_SPEED srl 1; + NEXT_STATE <= S_UNSET_SCKL; + else + NEXT_STATE <= S_DONE; + end if; + + when S_DONE => + sclk_o <= '1'; + sequence_done_o_x <= '1'; + NEXT_STATE <= S_IDLE; + + end case; + end process PROC_READ_BYTE; + + ----------------------------------------------------------------------------- + -- Output Signals + ----------------------------------------------------------------------------- + + SEQUENCE_DONE_OUT <= sequence_done_o; + BYTE_OUT <= spi_byte; + + -- I2c Outputs + SCLK_OUT <= sclk_o; + +end Behavioral; diff --git a/nxyter/source/adc_spi_sendbyte.vhd b/nxyter/source/adc_spi_sendbyte.vhd index 923f72d..5d664a3 100644 --- a/nxyter/source/adc_spi_sendbyte.vhd +++ b/nxyter/source/adc_spi_sendbyte.vhd @@ -1,161 +1,161 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.nxyter_components.all; - - -entity adc_spi_sendbyte is - generic ( - SPI_SPEED : unsigned(7 downto 0) := x"32" - ); - port( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - - START_IN : in std_logic; - BYTE_IN : in std_logic_vector(7 downto 0); - SEQUENCE_DONE_OUT : out std_logic; - - -- SPI connections - SCLK_OUT : out std_logic; - SDIO_OUT : out std_logic - ); -end entity; - -architecture Behavioral of adc_spi_sendbyte is - - -- Send Byte - signal sclk_o : std_logic; - signal sdio_o : std_logic; - signal spi_start : std_logic; - - signal sequence_done_o : std_logic; - signal spi_byte : unsigned(7 downto 0); - signal bit_ctr : unsigned(3 downto 0); - signal wait_timer_init : unsigned(7 downto 0); - - signal sequence_done_o_x : std_logic; - signal spi_byte_x : unsigned(7 downto 0); - signal bit_ctr_x : unsigned(3 downto 0); - signal wait_timer_init_x : unsigned(7 downto 0); - - type STATES is (S_IDLE, - S_SET_SDIO, - S_SET_SCLK, - S_NEXT_BIT, - S_DONE - ); - signal STATE, NEXT_STATE : STATES; - - -- Wait Timer - signal wait_timer_done : std_logic; - -begin - - -- Timer - nx_timer_1: nx_timer - generic map ( - CTR_WIDTH => 8 - ) - port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - TIMER_START_IN => wait_timer_init, - TIMER_DONE_OUT => wait_timer_done - ); - - - PROC_SEND_BYTE_TRANSFER: process(CLK_IN) - begin - if( rising_edge(CLK_IN) ) then - if( RESET_IN = '1' ) then - sequence_done_o <= '0'; - bit_ctr <= (others => '0'); - wait_timer_init <= (others => '0'); - STATE <= S_IDLE; - else - sequence_done_o <= sequence_done_o_x; - spi_byte <= spi_byte_x; - bit_ctr <= bit_ctr_x; - wait_timer_init <= wait_timer_init_x; - STATE <= NEXT_STATE; - end if; - end if; - end process PROC_SEND_BYTE_TRANSFER; - - PROC_SEND_BYTE: process(STATE, - START_IN, - wait_timer_done, - bit_ctr - ) - begin - sdio_o <= '0'; - sclk_o <= '0'; - sequence_done_o_x <= '0'; - spi_byte_x <= spi_byte; - bit_ctr_x <= bit_ctr; - wait_timer_init_x <= (others => '0'); - - case STATE is - when S_IDLE => - if (START_IN = '1') then - spi_byte_x <= BYTE_IN; - bit_ctr_x <= x"7"; - wait_timer_init_x <= SPI_SPEED srl 1; - NEXT_STATE <= S_SET_SDIO; - else - NEXT_STATE <= S_IDLE; - end if; - - when S_SET_SDIO => - sdio_o <= spi_byte(7); - if (wait_timer_done = '0') then - NEXT_STATE <= S_SET_SDIO; - else - wait_timer_init_x <= SPI_SPEED srl 1; - NEXT_STATE <= S_SET_SCLK; - end if; - - when S_SET_SCLK => - sdio_o <= spi_byte(7); - sclk_o <= '1'; - if (wait_timer_done = '0') then - NEXT_STATE <= S_SET_SCLK; - else - NEXT_STATE <= S_NEXT_BIT; - end if; - - when S_NEXT_BIT => - sdio_o <= spi_byte(7); - sclk_o <= '1'; - if (bit_ctr > 0) then - bit_ctr_x <= bit_ctr - 1; - spi_byte_x <= spi_byte sll 1; - wait_timer_init_x <= SPI_SPEED srl 1; - NEXT_STATE <= S_SET_SDIO; - else - NEXT_STATE <= S_DONE; - end if; - - when S_DONE => - sdio_o <= spi_byte(7); - sclk_o <= '1'; - sequence_done_o_x <= '1'; - NEXT_STATE <= S_IDLE; - - end case; - end process PROC_SEND_BYTE; - - ----------------------------------------------------------------------------- - -- Output Signals - ----------------------------------------------------------------------------- - - SEQUENCE_DONE_OUT <= sequence_done_o; - - -- SPI Outputs - SDIO_OUT <= sdio_o; - SCLK_OUT <= sclk_o; - -end Behavioral; +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.nxyter_components.all; + + +entity adc_spi_sendbyte is + generic ( + SPI_SPEED : unsigned(7 downto 0) := x"32" + ); + port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + + START_IN : in std_logic; + BYTE_IN : in std_logic_vector(7 downto 0); + SEQUENCE_DONE_OUT : out std_logic; + + -- SPI connections + SCLK_OUT : out std_logic; + SDIO_OUT : out std_logic + ); +end entity; + +architecture Behavioral of adc_spi_sendbyte is + + -- Send Byte + signal sclk_o : std_logic; + signal sdio_o : std_logic; + signal spi_start : std_logic; + + signal sequence_done_o : std_logic; + signal spi_byte : unsigned(7 downto 0); + signal bit_ctr : unsigned(3 downto 0); + signal wait_timer_init : unsigned(7 downto 0); + + signal sequence_done_o_x : std_logic; + signal spi_byte_x : unsigned(7 downto 0); + signal bit_ctr_x : unsigned(3 downto 0); + signal wait_timer_init_x : unsigned(7 downto 0); + + type STATES is (S_IDLE, + S_SET_SDIO, + S_SET_SCLK, + S_NEXT_BIT, + S_DONE + ); + signal STATE, NEXT_STATE : STATES; + + -- Wait Timer + signal wait_timer_done : std_logic; + +begin + + -- Timer + nx_timer_1: nx_timer + generic map ( + CTR_WIDTH => 8 + ) + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + TIMER_START_IN => wait_timer_init, + TIMER_DONE_OUT => wait_timer_done + ); + + + PROC_SEND_BYTE_TRANSFER: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + sequence_done_o <= '0'; + bit_ctr <= (others => '0'); + wait_timer_init <= (others => '0'); + STATE <= S_IDLE; + else + sequence_done_o <= sequence_done_o_x; + spi_byte <= spi_byte_x; + bit_ctr <= bit_ctr_x; + wait_timer_init <= wait_timer_init_x; + STATE <= NEXT_STATE; + end if; + end if; + end process PROC_SEND_BYTE_TRANSFER; + + PROC_SEND_BYTE: process(STATE, + START_IN, + wait_timer_done, + bit_ctr + ) + begin + sdio_o <= '0'; + sclk_o <= '0'; + sequence_done_o_x <= '0'; + spi_byte_x <= spi_byte; + bit_ctr_x <= bit_ctr; + wait_timer_init_x <= (others => '0'); + + case STATE is + when S_IDLE => + if (START_IN = '1') then + spi_byte_x <= BYTE_IN; + bit_ctr_x <= x"7"; + wait_timer_init_x <= SPI_SPEED srl 1; + NEXT_STATE <= S_SET_SDIO; + else + NEXT_STATE <= S_IDLE; + end if; + + when S_SET_SDIO => + sdio_o <= spi_byte(7); + if (wait_timer_done = '0') then + NEXT_STATE <= S_SET_SDIO; + else + wait_timer_init_x <= SPI_SPEED srl 1; + NEXT_STATE <= S_SET_SCLK; + end if; + + when S_SET_SCLK => + sdio_o <= spi_byte(7); + sclk_o <= '1'; + if (wait_timer_done = '0') then + NEXT_STATE <= S_SET_SCLK; + else + NEXT_STATE <= S_NEXT_BIT; + end if; + + when S_NEXT_BIT => + sdio_o <= spi_byte(7); + sclk_o <= '1'; + if (bit_ctr > 0) then + bit_ctr_x <= bit_ctr - 1; + spi_byte_x <= spi_byte sll 1; + wait_timer_init_x <= SPI_SPEED srl 1; + NEXT_STATE <= S_SET_SDIO; + else + NEXT_STATE <= S_DONE; + end if; + + when S_DONE => + sdio_o <= spi_byte(7); + sclk_o <= '1'; + sequence_done_o_x <= '1'; + NEXT_STATE <= S_IDLE; + + end case; + end process PROC_SEND_BYTE; + + ----------------------------------------------------------------------------- + -- Output Signals + ----------------------------------------------------------------------------- + + SEQUENCE_DONE_OUT <= sequence_done_o; + + -- SPI Outputs + SDIO_OUT <= sdio_o; + SCLK_OUT <= sclk_o; + +end Behavioral; diff --git a/nxyter/source/debug_multiplexer.vhd b/nxyter/source/debug_multiplexer.vhd index ac02bf3..a80d6e6 100644 --- a/nxyter/source/debug_multiplexer.vhd +++ b/nxyter/source/debug_multiplexer.vhd @@ -1,111 +1,111 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.nxyter_components.all; - -entity debug_multiplexer is - generic ( - NUM_PORTS : integer range 1 to 32 := 1 - ); - port( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - - DEBUG_LINE_IN : in debug_array_t(0 to NUM_PORTS-1); - DEBUG_LINE_OUT : out std_logic_vector(15 downto 0); - - -- Slave bus - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_ADDR_IN : in std_logic_vector(15 downto 0); - SLV_ACK_OUT : out std_logic; - SLV_NO_MORE_DATA_OUT : out std_logic; - SLV_UNKNOWN_ADDR_OUT : out std_logic - - ); -end entity; - -architecture Behavioral of debug_multiplexer is - - signal port_select : std_logic_vector(7 downto 0); - signal debug_line_o : std_logic_vector(15 downto 0); - - signal slv_data_out_o : std_logic_vector(31 downto 0); - signal slv_no_more_data_o : std_logic; - signal slv_unknown_addr_o : std_logic; - signal slv_ack_o : std_logic; - -begin - - PROC_MULTIPLEXER: process(port_select, - DEBUG_LINE_IN) - begin - if (unsigned(port_select) < NUM_PORTS) then - debug_line_o <= DEBUG_LINE_IN(to_integer(unsigned(port_select))); - else - debug_line_o <= (others => '1'); - end if; - end process PROC_MULTIPLEXER; - - PROC_SLAVE_BUS: process(CLK_IN) - begin - if( rising_edge(CLK_IN) ) then - if( RESET_IN = '1' ) then - slv_data_out_o <= (others => '0'); - slv_no_more_data_o <= '0'; - slv_unknown_addr_o <= '0'; - slv_ack_o <= '0'; - port_select <= (others => '0'); - else - slv_ack_o <= '1'; - slv_unknown_addr_o <= '0'; - slv_no_more_data_o <= '0'; - slv_data_out_o <= (others => '0'); - - if (SLV_WRITE_IN = '1') then - case SLV_ADDR_IN is - when x"0000" => - if (unsigned(SLV_DATA_IN(7 downto 0)) < NUM_PORTS) then - port_select <= SLV_DATA_IN(7 downto 0); - end if; - slv_ack_o <= '1'; - - when others => - slv_unknown_addr_o <= '1'; - slv_ack_o <= '0'; - end case; - - elsif (SLV_READ_IN = '1') then - case SLV_ADDR_IN is - when x"0000" => - slv_data_out_o(7 downto 0) <= port_select; - slv_data_out_o(31 downto 8) <= (others => '0'); - - when others => - slv_unknown_addr_o <= '1'; - slv_ack_o <= '0'; - end case; - - else - slv_ack_o <= '0'; - end if; - end if; - end if; - end process PROC_SLAVE_BUS; - - ----------------------------------------------------------------------------- - -- Output Signals - ----------------------------------------------------------------------------- - - SLV_DATA_OUT <= slv_data_out_o; - SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; - SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o; - SLV_ACK_OUT <= slv_ack_o; - - DEBUG_LINE_OUT <= debug_line_o; - -end Behavioral; +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.nxyter_components.all; + +entity debug_multiplexer is + generic ( + NUM_PORTS : integer range 1 to 32 := 1 + ); + port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + + DEBUG_LINE_IN : in debug_array_t(0 to NUM_PORTS-1); + DEBUG_LINE_OUT : out std_logic_vector(15 downto 0); + + -- Slave bus + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ADDR_IN : in std_logic_vector(15 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic + + ); +end entity; + +architecture Behavioral of debug_multiplexer is + + signal port_select : std_logic_vector(7 downto 0); + signal debug_line_o : std_logic_vector(15 downto 0); + + signal slv_data_out_o : std_logic_vector(31 downto 0); + signal slv_no_more_data_o : std_logic; + signal slv_unknown_addr_o : std_logic; + signal slv_ack_o : std_logic; + +begin + + PROC_MULTIPLEXER: process(port_select, + DEBUG_LINE_IN) + begin + if (unsigned(port_select) < NUM_PORTS) then + debug_line_o <= DEBUG_LINE_IN(to_integer(unsigned(port_select))); + else + debug_line_o <= (others => '1'); + end if; + end process PROC_MULTIPLEXER; + + PROC_SLAVE_BUS: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + slv_data_out_o <= (others => '0'); + slv_no_more_data_o <= '0'; + slv_unknown_addr_o <= '0'; + slv_ack_o <= '0'; + port_select <= (others => '0'); + else + slv_ack_o <= '1'; + slv_unknown_addr_o <= '0'; + slv_no_more_data_o <= '0'; + slv_data_out_o <= (others => '0'); + + if (SLV_WRITE_IN = '1') then + case SLV_ADDR_IN is + when x"0000" => + if (unsigned(SLV_DATA_IN(7 downto 0)) < NUM_PORTS) then + port_select <= SLV_DATA_IN(7 downto 0); + end if; + slv_ack_o <= '1'; + + when others => + slv_unknown_addr_o <= '1'; + slv_ack_o <= '0'; + end case; + + elsif (SLV_READ_IN = '1') then + case SLV_ADDR_IN is + when x"0000" => + slv_data_out_o(7 downto 0) <= port_select; + slv_data_out_o(31 downto 8) <= (others => '0'); + + when others => + slv_unknown_addr_o <= '1'; + slv_ack_o <= '0'; + end case; + + else + slv_ack_o <= '0'; + end if; + end if; + end if; + end process PROC_SLAVE_BUS; + + ----------------------------------------------------------------------------- + -- Output Signals + ----------------------------------------------------------------------------- + + SLV_DATA_OUT <= slv_data_out_o; + SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; + SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o; + SLV_ACK_OUT <= slv_ack_o; + + DEBUG_LINE_OUT <= debug_line_o; + +end Behavioral; diff --git a/nxyter/source/nx_data_delay.vhd b/nxyter/source/nx_data_delay.vhd new file mode 100644 index 0000000..18e0a4a --- /dev/null +++ b/nxyter/source/nx_data_delay.vhd @@ -0,0 +1,226 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.nxyter_components.all; + +entity nx_data_delay is + port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + + -- Signals + NX_FRAME_IN : in std_logic_vector(31 downto 0); + ADC_DATA_IN : in std_logic_vector(11 downto 0); + NEW_DATA_IN : in std_logic; + + NX_FRAME_OUT : out std_logic_vector(31 downto 0); + ADC_DATA_OUT : out std_logic_vector(11 downto 0); + NEW_DATA_OUT : out std_logic; + + -- Slave bus + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ADDR_IN : in std_logic_vector(15 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic; + + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); +end entity; + +architecture Behavioral of nx_data_delay is + + -- FIFO Write Handler + signal fifo_data_in : std_logic_vector(43 downto 0); + signal fifo_full : std_logic; + signal fifo_write_enable : std_logic; + signal fifo_reset : std_logic; + + -- FIFO READ ENABLE + signal fifo_data_out : std_logic_vector(43 downto 0); + signal fifo_read_enable : std_logic; + signal fifo_empty : std_logic; + signal fifo_almost_empty : std_logic; + + signal fifo_data_valid_t : std_logic; + signal fifo_data_valid : std_logic; + + -- FIFO READ + signal nx_frame_o : std_logic_vector(31 downto 0); + signal adc_data_o : std_logic_vector(11 downto 0); + signal new_data_o : std_logic; + + -- Slave Bus + signal slv_data_o : std_logic_vector(31 downto 0); + signal slv_no_more_data_o : std_logic; + signal slv_unknown_addr_o : std_logic; + signal slv_ack_o : std_logic; + signal fifo_delay : std_logic_vector(6 downto 0); + signal fifo_delay_reset : std_logic; + +begin + + -- Debug Signals + DEBUG_OUT(0) <= CLK_IN; + DEBUG_OUT(1) <= fifo_reset; + DEBUG_OUT(2) <= fifo_full; + DEBUG_OUT(3) <= fifo_write_enable; + DEBUG_OUT(4) <= fifo_empty; + DEBUG_OUT(5) <= fifo_almost_empty; + DEBUG_OUT(6) <= fifo_read_enable; + DEBUG_OUT(7) <= fifo_data_valid; + DEBUG_OUT(8) <= new_data_o; + DEBUG_OUT(15 downto 9) <= nx_frame_o(6 downto 0); + + ----------------------------------------------------------------------------- + -- FIFO Delay Handler + ----------------------------------------------------------------------------- + + fifo_44_data_delay_1: fifo_44_data_delay + port map ( + Data => fifo_data_in, + Clock => CLK_IN, + WrEn => fifo_write_enable, + RdEn => fifo_read_enable, + Reset => fifo_reset, + AmEmptyThresh => fifo_delay, + Q => fifo_data_out, + Empty => fifo_empty, + Full => fifo_full, + AlmostEmpty => fifo_almost_empty + ); + + ----------------------------------------------------------------------------- + -- FIFO Handler + ----------------------------------------------------------------------------- + + -- Write to FIFO + PROC_WRITE_TO_FIFO: process(NEW_DATA_IN, + NX_FRAME_IN, + ADC_DATA_IN) + begin + if ( NEW_DATA_IN = '1' and fifo_full = '0') then + fifo_data_in(31 downto 0) <= NX_FRAME_IN; + fifo_data_in(43 downto 32) <= ADC_DATA_IN; + fifo_write_enable <= '1'; + else + fifo_data_in <= x"fff_ffff_ffff"; + fifo_write_enable <= '0'; + end if; + + end process PROC_WRITE_TO_FIFO; + + fifo_reset <= RESET_IN or fifo_delay_reset; + + -- FIFO Read Handler + fifo_read_enable <= not fifo_almost_empty; + + PROC_FIFO_READ_ENABLE: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' or fifo_reset = '1') then + fifo_data_valid_t <= '0'; + fifo_data_valid <= '0'; + else + -- Delay read signal by one CLK + fifo_data_valid_t <= fifo_read_enable; + fifo_data_valid <= fifo_data_valid_t; + end if; + end if; + end process PROC_FIFO_READ_ENABLE; + + PROC_NX_FIFO_READ: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if (RESET_IN = '1' or fifo_reset = '1') then + nx_frame_o <= (others => '0'); + adc_data_o <= (others => '0'); + new_data_o <= '0'; + else + if (fifo_data_valid = '1') then + nx_frame_o <= fifo_data_out(31 downto 0); + adc_data_o <= fifo_data_out(43 downto 32); + new_data_o <= '1'; + else + nx_frame_o <= x"ffff_ffff"; + adc_data_o <= x"fff"; + new_data_o <= '0'; + end if; + end if; + end if; + end process PROC_NX_FIFO_READ; + + ----------------------------------------------------------------------------- + -- TRBNet Slave Bus + ----------------------------------------------------------------------------- + + -- Give status info to the TRB Slow Control Channel + PROC_FIFO_REGISTERS: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + slv_data_o <= (others => '0'); + slv_ack_o <= '0'; + slv_unknown_addr_o <= '0'; + slv_no_more_data_o <= '0'; + fifo_delay <= "0001010"; + fifo_delay_reset <= '0'; + else + slv_data_o <= (others => '0'); + slv_unknown_addr_o <= '0'; + slv_no_more_data_o <= '0'; + fifo_delay_reset <= '0'; + + if (SLV_READ_IN = '1') then + case SLV_ADDR_IN is + when x"0000" => + slv_data_o( 6 downto 0) <= fifo_delay; + slv_data_o(31 downto 7) <= (others => '0'); + slv_ack_o <= '1'; + + when others => + slv_unknown_addr_o <= '1'; + slv_ack_o <= '0'; + end case; + + elsif (SLV_WRITE_IN = '1') then + case SLV_ADDR_IN is + when x"0000" => + if (unsigned(SLV_DATA_IN(6 downto 0)) >= 2 and + unsigned(SLV_DATA_IN(6 downto 0)) <= 120) then + fifo_delay <= SLV_DATA_IN(6 downto 0); + fifo_delay_reset <= '1'; + end if; + slv_ack_o <= '1'; + + when others => + slv_unknown_addr_o <= '1'; + slv_ack_o <= '0'; + + end case; + else + slv_ack_o <= '0'; + end if; + end if; + end if; + end process PROC_FIFO_REGISTERS; + + -- Output Signals + NX_FRAME_OUT <= nx_frame_o; + ADC_DATA_OUT <= adc_data_o; + NEW_DATA_OUT <= new_data_o; + + SLV_DATA_OUT <= slv_data_o; + SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; + SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o; + SLV_ACK_OUT <= slv_ack_o; + +end Behavioral; diff --git a/nxyter/source/nx_data_receiver.vhd b/nxyter/source/nx_data_receiver.vhd index b344212..29e2885 100644 --- a/nxyter/source/nx_data_receiver.vhd +++ b/nxyter/source/nx_data_receiver.vhd @@ -1,827 +1,835 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb3_components.all; -use work.nxyter_components.all; - -entity nx_data_receiver is - port( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - - -- nXyter Ports - NX_TIMESTAMP_CLK_IN : in std_logic; - NX_TIMESTAMP_IN : in std_logic_vector (7 downto 0); - - -- ADC Ports - ADC_CLK_DAT_IN : in std_logic; - ADC_FCLK_IN : in std_logic_vector(1 downto 0); - ADC_DCLK_IN : in std_logic_vector(1 downto 0); - ADC_SAMPLE_CLK_OUT : out std_logic; - ADC_A_IN : in std_logic_vector(1 downto 0); - ADC_B_IN : in std_logic_vector(1 downto 0); - ADC_NX_IN : in std_logic_vector(1 downto 0); - ADC_D_IN : in std_logic_vector(1 downto 0); - - -- Outputs - NX_TIMESTAMP_OUT : out std_logic_vector(31 downto 0); - ADC_DATA_OUT : out std_logic_vector(11 downto 0); - NEW_DATA_OUT : out std_logic; - - -- Slave bus - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_ADDR_IN : in std_logic_vector(15 downto 0); - SLV_ACK_OUT : out std_logic; - SLV_NO_MORE_DATA_OUT : out std_logic; - SLV_UNKNOWN_ADDR_OUT : out std_logic; - - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); -end entity; - -architecture Behavioral of nx_data_receiver is - - ----------------------------------------------------------------------------- - -- NX_TIMESTAMP_CLK Domain - ----------------------------------------------------------------------------- - - -- FIFO DC Input Handler - signal nx_timestamp_reg_t : std_logic_vector(7 downto 0); - signal nx_timestamp_reg : std_logic_vector(7 downto 0); - signal nx_fifo_full : std_logic; - signal nx_fifo_reset : std_logic; - - -- NX_TIMESTAMP_IN Process - signal frame_byte_ctr : unsigned(1 downto 0); - signal nx_frame_word : std_logic_vector(31 downto 0); - signal nx_new_frame : std_logic; - - -- Frame Sync Process - signal frame_byte_pos : unsigned(1 downto 0); - - -- RS Sync FlipFlop - signal nx_frame_synced : std_logic; - signal rs_sync_set : std_logic; - signal rs_sync_reset : std_logic; - - -- Parity Check - signal parity_error : std_logic; - - -- Write to FIFO Handler - signal nx_fifo_data_input : std_logic_vector(31 downto 0); - signal nx_fifo_write_enable : std_logic; - - -- NX Clock Active - signal nx_clk_active_ff_0 : std_logic; - signal nx_clk_active_ff_1 : std_logic; - signal nx_clk_active_ff_2 : std_logic; - - -- ADC Ckl Generator - signal adc_clk_skip : std_logic; - signal adc_sample_clk : std_logic; - signal johnson_ff_0 : std_logic; - signal johnson_ff_1 : std_logic; - signal adc_clk_inv : std_logic; - signal adc_clk_delay : std_logic_vector(2 downto 0); - - ----------------------------------------------------------------------------- - -- CLK_IN Domain - ----------------------------------------------------------------------------- - - -- NX FIFO_READ - signal nx_timestamp_t : std_logic_vector(31 downto 0); - signal nx_new_timestamp : std_logic; - signal nx_new_timestamp_ctr : unsigned(3 downto 0); - - signal nx_fifo_delay_r : std_logic_vector(4 downto 0); - signal nx_fifo_almost_empty : std_logic; - - -- NX FIFO Output Handler - signal nx_fifo_data : std_logic_vector(31 downto 0); - signal nx_fifo_empty : std_logic; - signal nx_fifo_read_enable : std_logic; - signal nx_fifo_data_valid_t : std_logic; - signal nx_fifo_data_valid : std_logic; - signal nx_read_enable_pause : std_logic; - - -- Resync Counter Process - signal resync_counter : unsigned(11 downto 0); - signal resync_ctr_inc : std_logic; - signal nx_clk_active : std_logic; - - -- Parity Error Counter Process - signal parity_error_counter : unsigned(11 downto 0); - signal parity_error_ctr_inc : std_logic; - - signal reg_nx_frame_synced_t : std_logic; - signal reg_nx_frame_synced : std_logic; - - ----------------------------------------------------------------------------- - -- ADC Data Handler - ----------------------------------------------------------------------------- - - -- ADC Handler - signal adc_reset_r : std_logic; - signal adc_reset_l : std_logic; - signal adc_reset : std_logic; - - signal adc_data : std_logic_vector(11 downto 0); - signal test_adc_data : std_logic_vector(11 downto 0); - signal adc_data_valid : std_logic; - - signal adc_data_t : std_logic_vector(11 downto 0); - signal adc_new_data : std_logic; - signal adc_new_data_ctr : unsigned(3 downto 0); - - -- Data Output Handler - type STATES is (IDLE, - WAIT_ADC, - WAIT_TIMESTAMP - ); - signal STATE : STATES; - signal STATE_d : std_logic_vector(1 downto 0); - - signal nx_timestamp_o : std_logic_vector(31 downto 0); - signal adc_data_o : std_logic_vector(11 downto 0); - signal new_data_o : std_logic; - - -- Slave Bus - signal slv_data_out_o : std_logic_vector(31 downto 0); - signal slv_no_more_data_o : std_logic; - signal slv_unknown_addr_o : std_logic; - signal slv_ack_o : std_logic; - - signal reset_resync_ctr : std_logic; - signal reset_parity_error_ctr : std_logic; - signal fifo_reset_r : std_logic; - - signal valid_data_d : std_logic; - -begin - - DEBUG_OUT(0) <= CLK_IN; - DEBUG_OUT(2 downto 1) <= STATE_d; - DEBUG_OUT(3) <= adc_data_valid; -- nx_new_timestamp; - --DEBUG_OUT(4) <= adc_new_data; - --DEBUG_OUT(5) <= new_data_o; - --DEBUG_OUT(6) <= nx_fifo_data_valid; - --DEBUG_OUT(7) <= valid_data_d;--(others => '0'); - --DEBUG_OUT(15 downto 8) <= nx_timestamp_reg; - --DEBUG_OUT(15 downto 8) <= (others => '0'); - DEBUG_OUT(15 downto 4) <= test_adc_data; - - PROC_DEBUG: process(NX_TIMESTAMP_CLK_IN) - begin - if( rising_edge(NX_TIMESTAMP_CLK_IN) ) then - if( RESET_IN = '1' ) then - valid_data_d <= '0'; - else - if ((nx_timestamp_reg /= x"7f") and - (nx_timestamp_reg /= x"06")) then - valid_data_d <= '1'; - else - valid_data_d <= '0'; - end if; - end if; - end if; - end process PROC_DEBUG; - - ----------------------------------------------------------------------------- - -- ADC CLK DOMAIN - ----------------------------------------------------------------------------- - - adc_ad9222_1: entity work.adc_ad9222 - generic map ( - CHANNELS => 4, - DEVICES => 2, - RESOLUTION => 12 - ) - port map ( - CLK => CLK_IN, - CLK_ADCREF => adc_sample_clk, - CLK_ADCDAT => ADC_CLK_DAT_IN, - RESTART_IN => adc_reset, - ADCCLK_OUT => ADC_SAMPLE_CLK_OUT, - - ADC_DATA(0) => ADC_NX_IN(0), - ADC_DATA(1) => ADC_B_IN(0), - ADC_DATA(2) => ADC_A_IN(0), - ADC_DATA(3) => ADC_D_IN(0), - - ADC_DATA(4) => ADC_NX_IN(1), - ADC_DATA(5) => ADC_A_IN(1), - ADC_DATA(6) => ADC_B_IN(1), - ADC_DATA(7) => ADC_D_IN(1), - - ADC_DCO => ADC_DCLK_IN, - ADC_FCO => ADC_FCLK_IN, - - DATA_OUT(11 downto 0) => adc_data, - DATA_OUT(23 downto 12) => test_adc_data, - DATA_OUT(95 downto 24) => open, - - FCO_OUT => open, - DATA_VALID_OUT(0) => adc_data_valid, - DATA_VALID_OUT(1) => open, - DEBUG => open - ); - - adc_reset <= adc_reset_l or RESET_IN; - - pulse_to_level_1: pulse_to_level - generic map ( - NUM_CYCLES => "10000" - ) - port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - PULSE_IN => adc_reset_r, - LEVEL_OUT => adc_reset_l - ); - - ----------------------------------------------------------------------------- - -- NX_TIMESTAMP_CLK_IN Domain - ----------------------------------------------------------------------------- - - nx_timestamp_reg <= NX_TIMESTAMP_IN when rising_edge(NX_TIMESTAMP_CLK_IN); - - -- Transfer 8 to 32Bit - PROC_8_TO_32_BIT: process(NX_TIMESTAMP_CLK_IN) - begin - if( rising_edge(NX_TIMESTAMP_CLK_IN) ) then - if( RESET_IN = '1' ) then - frame_byte_ctr <= (others => '0'); - nx_frame_word <= (others => '0'); - nx_new_frame <= '0'; - else - nx_new_frame <= '0'; - - case frame_byte_pos is - when "11" => nx_frame_word(31 downto 24) <= nx_timestamp_reg; - frame_byte_ctr <= frame_byte_ctr + 1; - - when "10" => nx_frame_word(23 downto 16) <= nx_timestamp_reg; - frame_byte_ctr <= frame_byte_ctr + 1; - - when "01" => nx_frame_word(15 downto 8) <= nx_timestamp_reg; - frame_byte_ctr <= frame_byte_ctr + 1; - - when "00" => nx_frame_word( 7 downto 0) <= nx_timestamp_reg; - if (frame_byte_ctr = "11") then - nx_new_frame <= '1'; - end if; - frame_byte_ctr <= (others => '0'); - end case; - end if; - end if; - end process PROC_8_TO_32_BIT; - - -- Frame Sync process - PROC_SYNC_TO_NX_FRAME: process(NX_TIMESTAMP_CLK_IN) - begin - if( rising_edge(NX_TIMESTAMP_CLK_IN) ) then - if( RESET_IN = '1' ) then - frame_byte_pos <= "11"; - rs_sync_set <= '0'; - rs_sync_reset <= '0'; - else - rs_sync_set <= '0'; - rs_sync_reset <= '0'; - if (nx_new_frame = '1') then - case nx_frame_word is - when x"7f7f7f06" => - rs_sync_set <= '1'; - frame_byte_pos <= frame_byte_pos - 1; - - when x"7f7f067f" => - rs_sync_reset <= '1'; - frame_byte_pos <= frame_byte_pos - 2; - - when x"7f067f7f" => - rs_sync_reset <= '1'; - frame_byte_pos <= frame_byte_pos - 3; - - when x"067f7f7f" => - rs_sync_reset <= '1'; - frame_byte_pos <= frame_byte_pos - 4; - - when others => - frame_byte_pos <= frame_byte_pos - 1; - end case; - else - frame_byte_pos <= frame_byte_pos - 1; - end if; - end if; - end if; - end process PROC_SYNC_TO_NX_FRAME; - - -- RS FlipFlop to hold Sync Status - PROC_RS_FRAME_SYNCED: process(NX_TIMESTAMP_CLK_IN) - begin - if( rising_edge(NX_TIMESTAMP_CLK_IN) ) then - if (RESET_IN = '1' or rs_sync_reset = '1') then - nx_frame_synced <= '0'; - elsif (rs_sync_set = '1') then - nx_frame_synced <= '1'; - end if; - end if; - end process PROC_RS_FRAME_SYNCED; - - -- Check Parity - PROC_PARITY_CHECK: process(NX_TIMESTAMP_CLK_IN) - variable parity_bits : std_logic_vector(22 downto 0); - variable parity : std_logic; - begin - if( rising_edge(NX_TIMESTAMP_CLK_IN) ) then - if (RESET_IN = '1') then - parity_error <= '0'; - else - parity_error <= '0'; - if (nx_new_frame = '1' and nx_frame_synced = '1') then - -- Timestamp Bit #6 is excluded (funny nxyter-bug) - parity_bits := nx_frame_word(31) & - nx_frame_word(30 downto 24) & - nx_frame_word(21 downto 16) & - nx_frame_word(14 downto 8) & - nx_frame_word( 2 downto 1); - parity := xor_all(parity_bits); - - if (parity /= nx_frame_word(0)) then - parity_error <= '1'; - end if; - end if; - end if; - end if; - end process PROC_PARITY_CHECK; - - -- Write to FIFO - PROC_WRITE_TO_FIFO: process(NX_TIMESTAMP_CLK_IN) - begin - if( rising_edge(NX_TIMESTAMP_CLK_IN) ) then - if (RESET_IN = '1') then - nx_fifo_data_input <= (others => '0'); - nx_fifo_write_enable <= '0'; - else - nx_fifo_data_input <= x"deadbeef"; - nx_fifo_write_enable <= '0'; - if (nx_new_frame = '1' and nx_frame_synced = '1') then - nx_fifo_data_input <= nx_frame_word; - nx_fifo_write_enable <= '1'; - end if; - end if; - end if; - end process PROC_WRITE_TO_FIFO; - - fifo_ts_32to32_dc_1: fifo_ts_32to32_dc - port map ( - Data => nx_fifo_data_input, - WrClock => NX_TIMESTAMP_CLK_IN, - RdClock => CLK_IN, - WrEn => nx_fifo_write_enable, - RdEn => nx_fifo_read_enable, - Reset => nx_fifo_reset, - RPReset => nx_fifo_reset, - AmEmptyThresh => nx_fifo_delay_r, - Q => nx_fifo_data, - Empty => nx_fifo_empty, - Full => nx_fifo_full, - AlmostEmpty => nx_fifo_almost_empty - ); - - nx_fifo_reset <= RESET_IN or fifo_reset_r; - --- -- Reset NX_TIMESTAMP_CLK Domain --- PROC_NX_CLK_DOMAIN_RESET: process(CLK_IN) --- begin --- if( rising_edge(CLK_IN) ) then --- if( RESET_IN = '1' ) then --- reset_nx_domain_ctr <= (others => '0'); --- reset_nx_domain <= '1'; --- else --- if (nx_clk_pulse = '1') then --- nx_clk_pulse_ctr <= nx_clk_pulse_ctr + 1; --- end if; --- --- end if; --- --- end if; --- end process PROC_NX_CLK_DOMAIN_RESET; - - PROC_NX_CLK_ACT: process(NX_TIMESTAMP_CLK_IN) - begin - if(rising_edge(NX_TIMESTAMP_CLK_IN)) then - if(RESET_IN = '1' ) then - nx_clk_active_ff_0 <= '0'; - nx_clk_active_ff_1 <= '0'; - nx_clk_active_ff_2 <= '0'; - else - nx_clk_active_ff_0 <= not nx_clk_active_ff_2; - nx_clk_active_ff_1 <= nx_clk_active_ff_0; - nx_clk_active_ff_2 <= nx_clk_active_ff_1; - end if; - end if; - end process PROC_NX_CLK_ACT; - - -- Johnson Counter - PROC_ADC_CLK_GENERATOR: process(NX_TIMESTAMP_CLK_IN) - begin - if(rising_edge(NX_TIMESTAMP_CLK_IN)) then - if (RESET_IN = '1') then - johnson_ff_0 <= '0'; - johnson_ff_1 <= '0'; - else - if (adc_clk_skip = '0') then - johnson_ff_0 <= not johnson_ff_1; - johnson_ff_1 <= johnson_ff_0; - end if; - end if; - end if; - end process PROC_ADC_CLK_GENERATOR; - - PROC_ADC_CLK_DELAY_4NS: process(NX_TIMESTAMP_CLK_IN) - begin - if(falling_edge(NX_TIMESTAMP_CLK_IN)) then - if (RESET_IN = '1') then - adc_clk_inv <= '0'; - else - adc_clk_inv <= johnson_ff_0; - end if; - end if; - end process PROC_ADC_CLK_DELAY_4NS; - - adc_sample_clk <= adc_clk_inv when adc_clk_delay(0) = '1' else johnson_ff_0; - - PROC_ADC_CLK_DELAY: process(NX_TIMESTAMP_CLK_IN) - variable adc_clk_state : std_logic_vector(1 downto 0); - begin - if(rising_edge(NX_TIMESTAMP_CLK_IN)) then - if (RESET_IN = '1') then - adc_clk_skip <= '0'; - else - adc_clk_state := johnson_ff_1 & johnson_ff_0; - adc_clk_skip <= '0'; - - if (nx_new_frame = '1') then - if (adc_clk_state /= adc_clk_delay(2 downto 1)) then - adc_clk_skip <= '1'; - end if; - end if; - end if; - end if; - end process PROC_ADC_CLK_DELAY; - - ----------------------------------------------------------------------------- - -- NX CLK_IN Domain - ----------------------------------------------------------------------------- - - -- FIFO Read Handler - PROC_NX_FIFO_READ_ENABLE: process(CLK_IN) - begin - if( rising_edge(CLK_IN) ) then - if( RESET_IN = '1' or fifo_reset_r = '1') then - nx_fifo_read_enable <= '0'; - nx_read_enable_pause <= '0'; - nx_fifo_data_valid_t <= '0'; - nx_fifo_data_valid <= '0'; - else - if (nx_fifo_almost_empty = '0' and nx_read_enable_pause = '0') then - nx_fifo_read_enable <= '1'; - nx_read_enable_pause <= '1'; - else - nx_fifo_read_enable <= '0'; - nx_read_enable_pause <= '0'; - end if; - - -- Delay read signal by one CLK - nx_fifo_data_valid_t <= nx_fifo_read_enable; - nx_fifo_data_valid <= nx_fifo_data_valid_t; - - end if; - end if; - end process PROC_NX_FIFO_READ_ENABLE; - - PROC_NX_FIFO_READ: process(CLK_IN) - begin - if( rising_edge(CLK_IN) ) then - if (RESET_IN = '1' or fifo_reset_r = '1') then - nx_timestamp_t <= (others => '0'); - nx_new_timestamp <= '0'; - nx_new_timestamp_ctr <= (others => '0'); - else - if (nx_fifo_data_valid = '1') then - nx_timestamp_t <= nx_fifo_data; - nx_new_timestamp <= '1'; - nx_new_timestamp_ctr <= nx_new_timestamp_ctr + 1; - else - nx_timestamp_t <= x"deadbeef"; - nx_new_timestamp <= '0'; - end if; - end if; - end if; - end process PROC_NX_FIFO_READ; - - ----------------------------------------------------------------------------- - -- Status Counters - ----------------------------------------------------------------------------- - - -- Domain Transfers - pulse_sync_1: pulse_sync - port map ( - CLK_A_IN => NX_TIMESTAMP_CLK_IN, - RESET_A_IN => RESET_IN, - PULSE_A_IN => rs_sync_reset, - CLK_B_IN => CLK_IN, - RESET_B_IN => RESET_IN, - PULSE_B_OUT => resync_ctr_inc - ); - - pulse_sync_2: pulse_sync - port map ( - CLK_A_IN => NX_TIMESTAMP_CLK_IN, - RESET_A_IN => RESET_IN, - PULSE_A_IN => parity_error, - CLK_B_IN => CLK_IN, - RESET_B_IN => RESET_IN, - PULSE_B_OUT => parity_error_ctr_inc - ); - - PROC_SYNC_FRAME_SYNC: process(CLK_IN) - begin - if( rising_edge(CLK_IN) ) then - if(RESET_IN = '1' ) then - reg_nx_frame_synced_t <= '0'; - reg_nx_frame_synced <= '0'; - else - reg_nx_frame_synced_t <= nx_frame_synced; - reg_nx_frame_synced <= reg_nx_frame_synced_t; - end if; - end if; - end process PROC_SYNC_FRAME_SYNC; - - -- Counters - PROC_RESYNC_COUNTER: process(CLK_IN) - begin - if( rising_edge(CLK_IN) ) then - if (RESET_IN = '1' or reset_resync_ctr = '1') then - resync_counter <= (others => '0'); - else - if (resync_ctr_inc = '1') then - resync_counter <= resync_counter + 1; - end if; - end if; - end if; - end process PROC_RESYNC_COUNTER; - - PROC_PARITY_ERROR_COUNTER: process(CLK_IN) - begin - if( rising_edge(CLK_IN) ) then - if (RESET_IN = '1' or reset_parity_error_ctr = '1') then - parity_error_counter <= (others => '0'); - else - if (parity_error_ctr_inc = '1') then - parity_error_counter <= parity_error_counter + 1; - end if; - end if; - end if; - end process PROC_PARITY_ERROR_COUNTER; - - - ----------------------------------------------------------------------------- - -- ADC Fifo Handler - ----------------------------------------------------------------------------- - PROC_ADC_DATA_READ: process(CLK_IN) - begin - if( rising_edge(CLK_IN) ) then - if (RESET_IN = '1' or fifo_reset_r = '1') then - adc_data_t <= (others => '0'); - adc_new_data <= '0'; - adc_new_data_ctr <= (others => '0'); - else - if (adc_data_valid = '1') then - adc_data_t <= adc_data; - adc_new_data <= '1'; - adc_new_data_ctr <= adc_new_data_ctr + 1; - else - adc_data_t <= x"aff"; - adc_new_data <= '0'; - end if; - end if; - end if; - end process PROC_ADC_DATA_READ; - - ----------------------------------------------------------------------------- - -- Output handler - ----------------------------------------------------------------------------- - PROC_OUTPUT_HANDLER: process(CLK_IN) - begin - if( rising_edge(CLK_IN) ) then - if (RESET_IN = '1' or fifo_reset_r = '1') then - nx_timestamp_o <= (others => '0'); - adc_data_o <= (others => '0'); - new_data_o <= '0'; - STATE <= IDLE; - else - case STATE is - - when IDLE => - STATE_d <= "00"; - if (nx_new_timestamp = '1' and adc_new_data = '1') then - nx_timestamp_o <= nx_timestamp_t; - adc_data_o <= adc_data_t; - new_data_o <= '1'; - STATE <= IDLE; - elsif (nx_new_timestamp = '1') then - nx_timestamp_o <= nx_timestamp_t; - adc_data_o <= (others => '0'); - new_data_o <= '0'; - STATE <= WAIT_ADC; - elsif (adc_new_data = '1') then - adc_data_o <= adc_data_t; - nx_timestamp_o <= (others => '0'); - new_data_o <= '0'; - STATE <= WAIT_TIMESTAMP; - else - nx_timestamp_o <= (others => '0'); - adc_data_o <= (others => '0'); - new_data_o <= '0'; - STATE <= IDLE; - end if; - - when WAIT_ADC => - STATE_d <= "01"; - if (adc_new_data = '1') then - adc_data_o <= adc_data_t; - new_data_o <= '1'; - STATE <= IDLE; - else - new_data_o <= '0'; - STATE <= WAIT_ADC; - end if; - - when WAIT_TIMESTAMP => - STATE_d <= "10"; - if (nx_new_timestamp = '1') then - nx_timestamp_o <= nx_timestamp_t; - new_data_o <= '1'; - STATE <= IDLE; - else - new_data_o <= '0'; - STATE <= WAIT_TIMESTAMP; - end if; - - end case; - end if; - end if; - end process PROC_OUTPUT_HANDLER; - - ----------------------------------------------------------------------------- - -- TRBNet Slave Bus - ----------------------------------------------------------------------------- - - -- Give status info to the TRB Slow Control Channel - PROC_FIFO_REGISTERS: process(CLK_IN) - begin - if( rising_edge(CLK_IN) ) then - if( RESET_IN = '1' ) then - slv_data_out_o <= (others => '0'); - slv_ack_o <= '0'; - slv_unknown_addr_o <= '0'; - slv_no_more_data_o <= '0'; - reset_resync_ctr <= '0'; - reset_parity_error_ctr <= '0'; - nx_fifo_delay_r <= "01000"; - fifo_reset_r <= '0'; - adc_clk_delay <= "111"; - adc_reset_r <= '0'; - else - slv_data_out_o <= (others => '0'); - slv_ack_o <= '0'; - slv_unknown_addr_o <= '0'; - slv_no_more_data_o <= '0'; - reset_resync_ctr <= '0'; - reset_parity_error_ctr <= '0'; - fifo_reset_r <= '0'; - adc_reset_r <= '0'; - - if (SLV_READ_IN = '1') then - case SLV_ADDR_IN is - when x"0000" => - slv_data_out_o <= nx_timestamp_t; - slv_ack_o <= '1'; - - when x"0001" => - slv_data_out_o(0) <= nx_fifo_full; - slv_data_out_o(1) <= nx_fifo_empty; - slv_data_out_o(2) <= '0'; - slv_data_out_o(3) <= '0'; - slv_data_out_o(4) <= nx_fifo_data_valid; - slv_data_out_o(5) <= adc_new_data; - slv_data_out_o(29 downto 5) <= (others => '0'); - slv_data_out_o(30) <= '0'; - slv_data_out_o(31) <= reg_nx_frame_synced; - slv_ack_o <= '1'; - - when x"0002" => - slv_data_out_o(11 downto 0) <= resync_counter; - slv_data_out_o(31 downto 12) <= (others => '0'); - slv_ack_o <= '1'; - - when x"0003" => - slv_data_out_o(11 downto 0) <= parity_error_counter; - slv_data_out_o(31 downto 12) <= (others => '0'); - slv_ack_o <= '1'; - - when x"0004" => - slv_data_out_o( 4 downto 0) <= nx_fifo_delay_r; - slv_data_out_o(31 downto 5) <= (others => '0'); - slv_ack_o <= '1'; - - when x"0005" => - case adc_clk_delay is - when "010" => slv_data_out_o(2 downto 0) <= "000"; - when "011" => slv_data_out_o(2 downto 0) <= "001"; - when "000" => slv_data_out_o(2 downto 0) <= "010"; - when "001" => slv_data_out_o(2 downto 0) <= "011"; - when "100" => slv_data_out_o(2 downto 0) <= "100"; - when "101" => slv_data_out_o(2 downto 0) <= "101"; - when "110" => slv_data_out_o(2 downto 0) <= "110"; - when "111" => slv_data_out_o(2 downto 0) <= "111"; - end case; - - slv_data_out_o(31 downto 3) <= (others => '0'); - slv_ack_o <= '1'; - - when x"0006" => - slv_data_out_o(11 downto 0) <= adc_data_t; - slv_data_out_o(31 downto 12) <= (others => '0'); - slv_ack_o <= '1'; - - when others => - slv_unknown_addr_o <= '1'; - end case; - - elsif (SLV_WRITE_IN = '1') then - case SLV_ADDR_IN is - when x"0001" => - adc_reset_r <= '1'; - slv_ack_o <= '1'; - - when x"0002" => - reset_resync_ctr <= '1'; - slv_ack_o <= '1'; - - when x"0003" => - reset_parity_error_ctr <= '1'; - slv_ack_o <= '1'; - - when x"0004" => - if (SLV_DATA_IN < x"0000_001c" and - SLV_DATA_IN > x"0000_0001") then - nx_fifo_delay_r <= SLV_DATA_IN(4 downto 0); - fifo_reset_r <= '1'; - end if; - slv_ack_o <= '1'; - - when x"0005" => - if (SLV_DATA_IN < x"0000_0008") then - case SLV_DATA_IN(2 downto 0) is - when "000" => adc_clk_delay <= "010"; - when "001" => adc_clk_delay <= "011"; - when "010" => adc_clk_delay <= "000"; - when "011" => adc_clk_delay <= "001"; - when "100" => adc_clk_delay <= "100"; - when "101" => adc_clk_delay <= "101"; - when "110" => adc_clk_delay <= "110"; - when "111" => adc_clk_delay <= "111"; - end case; - adc_reset_r <= '1'; - end if; - slv_ack_o <= '1'; - - when others => - slv_unknown_addr_o <= '1'; - end case; - end if; - end if; - end if; - end process PROC_FIFO_REGISTERS; - - -- Output Signals - - NX_TIMESTAMP_OUT <= nx_timestamp_o; - ADC_DATA_OUT <= adc_data_o; - NEW_DATA_OUT <= new_data_o; - - SLV_DATA_OUT <= slv_data_out_o; - SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; - SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o; - SLV_ACK_OUT <= slv_ack_o; - -end Behavioral; +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.nxyter_components.all; + +entity nx_data_receiver is + port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + TRIGGER_IN : in std_logic; + + -- nXyter Ports + NX_TIMESTAMP_CLK_IN : in std_logic; + NX_TIMESTAMP_IN : in std_logic_vector (7 downto 0); + + -- ADC Ports + ADC_CLK_DAT_IN : in std_logic; + ADC_FCLK_IN : in std_logic_vector(1 downto 0); + ADC_DCLK_IN : in std_logic_vector(1 downto 0); + ADC_SAMPLE_CLK_OUT : out std_logic; + ADC_A_IN : in std_logic_vector(1 downto 0); + ADC_B_IN : in std_logic_vector(1 downto 0); + ADC_NX_IN : in std_logic_vector(1 downto 0); + ADC_D_IN : in std_logic_vector(1 downto 0); + + -- Outputs + NX_TIMESTAMP_OUT : out std_logic_vector(31 downto 0); + ADC_DATA_OUT : out std_logic_vector(11 downto 0); + NEW_DATA_OUT : out std_logic; + + TIMESTAMP_CURRENT_IN : in unsigned(11 downto 0); + + -- Slave bus + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ADDR_IN : in std_logic_vector(15 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic; + + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); +end entity; + +architecture Behavioral of nx_data_receiver is + + ----------------------------------------------------------------------------- + -- NX_TIMESTAMP_CLK Domain + ----------------------------------------------------------------------------- + + -- FIFO DC Input Handler + signal nx_timestamp_reg_t : std_logic_vector(7 downto 0); + signal nx_timestamp_reg : std_logic_vector(7 downto 0); + signal nx_fifo_full : std_logic; + signal nx_fifo_reset : std_logic; + + -- NX_TIMESTAMP_IN Process + signal frame_byte_ctr : unsigned(1 downto 0); + signal nx_frame_word : std_logic_vector(31 downto 0); + signal nx_new_frame : std_logic; + + -- Frame Sync Process + signal frame_byte_pos : unsigned(1 downto 0); + + -- RS Sync FlipFlop + signal nx_frame_synced : std_logic; + signal rs_sync_set : std_logic; + signal rs_sync_reset : std_logic; + + -- Parity Check + signal parity_error : std_logic; + + -- Write to FIFO Handler + signal nx_fifo_data_input : std_logic_vector(31 downto 0); + signal nx_fifo_write_enable : std_logic; + + -- NX Clock Active + signal nx_clk_active_ff_0 : std_logic; + signal nx_clk_active_ff_1 : std_logic; + signal nx_clk_active_ff_2 : std_logic; + + -- ADC Ckl Generator + signal adc_clk_skip : std_logic; + signal adc_sample_clk : std_logic; + signal johnson_ff_0 : std_logic; + signal johnson_ff_1 : std_logic; + signal adc_clk_inv : std_logic; + signal adc_clk_delay : std_logic_vector(2 downto 0); + + ----------------------------------------------------------------------------- + -- CLK_IN Domain + ----------------------------------------------------------------------------- + + -- NX FIFO READ ENABLE + signal nx_fifo_read_enable : std_logic; + signal nx_fifo_empty : std_logic; + signal nx_read_enable : std_logic; + signal nx_fifo_data_valid_t : std_logic; + signal nx_fifo_data_valid : std_logic; + + signal nx_fifo_delay_r : std_logic_vector(2 downto 0); + + -- NX FIFO READ + signal nx_timestamp_t : std_logic_vector(31 downto 0); + signal nx_new_timestamp : std_logic; + signal nx_new_timestamp_ctr : unsigned(3 downto 0); + signal nx_fifo_data : std_logic_vector(31 downto 0); + + -- Resync Counter Process + signal resync_counter : unsigned(11 downto 0); + signal resync_ctr_inc : std_logic; + signal nx_clk_active : std_logic; + + -- Parity Error Counter Process + signal parity_error_counter : unsigned(11 downto 0); + signal parity_error_ctr_inc : std_logic; + + signal reg_nx_frame_synced_t : std_logic; + signal reg_nx_frame_synced : std_logic; + + ----------------------------------------------------------------------------- + -- ADC Data Handler + ----------------------------------------------------------------------------- + + -- ADC Handler + signal adc_reset_r : std_logic; + signal adc_reset_l : std_logic; + signal adc_reset : std_logic; + + signal adc_data : std_logic_vector(11 downto 0); + signal test_adc_data : std_logic_vector(11 downto 0); + signal adc_data_valid : std_logic; + + signal adc_data_t : std_logic_vector(11 downto 0); + signal adc_new_data : std_logic; + signal adc_new_data_ctr : unsigned(3 downto 0); + + -- Data Output Handler + type STATES is (IDLE, + WAIT_ADC, + WAIT_TIMESTAMP + ); + signal STATE : STATES; + signal STATE_d : std_logic_vector(1 downto 0); + + signal nx_timestamp_o : std_logic_vector(31 downto 0); + signal adc_data_o : std_logic_vector(11 downto 0); + signal new_data_o : std_logic; + + -- Slave Bus + signal slv_data_out_o : std_logic_vector(31 downto 0); + signal slv_no_more_data_o : std_logic; + signal slv_unknown_addr_o : std_logic; + signal slv_ack_o : std_logic; + + signal reset_resync_ctr : std_logic; + signal reset_parity_error_ctr : std_logic; + signal fifo_reset_r : std_logic; + signal debug_adc : std_logic_vector(1 downto 0); + +begin + + DEBUG_OUT(0) <= CLK_IN; + DEBUG_OUT(1) <= NX_TIMESTAMP_CLK_IN; + DEBUG_OUT(2) <= TRIGGER_IN; --nx_fifo_reset; + + PROC_DEBUG_MULT: process(adc_data_valid, + test_adc_data) + begin + case debug_adc is + when "01" => + DEBUG_OUT(15 downto 4) <= adc_data; + DEBUG_OUT(3) <= adc_data_valid; + + when "10" => + DEBUG_OUT(15 downto 4) <= test_adc_data; + DEBUG_OUT(3) <= adc_data_valid; + + when others => + DEBUG_OUT(3) <= nx_fifo_full; + DEBUG_OUT(4) <= nx_fifo_write_enable; + DEBUG_OUT(5) <= nx_fifo_empty; + DEBUG_OUT(6) <= nx_fifo_read_enable; + DEBUG_OUT(7) <= nx_fifo_data_valid; + + DEBUG_OUT(8) <= adc_data_valid; + + DEBUG_OUT(9) <= nx_new_timestamp; + DEBUG_OUT(10) <= adc_new_data; + DEBUG_OUT(12 downto 11) <= STATE_d; + DEBUG_OUT(13) <= new_data_o; + + DEBUG_OUT(14) <= nx_frame_synced; + DEBUG_OUT(15) <= rs_sync_reset; + end case; + + end process PROC_DEBUG_MULT; + + ----------------------------------------------------------------------------- + -- ADC CLK DOMAIN + ----------------------------------------------------------------------------- + + adc_ad9222_1: entity work.adc_ad9222 + generic map ( + CHANNELS => 4, + DEVICES => 2, + RESOLUTION => 12 + ) + port map ( + CLK => CLK_IN, + CLK_ADCREF => adc_sample_clk, + CLK_ADCDAT => ADC_CLK_DAT_IN, + RESTART_IN => adc_reset, + ADCCLK_OUT => ADC_SAMPLE_CLK_OUT, + + ADC_DATA(0) => ADC_NX_IN(0), + ADC_DATA(1) => ADC_B_IN(0), + ADC_DATA(2) => ADC_A_IN(0), + ADC_DATA(3) => ADC_D_IN(0), + + ADC_DATA(4) => ADC_NX_IN(1), + ADC_DATA(5) => ADC_A_IN(1), + ADC_DATA(6) => ADC_B_IN(1), + ADC_DATA(7) => ADC_D_IN(1), + + ADC_DCO => ADC_DCLK_IN, + ADC_FCO => ADC_FCLK_IN, + + DATA_OUT(11 downto 0) => adc_data, + DATA_OUT(23 downto 12) => test_adc_data, + DATA_OUT(95 downto 24) => open, + + FCO_OUT => open, + DATA_VALID_OUT(0) => adc_data_valid, + DATA_VALID_OUT(1) => open, + DEBUG => open + ); + + adc_reset <= adc_reset_l or RESET_IN; + + pulse_to_level_1: pulse_to_level + generic map ( + NUM_CYCLES => "10000" + ) + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + PULSE_IN => adc_reset_r, + LEVEL_OUT => adc_reset_l + ); + + ----------------------------------------------------------------------------- + -- NX_TIMESTAMP_CLK_IN Domain + ----------------------------------------------------------------------------- + + nx_timestamp_reg <= NX_TIMESTAMP_IN when rising_edge(NX_TIMESTAMP_CLK_IN); + + -- Transfer 8 to 32Bit + PROC_8_TO_32_BIT: process(NX_TIMESTAMP_CLK_IN) + begin + if( rising_edge(NX_TIMESTAMP_CLK_IN) ) then + if( RESET_IN = '1' ) then + frame_byte_ctr <= (others => '0'); + nx_frame_word <= (others => '0'); + nx_new_frame <= '0'; + else + nx_new_frame <= '0'; + + case frame_byte_pos is + when "11" => nx_frame_word(31 downto 24) <= nx_timestamp_reg; + frame_byte_ctr <= frame_byte_ctr + 1; + + when "10" => nx_frame_word(23 downto 16) <= nx_timestamp_reg; + frame_byte_ctr <= frame_byte_ctr + 1; + + when "01" => nx_frame_word(15 downto 8) <= nx_timestamp_reg; + frame_byte_ctr <= frame_byte_ctr + 1; + + when "00" => nx_frame_word( 7 downto 0) <= nx_timestamp_reg; + if (frame_byte_ctr = "11") then + nx_new_frame <= '1'; + end if; + frame_byte_ctr <= (others => '0'); + end case; + end if; + end if; + end process PROC_8_TO_32_BIT; + + -- Frame Sync process + PROC_SYNC_TO_NX_FRAME: process(NX_TIMESTAMP_CLK_IN) + begin + if( rising_edge(NX_TIMESTAMP_CLK_IN) ) then + if( RESET_IN = '1' ) then + frame_byte_pos <= "11"; + rs_sync_set <= '0'; + rs_sync_reset <= '0'; + else + rs_sync_set <= '0'; + rs_sync_reset <= '0'; + if (nx_new_frame = '1') then + case nx_frame_word is + when x"7f7f7f06" => + rs_sync_set <= '1'; + frame_byte_pos <= frame_byte_pos - 1; + + when x"7f7f067f" => + rs_sync_reset <= '1'; + frame_byte_pos <= frame_byte_pos - 2; + + when x"7f067f7f" => + rs_sync_reset <= '1'; + frame_byte_pos <= frame_byte_pos - 3; + + when x"067f7f7f" => + rs_sync_reset <= '1'; + frame_byte_pos <= frame_byte_pos - 4; + + when others => + frame_byte_pos <= frame_byte_pos - 1; + end case; + else + frame_byte_pos <= frame_byte_pos - 1; + end if; + end if; + end if; + end process PROC_SYNC_TO_NX_FRAME; + + -- RS FlipFlop to hold Sync Status + PROC_RS_FRAME_SYNCED: process(NX_TIMESTAMP_CLK_IN) + begin + if( rising_edge(NX_TIMESTAMP_CLK_IN) ) then + if (RESET_IN = '1' or rs_sync_reset = '1') then + nx_frame_synced <= '0'; + elsif (rs_sync_set = '1') then + nx_frame_synced <= '1'; + end if; + end if; + end process PROC_RS_FRAME_SYNCED; + + -- Check Parity + PROC_PARITY_CHECK: process(NX_TIMESTAMP_CLK_IN) + variable parity_bits : std_logic_vector(22 downto 0); + variable parity : std_logic; + begin + if( rising_edge(NX_TIMESTAMP_CLK_IN) ) then + if (RESET_IN = '1') then + parity_error <= '0'; + else + parity_error <= '0'; + if (nx_new_frame = '1' and nx_frame_synced = '1') then + -- Timestamp Bit #6 is excluded (funny nxyter-bug) + parity_bits := nx_frame_word(31) & + nx_frame_word(30 downto 24) & + nx_frame_word(21 downto 16) & + nx_frame_word(14 downto 8) & + nx_frame_word( 2 downto 1); + parity := xor_all(parity_bits); + + if (parity /= nx_frame_word(0)) then + parity_error <= '1'; + end if; + end if; + end if; + end if; + end process PROC_PARITY_CHECK; + + -- Write to FIFO + PROC_WRITE_TO_FIFO: process(NX_TIMESTAMP_CLK_IN) + begin + if( rising_edge(NX_TIMESTAMP_CLK_IN) ) then + if (RESET_IN = '1') then + nx_fifo_data_input <= (others => '0'); + nx_fifo_write_enable <= '0'; + else + nx_fifo_data_input <= x"deadbeef"; + nx_fifo_write_enable <= '0'; + if (nx_new_frame = '1' and + nx_frame_synced = '1' and + nx_fifo_full = '0') then + nx_fifo_data_input <= nx_frame_word; + nx_fifo_write_enable <= '1'; + end if; + end if; + end if; + end process PROC_WRITE_TO_FIFO; + + fifo_ts_32to32_dc_1: fifo_ts_32to32_dc + port map ( + Data => nx_fifo_data_input, + WrClock => NX_TIMESTAMP_CLK_IN, + RdClock => CLK_IN, + WrEn => nx_fifo_write_enable, + RdEn => nx_fifo_read_enable, + Reset => nx_fifo_reset, + RPReset => nx_fifo_reset, + Q => nx_fifo_data, + Empty => nx_fifo_empty, + Full => nx_fifo_full + ); + + nx_fifo_reset <= RESET_IN or fifo_reset_r; + +-- -- Reset NX_TIMESTAMP_CLK Domain +-- PROC_NX_CLK_DOMAIN_RESET: process(CLK_IN) +-- begin +-- if( rising_edge(CLK_IN) ) then +-- if( RESET_IN = '1' ) then +-- reset_nx_domain_ctr <= (others => '0'); +-- reset_nx_domain <= '1'; +-- else +-- if (nx_clk_pulse = '1') then +-- nx_clk_pulse_ctr <= nx_clk_pulse_ctr + 1; +-- end if; +-- +-- end if; +-- +-- end if; +-- end process PROC_NX_CLK_DOMAIN_RESET; + + PROC_NX_CLK_ACT: process(NX_TIMESTAMP_CLK_IN) + begin + if(rising_edge(NX_TIMESTAMP_CLK_IN)) then + if(RESET_IN = '1' ) then + nx_clk_active_ff_0 <= '0'; + nx_clk_active_ff_1 <= '0'; + nx_clk_active_ff_2 <= '0'; + else + nx_clk_active_ff_0 <= not nx_clk_active_ff_2; + nx_clk_active_ff_1 <= nx_clk_active_ff_0; + nx_clk_active_ff_2 <= nx_clk_active_ff_1; + end if; + end if; + end process PROC_NX_CLK_ACT; + + -- Johnson Counter + PROC_ADC_CLK_GENERATOR: process(NX_TIMESTAMP_CLK_IN) + begin + if(rising_edge(NX_TIMESTAMP_CLK_IN)) then + if (RESET_IN = '1') then + johnson_ff_0 <= '0'; + johnson_ff_1 <= '0'; + else + if (adc_clk_skip = '0') then + johnson_ff_0 <= not johnson_ff_1; + johnson_ff_1 <= johnson_ff_0; + end if; + end if; + end if; + end process PROC_ADC_CLK_GENERATOR; + + PROC_ADC_CLK_DELAY_4NS: process(NX_TIMESTAMP_CLK_IN) + begin + if(falling_edge(NX_TIMESTAMP_CLK_IN)) then + if (RESET_IN = '1') then + adc_clk_inv <= '0'; + else + adc_clk_inv <= johnson_ff_0; + end if; + end if; + end process PROC_ADC_CLK_DELAY_4NS; + + adc_sample_clk <= adc_clk_inv when adc_clk_delay(0) = '1' else johnson_ff_0; + + PROC_ADC_CLK_DELAY: process(NX_TIMESTAMP_CLK_IN) + variable adc_clk_state : std_logic_vector(1 downto 0); + begin + if(rising_edge(NX_TIMESTAMP_CLK_IN)) then + if (RESET_IN = '1') then + adc_clk_skip <= '0'; + else + adc_clk_state := johnson_ff_1 & johnson_ff_0; + adc_clk_skip <= '0'; + + if (nx_new_frame = '1') then + if (adc_clk_state /= adc_clk_delay(2 downto 1)) then + adc_clk_skip <= '1'; + end if; + end if; + end if; + end if; + end process PROC_ADC_CLK_DELAY; + + ----------------------------------------------------------------------------- + -- NX CLK_IN Domain + ----------------------------------------------------------------------------- + + -- FIFO Read Handler + nx_fifo_read_enable <= not nx_fifo_empty; + + PROC_NX_FIFO_READ_ENABLE: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' or fifo_reset_r = '1') then + nx_fifo_data_valid_t <= '0'; + nx_fifo_data_valid <= '0'; + else + -- Delay read signal by one CLK + nx_fifo_data_valid_t <= nx_fifo_read_enable; + nx_fifo_data_valid <= nx_fifo_data_valid_t; + end if; + end if; + end process PROC_NX_FIFO_READ_ENABLE; + + PROC_NX_FIFO_READ: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if (RESET_IN = '1' or fifo_reset_r = '1') then + nx_timestamp_t <= (others => '0'); + nx_new_timestamp <= '0'; + nx_new_timestamp_ctr <= (others => '0'); + else + if (nx_fifo_data_valid = '1') then + nx_timestamp_t <= nx_fifo_data; + nx_new_timestamp <= '1'; + nx_new_timestamp_ctr <= nx_new_timestamp_ctr + 1; + else + nx_timestamp_t <= x"deadbeef"; + nx_new_timestamp <= '0'; + end if; + end if; + end if; + end process PROC_NX_FIFO_READ; + + ----------------------------------------------------------------------------- + -- Status Counters + ----------------------------------------------------------------------------- + + -- Domain Transfers + pulse_sync_1: pulse_sync + port map ( + CLK_A_IN => NX_TIMESTAMP_CLK_IN, + RESET_A_IN => RESET_IN, + PULSE_A_IN => rs_sync_reset, + CLK_B_IN => CLK_IN, + RESET_B_IN => RESET_IN, + PULSE_B_OUT => resync_ctr_inc + ); + + pulse_sync_2: pulse_sync + port map ( + CLK_A_IN => NX_TIMESTAMP_CLK_IN, + RESET_A_IN => RESET_IN, + PULSE_A_IN => parity_error, + CLK_B_IN => CLK_IN, + RESET_B_IN => RESET_IN, + PULSE_B_OUT => parity_error_ctr_inc + ); + + PROC_SYNC_FRAME_SYNC: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if(RESET_IN = '1' ) then + reg_nx_frame_synced_t <= '0'; + reg_nx_frame_synced <= '0'; + else + reg_nx_frame_synced_t <= nx_frame_synced; + reg_nx_frame_synced <= reg_nx_frame_synced_t; + end if; + end if; + end process PROC_SYNC_FRAME_SYNC; + + -- Counters + PROC_RESYNC_COUNTER: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if (RESET_IN = '1' or reset_resync_ctr = '1') then + resync_counter <= (others => '0'); + else + if (resync_ctr_inc = '1') then + resync_counter <= resync_counter + 1; + end if; + end if; + end if; + end process PROC_RESYNC_COUNTER; + + PROC_PARITY_ERROR_COUNTER: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if (RESET_IN = '1' or reset_parity_error_ctr = '1') then + parity_error_counter <= (others => '0'); + else + if (parity_error_ctr_inc = '1') then + parity_error_counter <= parity_error_counter + 1; + end if; + end if; + end if; + end process PROC_PARITY_ERROR_COUNTER; + + + ----------------------------------------------------------------------------- + -- ADC Fifo Handler + ----------------------------------------------------------------------------- + PROC_ADC_DATA_READ: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if (RESET_IN = '1' or fifo_reset_r = '1') then + adc_data_t <= (others => '0'); + adc_new_data <= '0'; + adc_new_data_ctr <= (others => '0'); + else + if (adc_data_valid = '1') then + adc_data_t <= adc_data; + adc_new_data <= '1'; + adc_new_data_ctr <= adc_new_data_ctr + 1; + else + adc_data_t <= x"aff"; + adc_new_data <= '0'; + end if; + end if; + end if; + end process PROC_ADC_DATA_READ; + + ----------------------------------------------------------------------------- + -- Output handler + ----------------------------------------------------------------------------- + PROC_OUTPUT_HANDLER: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if (RESET_IN = '1' or fifo_reset_r = '1') then + nx_timestamp_o <= (others => '0'); + adc_data_o <= (others => '0'); + new_data_o <= '0'; + STATE <= IDLE; + else + case STATE is + + when IDLE => + STATE_d <= "00"; + if (nx_new_timestamp = '1' and adc_new_data = '1') then + nx_timestamp_o <= nx_timestamp_t; + adc_data_o <= adc_data_t; + new_data_o <= '1'; + STATE <= IDLE; + elsif (nx_new_timestamp = '1') then + nx_timestamp_o <= nx_timestamp_t; + adc_data_o <= (others => '0'); + new_data_o <= '0'; + STATE <= WAIT_ADC; + elsif (adc_new_data = '1') then + adc_data_o <= adc_data_t; + nx_timestamp_o <= (others => '0'); + new_data_o <= '0'; + STATE <= WAIT_TIMESTAMP; + else + nx_timestamp_o <= (others => '0'); + adc_data_o <= (others => '0'); + new_data_o <= '0'; + STATE <= IDLE; + end if; + + when WAIT_ADC => + STATE_d <= "01"; + if (adc_new_data = '1') then + adc_data_o <= adc_data_t; + new_data_o <= '1'; + STATE <= IDLE; + else + new_data_o <= '0'; + STATE <= WAIT_ADC; + end if; + + when WAIT_TIMESTAMP => + STATE_d <= "10"; + if (nx_new_timestamp = '1') then + nx_timestamp_o <= nx_timestamp_t; + new_data_o <= '1'; + STATE <= IDLE; + else + new_data_o <= '0'; + STATE <= WAIT_TIMESTAMP; + end if; + + end case; + end if; + end if; + end process PROC_OUTPUT_HANDLER; + + ----------------------------------------------------------------------------- + -- TRBNet Slave Bus + ----------------------------------------------------------------------------- + + -- Give status info to the TRB Slow Control Channel + PROC_FIFO_REGISTERS: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + slv_data_out_o <= (others => '0'); + slv_ack_o <= '0'; + slv_unknown_addr_o <= '0'; + slv_no_more_data_o <= '0'; + reset_resync_ctr <= '0'; + reset_parity_error_ctr <= '0'; + nx_fifo_delay_r <= "100"; + fifo_reset_r <= '0'; + adc_clk_delay <= "111"; + adc_reset_r <= '0'; + debug_adc <= (others => '0'); + else + slv_data_out_o <= (others => '0'); + slv_ack_o <= '0'; + slv_unknown_addr_o <= '0'; + slv_no_more_data_o <= '0'; + reset_resync_ctr <= '0'; + reset_parity_error_ctr <= '0'; + fifo_reset_r <= '0'; + adc_reset_r <= '0'; + + if (SLV_READ_IN = '1') then + case SLV_ADDR_IN is + when x"0000" => + slv_data_out_o <= nx_timestamp_t; + slv_ack_o <= '1'; + + when x"0001" => + slv_data_out_o(0) <= nx_fifo_full; + slv_data_out_o(1) <= nx_fifo_empty; + slv_data_out_o(2) <= '0'; + slv_data_out_o(3) <= '0'; + slv_data_out_o(4) <= nx_fifo_data_valid; + slv_data_out_o(5) <= adc_new_data; + slv_data_out_o(29 downto 5) <= (others => '0'); + slv_data_out_o(30) <= '0'; + slv_data_out_o(31) <= reg_nx_frame_synced; + slv_ack_o <= '1'; + + when x"0002" => + slv_data_out_o(11 downto 0) <= resync_counter; + slv_data_out_o(31 downto 12) <= (others => '0'); + slv_ack_o <= '1'; + + when x"0003" => + slv_data_out_o(11 downto 0) <= parity_error_counter; + slv_data_out_o(31 downto 12) <= (others => '0'); + slv_ack_o <= '1'; + + when x"0004" => + slv_data_out_o( 2 downto 0) <= nx_fifo_delay_r; + slv_data_out_o(31 downto 3) <= (others => '0'); + slv_ack_o <= '1'; + + when x"0005" => + case adc_clk_delay is + when "010" => slv_data_out_o(2 downto 0) <= "000"; + when "011" => slv_data_out_o(2 downto 0) <= "001"; + when "000" => slv_data_out_o(2 downto 0) <= "010"; + when "001" => slv_data_out_o(2 downto 0) <= "011"; + when "100" => slv_data_out_o(2 downto 0) <= "100"; + when "101" => slv_data_out_o(2 downto 0) <= "101"; + when "110" => slv_data_out_o(2 downto 0) <= "110"; + when "111" => slv_data_out_o(2 downto 0) <= "111"; + end case; + + slv_data_out_o(31 downto 3) <= (others => '0'); + slv_ack_o <= '1'; + + when x"0006" => + slv_data_out_o(1 downto 0) <= debug_adc; + slv_data_out_o(31 downto 2) <= (others => '0'); + slv_ack_o <= '1'; + + when x"0007" => + slv_data_out_o(11 downto 0) <= adc_data_t; + slv_data_out_o(31 downto 12) <= (others => '0'); + slv_ack_o <= '1'; + + when others => + slv_unknown_addr_o <= '1'; + end case; + + elsif (SLV_WRITE_IN = '1') then + case SLV_ADDR_IN is + when x"0001" => + adc_reset_r <= '1'; + slv_ack_o <= '1'; + + when x"0002" => + reset_resync_ctr <= '1'; + slv_ack_o <= '1'; + + when x"0003" => + reset_parity_error_ctr <= '1'; + slv_ack_o <= '1'; + + when x"0004" => + nx_fifo_delay_r <= SLV_DATA_IN(2 downto 0); + fifo_reset_r <= '1'; + slv_ack_o <= '1'; + + when x"0005" => + if (SLV_DATA_IN < x"0000_0008") then + case SLV_DATA_IN(2 downto 0) is + when "000" => adc_clk_delay <= "010"; + when "001" => adc_clk_delay <= "011"; + when "010" => adc_clk_delay <= "000"; + when "011" => adc_clk_delay <= "001"; + when "100" => adc_clk_delay <= "100"; + when "101" => adc_clk_delay <= "101"; + when "110" => adc_clk_delay <= "110"; + when "111" => adc_clk_delay <= "111"; + end case; + adc_reset_r <= '1'; + end if; + slv_ack_o <= '1'; + + when x"0006" => + debug_adc <= SLV_DATA_IN(1 downto 0); + slv_ack_o <= '1'; + + when others => + slv_unknown_addr_o <= '1'; + end case; + end if; + end if; + end if; + end process PROC_FIFO_REGISTERS; + + -- Output Signals + + NX_TIMESTAMP_OUT <= nx_timestamp_o; + ADC_DATA_OUT <= adc_data_o; + NEW_DATA_OUT <= new_data_o; + + SLV_DATA_OUT <= slv_data_out_o; + SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; + SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o; + SLV_ACK_OUT <= slv_ack_o; + +end Behavioral; diff --git a/nxyter/source/nx_data_validate.vhd b/nxyter/source/nx_data_validate.vhd index 9c52243..ff68963 100644 --- a/nxyter/source/nx_data_validate.vhd +++ b/nxyter/source/nx_data_validate.vhd @@ -1,374 +1,406 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.trb_net_std.all; -use work.nxyter_components.all; - -entity nx_data_validate is - port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - - -- Inputs - NX_TIMESTAMP_IN : in std_logic_vector(31 downto 0); - ADC_DATA_IN : in std_logic_vector(11 downto 0); - NEW_DATA_IN : in std_logic; - - -- Outputs - TIMESTAMP_OUT : out std_logic_vector(13 downto 0); - CHANNEL_OUT : out std_logic_vector(6 downto 0); - TIMESTAMP_STATUS_OUT : out std_logic_vector(2 downto 0); - ADC_DATA_OUT : out std_logic_vector(11 downto 0); - DATA_VALID_OUT : out std_logic; - - NX_TOKEN_RETURN_OUT : out std_logic; - NX_NOMORE_DATA_OUT : out std_logic; - - -- Slave bus - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_ADDR_IN : in std_logic_vector(15 downto 0); - SLV_ACK_OUT : out std_logic; - SLV_NO_MORE_DATA_OUT : out std_logic; - SLV_UNKNOWN_ADDR_OUT : out std_logic; - - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); - -end entity; - -architecture Behavioral of nx_data_validate is - - -- Gray Decoder - signal nx_timestamp : std_logic_vector(13 downto 0); - signal nx_channel_id : std_logic_vector( 6 downto 0); - - -- TIMESTAMP_BITS - signal new_timestamp : std_logic; - signal valid_frame_bits : std_logic_vector(3 downto 0); - signal status_bits : std_logic_vector(1 downto 0); - signal parity_bit : std_logic; - signal parity : std_logic; - signal adc_data : std_logic_vector(11 downto 0); - - -- Validate Timestamp - signal timestamp_o : std_logic_vector(13 downto 0); - signal channel_o : std_logic_vector(6 downto 0); - signal timestamp_status_o : std_logic_vector(2 downto 0); - signal adc_data_o : std_logic_vector(11 downto 0); - signal data_valid_o : std_logic; - - signal nx_token_return_o : std_logic; - signal nx_nomore_data_o : std_logic; - - signal invalid_frame_ctr : unsigned(15 downto 0); - signal overflow_ctr : unsigned(15 downto 0); - signal pileup_ctr : unsigned(15 downto 0); - signal parity_error_ctr : unsigned(15 downto 0); - signal nx_valid_ctr : unsigned(19 downto 0); - signal nx_rate_timer : unsigned(19 downto 0); - - -- Config - signal readout_type : std_logic_vector(1 downto 0); - - -- Slave Bus - signal slv_data_out_o : std_logic_vector(31 downto 0); - signal slv_no_more_data_o : std_logic; - signal slv_unknown_addr_o : std_logic; - signal slv_ack_o : std_logic; - signal clear_counters : std_logic; - signal nx_trigger_rate : unsigned(19 downto 0); - - signal invalid_adc : std_logic; - -begin - - -- Debug Line - DEBUG_OUT(0) <= CLK_IN; - DEBUG_OUT(1) <= nx_token_return_o; - DEBUG_OUT(2) <= nx_nomore_data_o; - DEBUG_OUT(3) <= data_valid_o; - DEBUG_OUT(4) <= new_timestamp; - DEBUG_OUT(8 downto 5) <= (others => '0'); - DEBUG_OUT(15 downto 9) <= channel_o; - --DEBUG_OUT(6 downto 4) <= timestamp_status_o; - --DEBUG_OUT(7) <= nx_token_return_o; - --DEBUG_OUT(8) <= invalid_adc;--nx_nomore_data_o; - - --DEBUG_OUT(15 downto 9) <= channel_o; - - ----------------------------------------------------------------------------- - -- Gray Decoder for Timestamp and Channel Id - ----------------------------------------------------------------------------- - - Gray_Decoder_1: Gray_Decoder -- Decode nx_timestamp - generic map ( - WIDTH => 14 - ) - port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - GRAY_IN(13 downto 7) => not NX_TIMESTAMP_IN(30 downto 24), - GRAY_IN( 6 downto 0) => not NX_TIMESTAMP_IN(22 downto 16), - BINARY_OUT => nx_timestamp - ); - - Gray_Decoder_2: Gray_Decoder -- Decode Channel_ID - generic map ( - WIDTH => 7 - ) - port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - GRAY_IN => NX_TIMESTAMP_IN(14 downto 8), - BINARY_OUT => nx_channel_id - ); - - -- Separate Status-, Parity- and Frame-bits, calculate parity - PROC_TIMESTAMP_BITS: process (CLK_IN) - variable parity_bits : std_logic_vector(22 downto 0); - begin - if( rising_edge(CLK_IN) ) then - if (RESET_IN = '1') then - valid_frame_bits <= (others => '0'); - status_bits <= (others => '0'); - parity_bit <= '0'; - parity <= '0'; - new_timestamp <= '0'; - adc_data <= (others => '0'); - else - -- Timestamp Bit #6 is excluded (funny nxyter-bug) - parity_bits := NX_TIMESTAMP_IN(31 downto 24) & - NX_TIMESTAMP_IN(21 downto 16) & - NX_TIMESTAMP_IN(14 downto 8) & - NX_TIMESTAMP_IN( 2 downto 1); - valid_frame_bits <= (others => '0'); - status_bits <= (others => '0'); - parity_bit <= '0'; - parity <= '0'; - new_timestamp <= '0'; - adc_data <= (others => '0'); - - if (NEW_DATA_IN = '1') then - valid_frame_bits(3) <= NX_TIMESTAMP_IN(31); - valid_frame_bits(2) <= NX_TIMESTAMP_IN(23); - valid_frame_bits(1) <= NX_TIMESTAMP_IN(15); - valid_frame_bits(0) <= NX_TIMESTAMP_IN(7); - status_bits <= NX_TIMESTAMP_IN(2 downto 1); - parity_bit <= NX_TIMESTAMP_IN(0); - parity <= xor_all(parity_bits); - adc_data <= ADC_DATA_IN; - new_timestamp <= '1'; - end if; - end if; - end if; - end process PROC_TIMESTAMP_BITS; - - ----------------------------------------------------------------------------- - -- Filter only valid events - ----------------------------------------------------------------------------- - - PROC_VALIDATE_TIMESTAMP: process (CLK_IN) - begin - if( rising_edge(CLK_IN) ) then - if (RESET_IN = '1') then - timestamp_o <= (others => '0'); - channel_o <= (others => '0'); - timestamp_status_o <= (others => '0'); - adc_data_o <= (others => '0'); - data_valid_o <= '0'; - nx_token_return_o <= '0'; - nx_nomore_data_o <= '0'; - - invalid_frame_ctr <= (others => '0'); - overflow_ctr <= (others => '0'); - pileup_ctr <= (others => '0'); - parity_error_ctr <= (others => '0'); - nx_valid_ctr <= (others => '0'); - nx_trigger_rate <= (others => '0'); - nx_rate_timer <= (others => '0'); - else - timestamp_o <= (others => '0'); - channel_o <= (others => '0'); - timestamp_status_o <= (others => '0'); - adc_data_o <= (others => '0'); - data_valid_o <= '0'; - - invalid_adc <= '0'; - - if (new_timestamp = '1') then - case valid_frame_bits is - - -- Data Frame - when "1000" => - ---- Check Overflow - if ((status_bits(0) = '1') and (clear_counters = '0')) then - overflow_ctr <= overflow_ctr + 1; - end if; - - ---- Check Parity - if ((parity_bit /= parity) and (clear_counters = '0')) then - timestamp_status_o(0) <= '1'; - parity_error_ctr <= parity_error_ctr + 1; - end if; - - -- Check PileUp - if ((status_bits(1) = '1') and (clear_counters = '0')) then - pileup_ctr <= pileup_ctr + 1; - end if; - - -- Take Timestamp - timestamp_o <= nx_timestamp; - channel_o <= nx_channel_id; - timestamp_status_o(2 downto 1) <= status_bits; - adc_data_o <= adc_data; - data_valid_o <= '1'; - - -- Rate Counter - if (nx_rate_timer < x"186a0") then - nx_valid_ctr <= nx_valid_ctr + 1; - end if; - - if (adc_data = x"aff") then - invalid_adc <= '1'; - end if; - - nx_token_return_o <= '0'; - nx_nomore_data_o <= '0'; - - -- Token return and nomore_data - when "0000" => - nx_token_return_o <= '1'; - nx_nomore_data_o <= nx_token_return_o; - - when others => - -- Invalid frame, not empty, discard timestamp - if (clear_counters = '0') then - invalid_frame_ctr <= invalid_frame_ctr + 1; - end if; - nx_token_return_o <= '0'; - nx_nomore_data_o <= '0'; - - end case; - else - nx_token_return_o <= nx_token_return_o; - nx_nomore_data_o <= nx_nomore_data_o; - end if; -- new_timestamp = '1' - - -- Trigger Rate - if (nx_rate_timer < x"186a0") then - nx_rate_timer <= nx_rate_timer + 1; - else - nx_rate_timer <= (others => '0'); - nx_trigger_rate <= nx_valid_ctr; - nx_valid_ctr <= (others => '0'); - end if; - - -- Reset Counters - if (clear_counters = '1') then - invalid_frame_ctr <= (others => '0'); - overflow_ctr <= (others => '0'); - pileup_ctr <= (others => '0'); - parity_error_ctr <= (others => '0'); - end if; - end if; - end if; - end process PROC_VALIDATE_TIMESTAMP; - - ----------------------------------------------------------------------------- - -- TRBNet Slave Bus - ----------------------------------------------------------------------------- - - -- Give status info to the TRB Slow Control Channel - PROC_FIFO_REGISTERS: process(CLK_IN) - begin - if( rising_edge(CLK_IN) ) then - if( RESET_IN = '1' ) then - slv_data_out_o <= (others => '0'); - slv_ack_o <= '0'; - slv_unknown_addr_o <= '0'; - slv_no_more_data_o <= '0'; - clear_counters <= '0'; - else - slv_data_out_o <= (others => '0'); - slv_unknown_addr_o <= '0'; - slv_no_more_data_o <= '0'; - clear_counters <= '0'; - - if (SLV_READ_IN = '1') then - case SLV_ADDR_IN is - - when x"0000" => - slv_data_out_o(15 downto 0) <= - std_logic_vector(invalid_frame_ctr); - slv_data_out_o(31 downto 16) <= (others => '0'); - slv_ack_o <= '1'; - - when x"0001" => - slv_data_out_o(15 downto 0) <= - std_logic_vector(overflow_ctr); - slv_data_out_o(31 downto 16) <= (others => '0'); - slv_ack_o <= '1'; - - when x"0002" => - slv_data_out_o(15 downto 0) <= - std_logic_vector(pileup_ctr); - slv_data_out_o(31 downto 16) <= (others => '0'); - slv_ack_o <= '1'; - - when x"0003" => - slv_data_out_o(15 downto 0) <= - std_logic_vector(parity_error_ctr); - slv_data_out_o(31 downto 16) <= (others => '0'); - slv_ack_o <= '1'; - - when x"0004" => - slv_data_out_o(19 downto 0) <= - std_logic_vector(nx_trigger_rate); - slv_data_out_o(31 downto 20) <= (others => '0'); - slv_ack_o <= '1'; - - when others => - slv_unknown_addr_o <= '1'; - slv_ack_o <= '0'; - end case; - - elsif (SLV_WRITE_IN = '1') then - case SLV_ADDR_IN is - when x"0000" => - clear_counters <= '1'; - slv_ack_o <= '1'; - - when others => - slv_unknown_addr_o <= '1'; - slv_ack_o <= '0'; - end case; - else - slv_ack_o <= '0'; - end if; - end if; - end if; - end process PROC_FIFO_REGISTERS; - - ----------------------------------------------------------------------------- - -- Output Signals - ----------------------------------------------------------------------------- - - TIMESTAMP_OUT <= timestamp_o; - CHANNEL_OUT <= channel_o; - TIMESTAMP_STATUS_OUT <= timestamp_status_o; - ADC_DATA_OUT <= adc_data_o; - DATA_VALID_OUT <= data_valid_o; - NX_TOKEN_RETURN_OUT <= nx_token_return_o; - NX_NOMORE_DATA_OUT <= nx_nomore_data_o; - - -- Slave - SLV_DATA_OUT <= slv_data_out_o; - SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; - SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o; - SLV_ACK_OUT <= slv_ack_o; -end Behavioral; +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.nxyter_components.all; + +entity nx_data_validate is + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + + -- Inputs + NX_TIMESTAMP_IN : in std_logic_vector(31 downto 0); + ADC_DATA_IN : in std_logic_vector(11 downto 0); + NEW_DATA_IN : in std_logic; + + -- Outputs + TIMESTAMP_OUT : out std_logic_vector(13 downto 0); + CHANNEL_OUT : out std_logic_vector(6 downto 0); + TIMESTAMP_STATUS_OUT : out std_logic_vector(2 downto 0); + ADC_DATA_OUT : out std_logic_vector(11 downto 0); + DATA_VALID_OUT : out std_logic; + + NX_TOKEN_RETURN_OUT : out std_logic; + NX_NOMORE_DATA_OUT : out std_logic; + + -- Slave bus + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ADDR_IN : in std_logic_vector(15 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic; + + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); + +end entity; + +architecture Behavioral of nx_data_validate is + + -- Gray Decoder + signal nx_timestamp : std_logic_vector(13 downto 0); + signal nx_channel_id : std_logic_vector( 6 downto 0); + + -- TIMESTAMP_BITS + signal new_timestamp : std_logic; + signal valid_frame_bits : std_logic_vector(3 downto 0); + signal status_bits : std_logic_vector(1 downto 0); + signal parity_bit : std_logic; + signal parity : std_logic; + signal adc_data : std_logic_vector(11 downto 0); + + -- Validate Timestamp + signal timestamp_o : std_logic_vector(13 downto 0); + signal channel_o : std_logic_vector(6 downto 0); + signal timestamp_status_o : std_logic_vector(2 downto 0); + signal adc_data_o : std_logic_vector(11 downto 0); + signal data_valid_o : std_logic; + + signal nx_token_return_o : std_logic; + signal nx_nomore_data_o : std_logic; + + signal invalid_frame_ctr : unsigned(15 downto 0); + signal overflow_ctr : unsigned(15 downto 0); + signal pileup_ctr : unsigned(15 downto 0); + signal parity_error_ctr : unsigned(15 downto 0); + + signal trigger_rate_inc : std_logic; + signal frame_rate_inc : std_logic; + + -- Rate Calculation + signal nx_trigger_ctr_t : unsigned(27 downto 0); + signal nx_frame_ctr_t : unsigned(27 downto 0); + signal nx_rate_timer : unsigned(27 downto 0); + + -- Config + signal readout_type : std_logic_vector(1 downto 0); + + -- Slave Bus + signal slv_data_out_o : std_logic_vector(31 downto 0); + signal slv_no_more_data_o : std_logic; + signal slv_unknown_addr_o : std_logic; + signal slv_ack_o : std_logic; + signal clear_counters : std_logic; + signal nx_trigger_rate : unsigned(27 downto 0); + signal nx_frame_rate : unsigned(27 downto 0); + + signal invalid_adc : std_logic; + +begin + + -- Debug Line + DEBUG_OUT(0) <= CLK_IN; + DEBUG_OUT(1) <= nx_token_return_o; + DEBUG_OUT(2) <= nx_nomore_data_o; + DEBUG_OUT(3) <= data_valid_o; + DEBUG_OUT(4) <= new_timestamp; + DEBUG_OUT(8 downto 5) <= (others => '0'); + DEBUG_OUT(15 downto 9) <= channel_o; + --DEBUG_OUT(6 downto 4) <= timestamp_status_o; + --DEBUG_OUT(7) <= nx_token_return_o; + --DEBUG_OUT(8) <= invalid_adc;--nx_nomore_data_o; + + --DEBUG_OUT(15 downto 9) <= channel_o; + + ----------------------------------------------------------------------------- + -- Gray Decoder for Timestamp and Channel Id + ----------------------------------------------------------------------------- + + Gray_Decoder_1: Gray_Decoder -- Decode nx_timestamp + generic map ( + WIDTH => 14 + ) + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + GRAY_IN(13 downto 7) => not NX_TIMESTAMP_IN(30 downto 24), + GRAY_IN( 6 downto 0) => not NX_TIMESTAMP_IN(22 downto 16), + BINARY_OUT => nx_timestamp + ); + + Gray_Decoder_2: Gray_Decoder -- Decode Channel_ID + generic map ( + WIDTH => 7 + ) + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + GRAY_IN => NX_TIMESTAMP_IN(14 downto 8), + BINARY_OUT => nx_channel_id + ); + + -- Separate Status-, Parity- and Frame-bits, calculate parity + PROC_TIMESTAMP_BITS: process (CLK_IN) + variable parity_bits : std_logic_vector(22 downto 0); + begin + if( rising_edge(CLK_IN) ) then + if (RESET_IN = '1') then + valid_frame_bits <= (others => '0'); + status_bits <= (others => '0'); + parity_bit <= '0'; + parity <= '0'; + new_timestamp <= '0'; + adc_data <= (others => '0'); + else + -- Timestamp Bit #6 is excluded (funny nxyter-bug) + parity_bits := NX_TIMESTAMP_IN(31 downto 24) & + NX_TIMESTAMP_IN(21 downto 16) & + NX_TIMESTAMP_IN(14 downto 8) & + NX_TIMESTAMP_IN( 2 downto 1); + valid_frame_bits <= (others => '0'); + status_bits <= (others => '0'); + parity_bit <= '0'; + parity <= '0'; + new_timestamp <= '0'; + adc_data <= (others => '0'); + + if (NEW_DATA_IN = '1') then + valid_frame_bits(3) <= NX_TIMESTAMP_IN(31); + valid_frame_bits(2) <= NX_TIMESTAMP_IN(23); + valid_frame_bits(1) <= NX_TIMESTAMP_IN(15); + valid_frame_bits(0) <= NX_TIMESTAMP_IN(7); + status_bits <= NX_TIMESTAMP_IN(2 downto 1); + parity_bit <= NX_TIMESTAMP_IN(0); + parity <= xor_all(parity_bits); + adc_data <= ADC_DATA_IN; + new_timestamp <= '1'; + end if; + end if; + end if; + end process PROC_TIMESTAMP_BITS; + + ----------------------------------------------------------------------------- + -- Filter only valid events + ----------------------------------------------------------------------------- + + PROC_VALIDATE_TIMESTAMP: process (CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if (RESET_IN = '1') then + timestamp_o <= (others => '0'); + channel_o <= (others => '0'); + timestamp_status_o <= (others => '0'); + adc_data_o <= (others => '0'); + data_valid_o <= '0'; + nx_token_return_o <= '0'; + nx_nomore_data_o <= '0'; + trigger_rate_inc <= '0'; + frame_rate_inc <= '0'; + + invalid_frame_ctr <= (others => '0'); + overflow_ctr <= (others => '0'); + pileup_ctr <= (others => '0'); + parity_error_ctr <= (others => '0'); + else + timestamp_o <= (others => '0'); + channel_o <= (others => '0'); + timestamp_status_o <= (others => '0'); + adc_data_o <= (others => '0'); + data_valid_o <= '0'; + trigger_rate_inc <= '0'; + frame_rate_inc <= '0'; + invalid_adc <= '0'; + + if (new_timestamp = '1') then + case valid_frame_bits is + + -- Data Frame + when "1000" => + ---- Check Overflow + if ((status_bits(0) = '1') and (clear_counters = '0')) then + overflow_ctr <= overflow_ctr + 1; + end if; + + ---- Check Parity + if ((parity_bit /= parity) and (clear_counters = '0')) then + timestamp_status_o(0) <= '1'; + parity_error_ctr <= parity_error_ctr + 1; + end if; + + -- Check PileUp + if ((status_bits(1) = '1') and (clear_counters = '0')) then + pileup_ctr <= pileup_ctr + 1; + end if; + + -- Take Timestamp + timestamp_o <= nx_timestamp; + channel_o <= nx_channel_id; + timestamp_status_o(2 downto 1) <= status_bits; + adc_data_o <= adc_data; + data_valid_o <= '1'; + + if (adc_data = x"aff") then + invalid_adc <= '1'; + end if; + + nx_token_return_o <= '0'; + nx_nomore_data_o <= '0'; + trigger_rate_inc <= '1'; + + -- Token return and nomore_data + when "0000" => + nx_token_return_o <= '1'; + nx_nomore_data_o <= nx_token_return_o; + + when others => + -- Invalid frame, not empty, discard timestamp + if (clear_counters = '0') then + invalid_frame_ctr <= invalid_frame_ctr + 1; + end if; + nx_token_return_o <= '0'; + nx_nomore_data_o <= '0'; + + end case; + + frame_rate_inc <= '1'; + + else + nx_token_return_o <= nx_token_return_o; + nx_nomore_data_o <= nx_nomore_data_o; + end if; + + -- Reset Counters + if (clear_counters = '1') then + invalid_frame_ctr <= (others => '0'); + overflow_ctr <= (others => '0'); + pileup_ctr <= (others => '0'); + parity_error_ctr <= (others => '0'); + end if; + end if; + end if; + end process PROC_VALIDATE_TIMESTAMP; + + PROC_CAL_RATES: process (CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if (RESET_IN = '1') then + nx_trigger_ctr_t <= (others => '0'); + nx_frame_ctr_t <= (others => '0'); + nx_rate_timer <= (others => '0'); + nx_trigger_rate <= (others => '0'); + nx_frame_rate <= (others => '0'); + else + if (nx_rate_timer < x"5f5e100") then + if (trigger_rate_inc = '1') then + nx_trigger_ctr_t <= nx_trigger_ctr_t + 1; + end if; + if (frame_rate_inc = '1') then + nx_frame_ctr_t <= nx_frame_ctr_t + 1; + end if; + nx_rate_timer <= nx_rate_timer + 1; + else + nx_trigger_rate <= nx_trigger_ctr_t; + nx_frame_rate <= nx_frame_ctr_t; + nx_trigger_ctr_t <= (others => '0'); + nx_frame_ctr_t <= (others => '0'); + nx_rate_timer <= (others => '0'); + end if; + end if; + end if; + end process PROC_CAL_RATES; + + ----------------------------------------------------------------------------- + -- TRBNet Slave Bus + ----------------------------------------------------------------------------- + + -- Give status info to the TRB Slow Control Channel + PROC_FIFO_REGISTERS: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + slv_data_out_o <= (others => '0'); + slv_ack_o <= '0'; + slv_unknown_addr_o <= '0'; + slv_no_more_data_o <= '0'; + clear_counters <= '0'; + else + slv_data_out_o <= (others => '0'); + slv_unknown_addr_o <= '0'; + slv_no_more_data_o <= '0'; + clear_counters <= '0'; + + if (SLV_READ_IN = '1') then + case SLV_ADDR_IN is + + when x"0000" => + slv_data_out_o(15 downto 0) <= + std_logic_vector(invalid_frame_ctr); + slv_data_out_o(31 downto 16) <= (others => '0'); + slv_ack_o <= '1'; + + when x"0001" => + slv_data_out_o(15 downto 0) <= + std_logic_vector(overflow_ctr); + slv_data_out_o(31 downto 16) <= (others => '0'); + slv_ack_o <= '1'; + + when x"0002" => + slv_data_out_o(15 downto 0) <= + std_logic_vector(pileup_ctr); + slv_data_out_o(31 downto 16) <= (others => '0'); + slv_ack_o <= '1'; + + when x"0003" => + slv_data_out_o(15 downto 0) <= + std_logic_vector(parity_error_ctr); + slv_data_out_o(31 downto 16) <= (others => '0'); + slv_ack_o <= '1'; + + when x"0004" => + slv_data_out_o(27 downto 0) <= + std_logic_vector(nx_trigger_rate); + slv_data_out_o(31 downto 28) <= (others => '0'); + slv_ack_o <= '1'; + + when x"0005" => + slv_data_out_o(27 downto 0) <= + std_logic_vector(nx_frame_rate); + slv_data_out_o(31 downto 28) <= (others => '0'); + slv_ack_o <= '1'; + + when others => + slv_unknown_addr_o <= '1'; + slv_ack_o <= '0'; + end case; + + elsif (SLV_WRITE_IN = '1') then + case SLV_ADDR_IN is + when x"0000" => + clear_counters <= '1'; + slv_ack_o <= '1'; + + when others => + slv_unknown_addr_o <= '1'; + slv_ack_o <= '0'; + end case; + else + slv_ack_o <= '0'; + end if; + end if; + end if; + end process PROC_FIFO_REGISTERS; + + ----------------------------------------------------------------------------- + -- Output Signals + ----------------------------------------------------------------------------- + + TIMESTAMP_OUT <= timestamp_o; + CHANNEL_OUT <= channel_o; + TIMESTAMP_STATUS_OUT <= timestamp_status_o; + ADC_DATA_OUT <= adc_data_o; + DATA_VALID_OUT <= data_valid_o; + NX_TOKEN_RETURN_OUT <= nx_token_return_o; + NX_NOMORE_DATA_OUT <= nx_nomore_data_o; + + -- Slave + SLV_DATA_OUT <= slv_data_out_o; + SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; + SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o; + SLV_ACK_OUT <= slv_ack_o; +end Behavioral; diff --git a/nxyter/source/nx_fpga_timestamp.vhd b/nxyter/source/nx_fpga_timestamp.vhd index 1262c19..21bd917 100644 --- a/nxyter/source/nx_fpga_timestamp.vhd +++ b/nxyter/source/nx_fpga_timestamp.vhd @@ -12,8 +12,8 @@ entity nx_fpga_timestamp is TIMESTAMP_SYNC_IN : in std_logic; TRIGGER_IN : in std_logic; - - TIMESTAMP_OUT : out unsigned(11 downto 0); + TIMESTAMP_CURRENT_OUT : out unsigned(11 downto 0); + TIMESTAMP_HOLD_OUT : out unsigned(11 downto 0); NX_TIMESTAMP_SYNC_OUT : out std_logic; -- Slave bus @@ -33,7 +33,8 @@ end entity; architecture Behavioral of nx_fpga_timestamp is signal timestamp_ctr : unsigned(11 downto 0); - signal timestamp_o : unsigned(11 downto 0); + signal timestamp_current_o : unsigned(11 downto 0); + signal timestamp_hold_o : unsigned(11 downto 0); signal trigger_x : std_logic; signal trigger_l : std_logic; signal trigger : std_logic; @@ -49,10 +50,9 @@ begin DEBUG_OUT(1) <= trigger; DEBUG_OUT(2) <= timestamp_sync; DEBUG_OUT(3) <= '0'; - DEBUG_OUT(15 downto 4) <= TIMESTAMP_OUT; + DEBUG_OUT(15 downto 4) <= timestamp_hold_o; - -- Cross the abyss for trigger and sync signal - + -- Cross Clockdomain for TRIGGER and SYNC signal PROC_SYNC: process (CLK_IN) begin if( rising_edge(CLK_IN) ) then @@ -71,7 +71,6 @@ begin end process PROC_SYNC; -- Convert TRIGGER_IN to Pulse - level_to_pulse_1: level_to_pulse port map ( CLK_IN => CLK_IN, @@ -81,7 +80,6 @@ begin ); -- Convert TIMESTAMP_SYNC_IN to Pulse - level_to_pulse_2: level_to_pulse port map ( CLK_IN => CLK_IN, @@ -96,19 +94,19 @@ begin begin if( rising_edge(CLK_IN) ) then if( RESET_IN = '1' ) then - timestamp_ctr <= (others => '0'); - timestamp_o <= (others => '0'); - nx_timestamp_sync_o <= '0'; + timestamp_ctr <= (others => '0'); + timestamp_hold_o <= (others => '0'); + nx_timestamp_sync_o <= '0'; else - nx_timestamp_sync_o <= '0'; + nx_timestamp_sync_o <= '0'; if (timestamp_sync = '1') then timestamp_ctr <= (others => '0'); - timestamp_o <= (others => '0'); + timestamp_hold_o <= (others => '0'); nx_timestamp_sync_o <= '1'; else if (trigger = '1') then - timestamp_o <= timestamp_ctr - 3; + timestamp_hold_o <= timestamp_ctr - 3; end if; timestamp_ctr <= timestamp_ctr + 1; end if; @@ -116,12 +114,15 @@ begin end if; end process; + timestamp_current_o <= timestamp_ctr; + ----------------------------------------------------------------------------- -- Output Signals ----------------------------------------------------------------------------- - - TIMESTAMP_OUT <= timestamp_o; - NX_TIMESTAMP_SYNC_OUT <= nx_timestamp_sync_o; + + TIMESTAMP_CURRENT_OUT <= timestamp_current_o; + TIMESTAMP_HOLD_OUT <= timestamp_hold_o; + NX_TIMESTAMP_SYNC_OUT <= nx_timestamp_sync_o; end Behavioral; diff --git a/nxyter/source/nx_histograms.vhd b/nxyter/source/nx_histograms.vhd index d7b83dc..2465d5a 100644 --- a/nxyter/source/nx_histograms.vhd +++ b/nxyter/source/nx_histograms.vhd @@ -36,7 +36,7 @@ end entity; architecture nx_histograms of nx_histograms is - type histogram_t is array(0 to 2**BUS_WIDTH - 1) of unsigned(23 downto 0); + type histogram_t is array(0 to 2**BUS_WIDTH - 1) of unsigned(31 downto 0); -- PROC_CHANNEL_HIST signal hist_channel_stat : histogram_t; @@ -130,17 +130,17 @@ hist_enable_1: if ENABLE = 1 generate if (SLV_READ_IN = '1') then if (unsigned(SLV_ADDR_IN) >= x"0000" and unsigned(SLV_ADDR_IN) <= x"007f") then - slv_data_out_o(23 downto 0) <= std_logic_vector( + slv_data_out_o(31 downto 0) <= std_logic_vector( hist_channel_stat(to_integer(unsigned(SLV_ADDR_IN(7 downto 0)))) ); - slv_data_out_o(31 downto 24) <= (others => '0'); + -- slv_data_out_o(31 downto 24) <= (others => '0'); slv_ack_o <= '1'; elsif (unsigned(SLV_ADDR_IN) >= x"0080" and unsigned(SLV_ADDR_IN) <= x"00ff") then - slv_data_out_o(23 downto 0) <= std_logic_vector( + slv_data_out_o(31 downto 0) <= std_logic_vector( hist_channel_freq(to_integer(unsigned(SLV_ADDR_IN(7 downto 0)))) ); - slv_data_out_o(31 downto 24) <= (others => '0'); + -- slv_data_out_o(31 downto 24) <= (others => '0'); slv_ack_o <= '1'; else slv_ack_o <= '0'; diff --git a/nxyter/source/nx_i2c_master.vhd b/nxyter/source/nx_i2c_master.vhd index e0a9d18..1d4208f 100644 --- a/nxyter/source/nx_i2c_master.vhd +++ b/nxyter/source/nx_i2c_master.vhd @@ -1,558 +1,558 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.nxyter_components.all; - -entity nx_i2c_master is - generic ( - I2C_SPEED : unsigned(11 downto 0) := x"3e8" - ); - port( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - - -- I2C connections - SDA_INOUT : inout std_logic; - SCL_INOUT : inout std_logic; - - -- Internal Interface - INTERNAL_COMMAND_IN : in std_logic_vector(31 downto 0); - COMMAND_BUSY_OUT : out std_logic; - I2C_DATA_OUT : out std_logic_vector(31 downto 0); - I2C_LOCK_IN : in std_logic; - - -- Slave bus - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_ACK_OUT : out std_logic; - SLV_NO_MORE_DATA_OUT : out std_logic; - SLV_UNKNOWN_ADDR_OUT : out std_logic; - - -- Debug Line - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); -end entity; - -architecture Behavioral of nx_i2c_master is - - signal sda_o : std_logic; - signal scl_o : std_logic; - - signal sda_i : std_logic; - signal sda_x : std_logic; - signal sda : std_logic; - - signal scl_i : std_logic; - signal scl_x : std_logic; - signal scl : std_logic; - signal command_busy_o : std_logic; - - -- I2C Master - signal sda_master : std_logic; - signal scl_master : std_logic; - signal i2c_start : std_logic; - signal i2c_busy : std_logic; - signal startstop_select : std_logic; - signal startstop_seq_start : std_logic; - signal sendbyte_seq_start : std_logic; - signal readbyte_seq_start : std_logic; - signal sendbyte_byte : std_logic_vector(7 downto 0); - signal read_seq_ctr : std_logic; - signal i2c_data : std_logic_vector(31 downto 0); - - signal i2c_busy_x : std_logic; - signal startstop_select_x : std_logic; - signal startstop_seq_start_x : std_logic; - signal sendbyte_seq_start_x : std_logic; - signal sendbyte_byte_x : std_logic_vector(7 downto 0); - signal readbyte_seq_start_x : std_logic; - signal read_seq_ctr_x : std_logic; - signal i2c_data_x : std_logic_vector(31 downto 0); - - signal sda_startstop : std_logic; - signal scl_startstop : std_logic; - signal i2c_notready : std_logic; - signal startstop_done : std_logic; - - signal sda_sendbyte : std_logic; - signal scl_sendbyte : std_logic; - signal sendbyte_ack : std_logic; - signal sendbyte_done : std_logic; - - signal sda_readbyte : std_logic; - signal scl_readbyte : std_logic; - signal readbyte_byte : std_logic_vector(7 downto 0); - signal readbyte_done : std_logic; - - type STATES is (S_RESET, - S_IDLE, - S_START, - S_START_WAIT, - - S_SEND_CHIP_ID, - S_SEND_CHIP_ID_WAIT, - S_SEND_REGISTER, - S_SEND_REGISTER_WAIT, - S_SEND_DATA, - S_SEND_DATA_WAIT, - S_GET_DATA, - S_GET_DATA_WAIT, - - S_STOP, - S_STOP_WAIT - ); - signal STATE, NEXT_STATE : STATES; - - -- TRBNet Slave Bus - signal slv_data_out_o : std_logic_vector(31 downto 0); - signal slv_no_more_data_o : std_logic; - signal slv_unknown_addr_o : std_logic; - signal slv_ack_o : std_logic; - - signal i2c_chipid : std_logic_vector(6 downto 0); - signal i2c_rw_bit : std_logic; - signal i2c_registerid : std_logic_vector(7 downto 0); - signal i2c_register_data : std_logic_vector(7 downto 0); - signal i2c_register_value_read : std_logic_vector(7 downto 0); - - signal disable_slave_bus : std_logic; - signal internal_command : std_logic; - signal internal_command_d : std_logic; - signal i2c_data_internal_o : std_logic_vector(31 downto 0); - signal i2c_data_slave : std_logic_vector(31 downto 0); - -begin - - -- Debug - DEBUG_OUT(0) <= CLK_IN; - DEBUG_OUT(8 downto 1) <= i2c_data(7 downto 0); - DEBUG_OUT(10 downto 9) <= i2c_data(31 downto 30); - DEBUG_OUT(11) <= i2c_busy; - DEBUG_OUT(12) <= sda_o; - DEBUG_OUT(13) <= scl_o; - DEBUG_OUT(14) <= sda; - DEBUG_OUT(15) <= scl; - --DEBUG_OUT(12 downto 9) <= i2c_data(31 downto 28); - - -- Start / Stop Sequence - nx_i2c_startstop_1: nx_i2c_startstop - generic map ( - I2C_SPEED => I2C_SPEED - ) - port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - START_IN => startstop_seq_start, - SELECT_IN => startstop_select, - SEQUENCE_DONE_OUT => startstop_done, - SDA_OUT => sda_startstop, - SCL_OUT => scl_startstop, - NREADY_OUT => i2c_notready - ); - - nx_i2c_sendbyte_1: nx_i2c_sendbyte - generic map ( - I2C_SPEED => I2C_SPEED - ) - port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - START_IN => sendbyte_seq_start, - BYTE_IN => sendbyte_byte, - SEQUENCE_DONE_OUT => sendbyte_done, - SDA_OUT => sda_sendbyte, - SCL_OUT => scl_sendbyte, - SDA_IN => sda, - SCL_IN => scl, - ACK_OUT => sendbyte_ack - ); - - nx_i2c_readbyte_1: nx_i2c_readbyte - generic map ( - I2C_SPEED => I2C_SPEED - ) - port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - START_IN => readbyte_seq_start, - BYTE_OUT => readbyte_byte, - SEQUENCE_DONE_OUT => readbyte_done, - SDA_OUT => sda_readbyte, - SCL_OUT => scl_readbyte, - SDA_IN => sda - ); - - -- Sync I2C Lines - sda_i <= SDA_INOUT; - scl_i <= SCL_INOUT; - - PROC_I2C_LINES_SYNC: process(CLK_IN) - begin - if( rising_edge(CLK_IN) ) then - if( RESET_IN = '1' ) then - sda_x <= '1'; - sda <= '1'; - - scl_x <= '1'; - scl <= '1'; - else - sda_x <= sda_i; - sda <= sda_x; - - scl_x <= scl_i; - scl <= scl_x; - end if; - end if; - end process PROC_I2C_LINES_SYNC; - - PROC_I2C_MASTER_TRANSFER: process(CLK_IN) - begin - if( rising_edge(CLK_IN) ) then - if( RESET_IN = '1' ) then - i2c_busy <= '1'; - startstop_select <= '0'; - startstop_seq_start <= '0'; - sendbyte_seq_start <= '0'; - readbyte_seq_start <= '0'; - sendbyte_byte <= (others => '0'); - i2c_data <= (others => '0'); - read_seq_ctr <= '0'; - STATE <= S_RESET; - else - i2c_busy <= i2c_busy_x; - startstop_select <= startstop_select_x; - startstop_seq_start <= startstop_seq_start_x; - sendbyte_seq_start <= sendbyte_seq_start_x; - readbyte_seq_start <= readbyte_seq_start_x; - sendbyte_byte <= sendbyte_byte_x; - i2c_data <= i2c_data_x; - read_seq_ctr <= read_seq_ctr_x; - STATE <= NEXT_STATE; - end if; - end if; - end process PROC_I2C_MASTER_TRANSFER; - - - PROC_I2C_MASTER: process(STATE, - i2c_start, - startstop_done, - read_seq_ctr, - sendbyte_done, - sendbyte_ack, - readbyte_done, - startstop_done - ) - - begin - -- Defaults - sda_master <= '1'; - scl_master <= '1'; - i2c_busy_x <= '1'; - startstop_select_x <= '0'; - startstop_seq_start_x <= '0'; - sendbyte_seq_start_x <= '0'; - sendbyte_byte_x <= (others => '0'); - readbyte_seq_start_x <= '0'; - i2c_data_x <= i2c_data; - read_seq_ctr_x <= read_seq_ctr; - - case STATE is - - when S_RESET => - i2c_data_x <= (others => '0'); - NEXT_STATE <= S_IDLE; - - when S_IDLE => - if (i2c_start = '1') then - i2c_data_x <= x"8000_0000"; -- Set Running, clear all - -- other bits - NEXT_STATE <= S_START; - else - i2c_busy_x <= '0'; - i2c_data_x <= i2c_data and x"7fff_ffff"; -- clear running - -- bit; - read_seq_ctr_x <= '0'; - NEXT_STATE <= S_IDLE; - end if; - - -- I2C START Sequence - when S_START => - startstop_select_x <= '1'; - startstop_seq_start_x <= '1'; - NEXT_STATE <= S_START_WAIT; - - when S_START_WAIT => - if (startstop_done = '0') then - NEXT_STATE <= S_START_WAIT; - else - sda_master <= '0'; - scl_master <= '0'; - NEXT_STATE <= S_SEND_CHIP_ID; - end if; - - -- I2C SEND ChipId Sequence - when S_SEND_CHIP_ID => - scl_master <= '0'; - sendbyte_byte_x(7 downto 1) <= i2c_chipid; - if (read_seq_ctr = '0') then - sendbyte_byte_x(0) <= '0'; - else - sendbyte_byte_x(0) <= '1'; - end if; - sendbyte_seq_start_x <= '1'; - NEXT_STATE <= S_SEND_CHIP_ID_WAIT; - - when S_SEND_CHIP_ID_WAIT => - if (sendbyte_done = '0') then - NEXT_STATE <= S_SEND_CHIP_ID_WAIT; - else - scl_master <= '0'; - if (sendbyte_ack = '0') then - i2c_data_x <= i2c_data or x"0100_0000"; - NEXT_STATE <= S_STOP; - else - if (read_seq_ctr = '0') then - read_seq_ctr_x <= '1'; - NEXT_STATE <= S_SEND_REGISTER; - else - NEXT_STATE <= S_GET_DATA; - end if; - end if; - end if; - - -- I2C SEND RegisterId - when S_SEND_REGISTER => - scl_master <= '0'; - sendbyte_byte_x <= i2c_registerid; - sendbyte_seq_start_x <= '1'; - NEXT_STATE <= S_SEND_REGISTER_WAIT; - - when S_SEND_REGISTER_WAIT => - if (sendbyte_done = '0') then - NEXT_STATE <= S_SEND_REGISTER_WAIT; - else - scl_master <= '0'; - if (sendbyte_ack = '0') then - i2c_data_x <= i2c_data or x"0200_0000"; - NEXT_STATE <= S_STOP; - else - if (i2c_rw_bit = '0') then - NEXT_STATE <= S_SEND_DATA; - else - NEXT_STATE <= S_START; - end if; - end if; - end if; - - -- I2C SEND DataWord - when S_SEND_DATA => - scl_master <= '0'; - sendbyte_byte_x <= i2c_register_data; - sendbyte_seq_start_x <= '1'; - NEXT_STATE <= S_SEND_DATA_WAIT; - - when S_SEND_DATA_WAIT => - if (sendbyte_done = '0') then - NEXT_STATE <= S_SEND_DATA_WAIT; - else - scl_master <= '0'; - if (sendbyte_ack = '0') then - i2c_data_x <= i2c_data or x"0400_0000"; - end if; - NEXT_STATE <= S_STOP; - end if; - - -- I2C GET DataWord - when S_GET_DATA => - scl_master <= '0'; - readbyte_seq_start_x <= '1'; - NEXT_STATE <= S_GET_DATA_WAIT; - - when S_GET_DATA_WAIT => - if (readbyte_done = '0') then - NEXT_STATE <= S_GET_DATA_WAIT; - else - scl_master <= '0'; - i2c_data_x(7 downto 0)<= readbyte_byte; - NEXT_STATE <= S_STOP; - end if; - - -- I2C STOP Sequence - when S_STOP => - sda_master <= '0'; - scl_master <= '0'; - startstop_select_x <= '0'; - startstop_seq_start_x <= '1'; - NEXT_STATE <= S_STOP_WAIT; - - when S_STOP_WAIT => - if (startstop_done = '0') then - NEXT_STATE <= S_STOP_WAIT; - else - i2c_data_x <= i2c_data or x"4000_0000"; -- Set DONE Bit - NEXT_STATE <= S_IDLE; - end if; - - end case; - end process PROC_I2C_MASTER; - - PROC_I2C_DATA_MULTIPLEXER: process(CLK_IN) - begin - if( rising_edge(CLK_IN) ) then - if( RESET_IN = '1' ) then - i2c_data_internal_o <= (others => '0'); - i2c_data_slave <= (others => '0'); - command_busy_o <= '0'; - else - if (internal_command = '0' and internal_command_d = '0') then - i2c_data_slave <= i2c_data; - else - i2c_data_internal_o <= i2c_data; - end if; - end if; - command_busy_o <= i2c_busy; - end if; - end process PROC_I2C_DATA_MULTIPLEXER; - - ----------------------------------------------------------------------------- - -- TRBNet Slave Bus - ----------------------------------------------------------------------------- - -- - -- Write bit definition - -- ==================== - -- - -- D[31] I2C_GO 0 => don't do anything on I2C, - -- 1 => start I2C access - -- D[30] I2C_ACTION 0 => write byte, 1 => read byte - -- D[29:24] I2C_SPEED set all to '1' - -- D[23:16] I2C_ADDRESS address of I2C chip - -- D[15:8] I2C_CMD command byte for access - -- D[7:0] I2C_DATA data to be written - -- - -- Read bit definition - -- =================== - -- - -- D[31] RUNNING whatever - -- D[30] I2C_DONE whatever - -- D[29] ERROR_RADDACK no acknowledge for repeated address byte - -- D[28] ERROR_RSTART generation of repeated START condition failed - -- D[27] ERROR_DATACK no acknowledge for data byte - -- D[26] ERROR_CMDACK no acknowledge for command byte - -- D[25] ERROR_ADDACK no acknowledge for address byte - -- D[24] ERROR_START generation of START condition failed - -- D[23:21] reserved reserved - -- D[20:16] debug subject to change, don't use - -- D[15:8] reserved reserved - -- D[7:0] I2C_DATA result of I2C read operation - -- - - PROC_SLAVE_BUS: process(CLK_IN) - begin - if( rising_edge(CLK_IN) ) then - if( RESET_IN = '1' ) then - slv_data_out_o <= (others => '0'); - slv_no_more_data_o <= '0'; - slv_unknown_addr_o <= '0'; - slv_ack_o <= '0'; - i2c_start <= '0'; - internal_command <= '0'; - internal_command_d <= '0'; - - i2c_chipid <= (others => '0'); - i2c_rw_bit <= '0'; - i2c_registerid <= (others => '0'); - i2c_register_data <= (others => '0'); - i2c_register_value_read <= (others => '0'); - - else - slv_unknown_addr_o <= '0'; - slv_no_more_data_o <= '0'; - slv_data_out_o <= (others => '0'); - i2c_start <= '0'; - - internal_command_d <= internal_command; - - if (i2c_busy = '0' and internal_command_d = '1') then - internal_command <= '0'; - slv_ack_o <= '0'; - - elsif (i2c_busy = '0' and INTERNAL_COMMAND_IN(31) = '1') then - -- Internal Interface Command - i2c_rw_bit <= INTERNAL_COMMAND_IN(30); - i2c_chipid <= INTERNAL_COMMAND_IN(22 downto 16); - i2c_registerid <= INTERNAL_COMMAND_IN(15 downto 8); - i2c_register_data <= INTERNAL_COMMAND_IN(7 downto 0); - i2c_start <= '1'; - internal_command <= '1'; - slv_ack_o <= '0'; - - elsif (SLV_WRITE_IN = '1') then - if (internal_command = '0' and - I2C_LOCK_IN = '0' and - i2c_busy = '0' and - SLV_DATA_IN(31) = '1') then - i2c_rw_bit <= SLV_DATA_IN(30); - i2c_chipid <= SLV_DATA_IN(22 downto 16); - i2c_registerid <= SLV_DATA_IN(15 downto 8); - i2c_register_data <= SLV_DATA_IN(7 downto 0); - i2c_start <= '1'; - slv_ack_o <= '1'; - else - slv_no_more_data_o <= '1'; - slv_ack_o <= '0'; - end if; - - elsif (SLV_READ_IN = '1') then - if (internal_command = '0' and - I2C_LOCK_IN = '0' and - i2c_busy = '0') then - slv_data_out_o <= i2c_data_slave; - slv_ack_o <= '1'; - else - slv_data_out_o <= (others => '0'); - slv_no_more_data_o <= '1'; - slv_ack_o <= '0'; - end if; - - else - slv_ack_o <= '0'; - end if; - - end if; - end if; - end process PROC_SLAVE_BUS; - - - ----------------------------------------------------------------------------- - -- Output Signals - ----------------------------------------------------------------------------- - - -- I2C Outputs - sda_o <= (sda_master and - sda_startstop and - sda_sendbyte and - sda_readbyte - ); - SDA_INOUT <= '0' when (sda_o = '0') else 'Z'; - - scl_o <= (scl_master and - scl_startstop and - scl_sendbyte and - scl_readbyte - ); - SCL_INOUT <= '0' when (scl_o = '0') else 'Z'; - - COMMAND_BUSY_OUT <= command_busy_o; - I2C_DATA_OUT <= i2c_data_internal_o; - - -- Slave Bus - SLV_DATA_OUT <= slv_data_out_o; - SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; - SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o; - SLV_ACK_OUT <= slv_ack_o; - -end Behavioral; +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.nxyter_components.all; + +entity nx_i2c_master is + generic ( + I2C_SPEED : unsigned(11 downto 0) := x"3e8" + ); + port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + + -- I2C connections + SDA_INOUT : inout std_logic; + SCL_INOUT : inout std_logic; + + -- Internal Interface + INTERNAL_COMMAND_IN : in std_logic_vector(31 downto 0); + COMMAND_BUSY_OUT : out std_logic; + I2C_DATA_OUT : out std_logic_vector(31 downto 0); + I2C_LOCK_IN : in std_logic; + + -- Slave bus + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic; + + -- Debug Line + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); +end entity; + +architecture Behavioral of nx_i2c_master is + + signal sda_o : std_logic; + signal scl_o : std_logic; + + signal sda_i : std_logic; + signal sda_x : std_logic; + signal sda : std_logic; + + signal scl_i : std_logic; + signal scl_x : std_logic; + signal scl : std_logic; + signal command_busy_o : std_logic; + + -- I2C Master + signal sda_master : std_logic; + signal scl_master : std_logic; + signal i2c_start : std_logic; + signal i2c_busy : std_logic; + signal startstop_select : std_logic; + signal startstop_seq_start : std_logic; + signal sendbyte_seq_start : std_logic; + signal readbyte_seq_start : std_logic; + signal sendbyte_byte : std_logic_vector(7 downto 0); + signal read_seq_ctr : std_logic; + signal i2c_data : std_logic_vector(31 downto 0); + + signal i2c_busy_x : std_logic; + signal startstop_select_x : std_logic; + signal startstop_seq_start_x : std_logic; + signal sendbyte_seq_start_x : std_logic; + signal sendbyte_byte_x : std_logic_vector(7 downto 0); + signal readbyte_seq_start_x : std_logic; + signal read_seq_ctr_x : std_logic; + signal i2c_data_x : std_logic_vector(31 downto 0); + + signal sda_startstop : std_logic; + signal scl_startstop : std_logic; + signal i2c_notready : std_logic; + signal startstop_done : std_logic; + + signal sda_sendbyte : std_logic; + signal scl_sendbyte : std_logic; + signal sendbyte_ack : std_logic; + signal sendbyte_done : std_logic; + + signal sda_readbyte : std_logic; + signal scl_readbyte : std_logic; + signal readbyte_byte : std_logic_vector(7 downto 0); + signal readbyte_done : std_logic; + + type STATES is (S_RESET, + S_IDLE, + S_START, + S_START_WAIT, + + S_SEND_CHIP_ID, + S_SEND_CHIP_ID_WAIT, + S_SEND_REGISTER, + S_SEND_REGISTER_WAIT, + S_SEND_DATA, + S_SEND_DATA_WAIT, + S_GET_DATA, + S_GET_DATA_WAIT, + + S_STOP, + S_STOP_WAIT + ); + signal STATE, NEXT_STATE : STATES; + + -- TRBNet Slave Bus + signal slv_data_out_o : std_logic_vector(31 downto 0); + signal slv_no_more_data_o : std_logic; + signal slv_unknown_addr_o : std_logic; + signal slv_ack_o : std_logic; + + signal i2c_chipid : std_logic_vector(6 downto 0); + signal i2c_rw_bit : std_logic; + signal i2c_registerid : std_logic_vector(7 downto 0); + signal i2c_register_data : std_logic_vector(7 downto 0); + signal i2c_register_value_read : std_logic_vector(7 downto 0); + + signal disable_slave_bus : std_logic; + signal internal_command : std_logic; + signal internal_command_d : std_logic; + signal i2c_data_internal_o : std_logic_vector(31 downto 0); + signal i2c_data_slave : std_logic_vector(31 downto 0); + +begin + + -- Debug + DEBUG_OUT(0) <= CLK_IN; + DEBUG_OUT(8 downto 1) <= i2c_data(7 downto 0); + DEBUG_OUT(10 downto 9) <= i2c_data(31 downto 30); + DEBUG_OUT(11) <= i2c_busy; + DEBUG_OUT(12) <= sda_o; + DEBUG_OUT(13) <= scl_o; + DEBUG_OUT(14) <= sda; + DEBUG_OUT(15) <= scl; + --DEBUG_OUT(12 downto 9) <= i2c_data(31 downto 28); + + -- Start / Stop Sequence + nx_i2c_startstop_1: nx_i2c_startstop + generic map ( + I2C_SPEED => I2C_SPEED + ) + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + START_IN => startstop_seq_start, + SELECT_IN => startstop_select, + SEQUENCE_DONE_OUT => startstop_done, + SDA_OUT => sda_startstop, + SCL_OUT => scl_startstop, + NREADY_OUT => i2c_notready + ); + + nx_i2c_sendbyte_1: nx_i2c_sendbyte + generic map ( + I2C_SPEED => I2C_SPEED + ) + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + START_IN => sendbyte_seq_start, + BYTE_IN => sendbyte_byte, + SEQUENCE_DONE_OUT => sendbyte_done, + SDA_OUT => sda_sendbyte, + SCL_OUT => scl_sendbyte, + SDA_IN => sda, + SCL_IN => scl, + ACK_OUT => sendbyte_ack + ); + + nx_i2c_readbyte_1: nx_i2c_readbyte + generic map ( + I2C_SPEED => I2C_SPEED + ) + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + START_IN => readbyte_seq_start, + BYTE_OUT => readbyte_byte, + SEQUENCE_DONE_OUT => readbyte_done, + SDA_OUT => sda_readbyte, + SCL_OUT => scl_readbyte, + SDA_IN => sda + ); + + -- Sync I2C Lines + sda_i <= SDA_INOUT; + scl_i <= SCL_INOUT; + + PROC_I2C_LINES_SYNC: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + sda_x <= '1'; + sda <= '1'; + + scl_x <= '1'; + scl <= '1'; + else + sda_x <= sda_i; + sda <= sda_x; + + scl_x <= scl_i; + scl <= scl_x; + end if; + end if; + end process PROC_I2C_LINES_SYNC; + + PROC_I2C_MASTER_TRANSFER: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + i2c_busy <= '1'; + startstop_select <= '0'; + startstop_seq_start <= '0'; + sendbyte_seq_start <= '0'; + readbyte_seq_start <= '0'; + sendbyte_byte <= (others => '0'); + i2c_data <= (others => '0'); + read_seq_ctr <= '0'; + STATE <= S_RESET; + else + i2c_busy <= i2c_busy_x; + startstop_select <= startstop_select_x; + startstop_seq_start <= startstop_seq_start_x; + sendbyte_seq_start <= sendbyte_seq_start_x; + readbyte_seq_start <= readbyte_seq_start_x; + sendbyte_byte <= sendbyte_byte_x; + i2c_data <= i2c_data_x; + read_seq_ctr <= read_seq_ctr_x; + STATE <= NEXT_STATE; + end if; + end if; + end process PROC_I2C_MASTER_TRANSFER; + + + PROC_I2C_MASTER: process(STATE, + i2c_start, + startstop_done, + read_seq_ctr, + sendbyte_done, + sendbyte_ack, + readbyte_done, + startstop_done + ) + + begin + -- Defaults + sda_master <= '1'; + scl_master <= '1'; + i2c_busy_x <= '1'; + startstop_select_x <= '0'; + startstop_seq_start_x <= '0'; + sendbyte_seq_start_x <= '0'; + sendbyte_byte_x <= (others => '0'); + readbyte_seq_start_x <= '0'; + i2c_data_x <= i2c_data; + read_seq_ctr_x <= read_seq_ctr; + + case STATE is + + when S_RESET => + i2c_data_x <= (others => '0'); + NEXT_STATE <= S_IDLE; + + when S_IDLE => + if (i2c_start = '1') then + i2c_data_x <= x"8000_0000"; -- Set Running, clear all + -- other bits + NEXT_STATE <= S_START; + else + i2c_busy_x <= '0'; + i2c_data_x <= i2c_data and x"7fff_ffff"; -- clear running + -- bit; + read_seq_ctr_x <= '0'; + NEXT_STATE <= S_IDLE; + end if; + + -- I2C START Sequence + when S_START => + startstop_select_x <= '1'; + startstop_seq_start_x <= '1'; + NEXT_STATE <= S_START_WAIT; + + when S_START_WAIT => + if (startstop_done = '0') then + NEXT_STATE <= S_START_WAIT; + else + sda_master <= '0'; + scl_master <= '0'; + NEXT_STATE <= S_SEND_CHIP_ID; + end if; + + -- I2C SEND ChipId Sequence + when S_SEND_CHIP_ID => + scl_master <= '0'; + sendbyte_byte_x(7 downto 1) <= i2c_chipid; + if (read_seq_ctr = '0') then + sendbyte_byte_x(0) <= '0'; + else + sendbyte_byte_x(0) <= '1'; + end if; + sendbyte_seq_start_x <= '1'; + NEXT_STATE <= S_SEND_CHIP_ID_WAIT; + + when S_SEND_CHIP_ID_WAIT => + if (sendbyte_done = '0') then + NEXT_STATE <= S_SEND_CHIP_ID_WAIT; + else + scl_master <= '0'; + if (sendbyte_ack = '0') then + i2c_data_x <= i2c_data or x"0100_0000"; + NEXT_STATE <= S_STOP; + else + if (read_seq_ctr = '0') then + read_seq_ctr_x <= '1'; + NEXT_STATE <= S_SEND_REGISTER; + else + NEXT_STATE <= S_GET_DATA; + end if; + end if; + end if; + + -- I2C SEND RegisterId + when S_SEND_REGISTER => + scl_master <= '0'; + sendbyte_byte_x <= i2c_registerid; + sendbyte_seq_start_x <= '1'; + NEXT_STATE <= S_SEND_REGISTER_WAIT; + + when S_SEND_REGISTER_WAIT => + if (sendbyte_done = '0') then + NEXT_STATE <= S_SEND_REGISTER_WAIT; + else + scl_master <= '0'; + if (sendbyte_ack = '0') then + i2c_data_x <= i2c_data or x"0200_0000"; + NEXT_STATE <= S_STOP; + else + if (i2c_rw_bit = '0') then + NEXT_STATE <= S_SEND_DATA; + else + NEXT_STATE <= S_START; + end if; + end if; + end if; + + -- I2C SEND DataWord + when S_SEND_DATA => + scl_master <= '0'; + sendbyte_byte_x <= i2c_register_data; + sendbyte_seq_start_x <= '1'; + NEXT_STATE <= S_SEND_DATA_WAIT; + + when S_SEND_DATA_WAIT => + if (sendbyte_done = '0') then + NEXT_STATE <= S_SEND_DATA_WAIT; + else + scl_master <= '0'; + if (sendbyte_ack = '0') then + i2c_data_x <= i2c_data or x"0400_0000"; + end if; + NEXT_STATE <= S_STOP; + end if; + + -- I2C GET DataWord + when S_GET_DATA => + scl_master <= '0'; + readbyte_seq_start_x <= '1'; + NEXT_STATE <= S_GET_DATA_WAIT; + + when S_GET_DATA_WAIT => + if (readbyte_done = '0') then + NEXT_STATE <= S_GET_DATA_WAIT; + else + scl_master <= '0'; + i2c_data_x(7 downto 0)<= readbyte_byte; + NEXT_STATE <= S_STOP; + end if; + + -- I2C STOP Sequence + when S_STOP => + sda_master <= '0'; + scl_master <= '0'; + startstop_select_x <= '0'; + startstop_seq_start_x <= '1'; + NEXT_STATE <= S_STOP_WAIT; + + when S_STOP_WAIT => + if (startstop_done = '0') then + NEXT_STATE <= S_STOP_WAIT; + else + i2c_data_x <= i2c_data or x"4000_0000"; -- Set DONE Bit + NEXT_STATE <= S_IDLE; + end if; + + end case; + end process PROC_I2C_MASTER; + + PROC_I2C_DATA_MULTIPLEXER: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + i2c_data_internal_o <= (others => '0'); + i2c_data_slave <= (others => '0'); + command_busy_o <= '0'; + else + if (internal_command = '0' and internal_command_d = '0') then + i2c_data_slave <= i2c_data; + else + i2c_data_internal_o <= i2c_data; + end if; + end if; + command_busy_o <= i2c_busy; + end if; + end process PROC_I2C_DATA_MULTIPLEXER; + + ----------------------------------------------------------------------------- + -- TRBNet Slave Bus + ----------------------------------------------------------------------------- + -- + -- Write bit definition + -- ==================== + -- + -- D[31] I2C_GO 0 => don't do anything on I2C, + -- 1 => start I2C access + -- D[30] I2C_ACTION 0 => write byte, 1 => read byte + -- D[29:24] I2C_SPEED set all to '1' + -- D[23:16] I2C_ADDRESS address of I2C chip + -- D[15:8] I2C_CMD command byte for access + -- D[7:0] I2C_DATA data to be written + -- + -- Read bit definition + -- =================== + -- + -- D[31] RUNNING whatever + -- D[30] I2C_DONE whatever + -- D[29] ERROR_RADDACK no acknowledge for repeated address byte + -- D[28] ERROR_RSTART generation of repeated START condition failed + -- D[27] ERROR_DATACK no acknowledge for data byte + -- D[26] ERROR_CMDACK no acknowledge for command byte + -- D[25] ERROR_ADDACK no acknowledge for address byte + -- D[24] ERROR_START generation of START condition failed + -- D[23:21] reserved reserved + -- D[20:16] debug subject to change, don't use + -- D[15:8] reserved reserved + -- D[7:0] I2C_DATA result of I2C read operation + -- + + PROC_SLAVE_BUS: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + slv_data_out_o <= (others => '0'); + slv_no_more_data_o <= '0'; + slv_unknown_addr_o <= '0'; + slv_ack_o <= '0'; + i2c_start <= '0'; + internal_command <= '0'; + internal_command_d <= '0'; + + i2c_chipid <= (others => '0'); + i2c_rw_bit <= '0'; + i2c_registerid <= (others => '0'); + i2c_register_data <= (others => '0'); + i2c_register_value_read <= (others => '0'); + + else + slv_unknown_addr_o <= '0'; + slv_no_more_data_o <= '0'; + slv_data_out_o <= (others => '0'); + i2c_start <= '0'; + + internal_command_d <= internal_command; + + if (i2c_busy = '0' and internal_command_d = '1') then + internal_command <= '0'; + slv_ack_o <= '0'; + + elsif (i2c_busy = '0' and INTERNAL_COMMAND_IN(31) = '1') then + -- Internal Interface Command + i2c_rw_bit <= INTERNAL_COMMAND_IN(30); + i2c_chipid <= INTERNAL_COMMAND_IN(22 downto 16); + i2c_registerid <= INTERNAL_COMMAND_IN(15 downto 8); + i2c_register_data <= INTERNAL_COMMAND_IN(7 downto 0); + i2c_start <= '1'; + internal_command <= '1'; + slv_ack_o <= '0'; + + elsif (SLV_WRITE_IN = '1') then + if (internal_command = '0' and + I2C_LOCK_IN = '0' and + i2c_busy = '0' and + SLV_DATA_IN(31) = '1') then + i2c_rw_bit <= SLV_DATA_IN(30); + i2c_chipid <= SLV_DATA_IN(22 downto 16); + i2c_registerid <= SLV_DATA_IN(15 downto 8); + i2c_register_data <= SLV_DATA_IN(7 downto 0); + i2c_start <= '1'; + slv_ack_o <= '1'; + else + slv_no_more_data_o <= '1'; + slv_ack_o <= '0'; + end if; + + elsif (SLV_READ_IN = '1') then + if (internal_command = '0' and + I2C_LOCK_IN = '0' and + i2c_busy = '0') then + slv_data_out_o <= i2c_data_slave; + slv_ack_o <= '1'; + else + slv_data_out_o <= (others => '0'); + slv_no_more_data_o <= '1'; + slv_ack_o <= '0'; + end if; + + else + slv_ack_o <= '0'; + end if; + + end if; + end if; + end process PROC_SLAVE_BUS; + + + ----------------------------------------------------------------------------- + -- Output Signals + ----------------------------------------------------------------------------- + + -- I2C Outputs + sda_o <= (sda_master and + sda_startstop and + sda_sendbyte and + sda_readbyte + ); + SDA_INOUT <= '0' when (sda_o = '0') else 'Z'; + + scl_o <= (scl_master and + scl_startstop and + scl_sendbyte and + scl_readbyte + ); + SCL_INOUT <= '0' when (scl_o = '0') else 'Z'; + + COMMAND_BUSY_OUT <= command_busy_o; + I2C_DATA_OUT <= i2c_data_internal_o; + + -- Slave Bus + SLV_DATA_OUT <= slv_data_out_o; + SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; + SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o; + SLV_ACK_OUT <= slv_ack_o; + +end Behavioral; diff --git a/nxyter/source/nx_i2c_readbyte.vhd b/nxyter/source/nx_i2c_readbyte.vhd index 4a9d9ab..bee2a5e 100644 --- a/nxyter/source/nx_i2c_readbyte.vhd +++ b/nxyter/source/nx_i2c_readbyte.vhd @@ -1,241 +1,241 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.nxyter_components.all; - - -entity nx_i2c_readbyte is - generic ( - I2C_SPEED : unsigned(11 downto 0) := x"3e8" - ); - port( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - - START_IN : in std_logic; - BYTE_OUT : out std_logic_vector(7 downto 0); - SEQUENCE_DONE_OUT : out std_logic; - - -- I2C connections - SDA_OUT : out std_logic; - SCL_OUT : out std_logic; - SDA_IN : in std_logic - ); -end entity; - -architecture Behavioral of nx_i2c_readbyte is - - -- Send Byte - signal sda_o : std_logic; - signal scl_o : std_logic; - signal i2c_start : std_logic; - - signal sequence_done_o : std_logic; - signal i2c_byte : unsigned(7 downto 0); - signal bit_ctr : unsigned(3 downto 0); - signal i2c_ack_o : std_logic; - signal wait_timer_init : unsigned(11 downto 0); - - signal sequence_done_o_x : std_logic; - signal i2c_byte_x : unsigned(7 downto 0); - signal bit_ctr_x : unsigned(3 downto 0); - signal i2c_ack_o_x : std_logic; - signal wait_timer_init_x : unsigned(11 downto 0); - - type STATES is (S_IDLE, - S_INIT, - S_INIT_WAIT, - - S_READ_BYTE, - S_UNSET_SCL1, - S_SET_SCL1, - S_GET_BIT, - S_SET_SCL2, - S_UNSET_SCL2, - S_NEXT_BIT, - - S_NACK_SET, - S_NACK_SET_SCL, - S_NACK_UNSET_SCL - ); - signal STATE, NEXT_STATE : STATES; - - -- Wait Timer - signal wait_timer_done : std_logic; - -begin - - -- Timer - nx_timer_1: nx_timer - generic map( - CTR_WIDTH => 12 - ) - port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - TIMER_START_IN => wait_timer_init, - TIMER_DONE_OUT => wait_timer_done - ); - - - PROC_READ_BYTE_TRANSFER: process(CLK_IN) - begin - if( rising_edge(CLK_IN) ) then - if( RESET_IN = '1' ) then - sequence_done_o <= '0'; - bit_ctr <= (others => '0'); - i2c_ack_o <= '0'; - wait_timer_init <= (others => '0'); - STATE <= S_IDLE; - else - sequence_done_o <= sequence_done_o_x; - i2c_byte <= i2c_byte_x; - bit_ctr <= bit_ctr_x; - i2c_ack_o <= i2c_ack_o_x; - wait_timer_init <= wait_timer_init_x; - STATE <= NEXT_STATE; - end if; - end if; - end process PROC_READ_BYTE_TRANSFER; - - PROC_READ_BYTE: process(STATE, - START_IN, - wait_timer_done, - bit_ctr - ) - begin - sda_o <= '1'; - scl_o <= '1'; - sequence_done_o_x <= '0'; - i2c_byte_x <= i2c_byte; - bit_ctr_x <= bit_ctr; - i2c_ack_o_x <= i2c_ack_o; - wait_timer_init_x <= (others => '0'); - - case STATE is - when S_IDLE => - if (START_IN = '1') then - sda_o <= '0'; - scl_o <= '0'; - i2c_byte_x <= (others => '0'); - NEXT_STATE <= S_INIT; - else - NEXT_STATE <= S_IDLE; - end if; - - -- INIT - when S_INIT => - sda_o <= '0'; - scl_o <= '0'; - wait_timer_init_x <= I2C_SPEED srl 1; - NEXT_STATE <= S_INIT_WAIT; - - when S_INIT_WAIT => - sda_o <= '0'; - scl_o <= '0'; - if (wait_timer_done = '0') then - NEXT_STATE <= S_INIT_WAIT; - else - NEXT_STATE <= S_READ_BYTE; - end if; - - -- I2C Read byte - when S_READ_BYTE => - scl_o <= '0'; - bit_ctr_x <= x"7"; - wait_timer_init_x <= I2C_SPEED srl 2; - NEXT_STATE <= S_UNSET_SCL1; - - when S_UNSET_SCL1 => - scl_o <= '0'; - if (wait_timer_done = '0') then - NEXT_STATE <= S_UNSET_SCL1; - else - wait_timer_init_x <= I2C_SPEED srl 2; - NEXT_STATE <= S_SET_SCL1; - end if; - - when S_SET_SCL1 => - if (wait_timer_done = '0') then - NEXT_STATE <= S_SET_SCL1; - else - wait_timer_init_x <= I2C_SPEED srl 2; - NEXT_STATE <= S_GET_BIT; - end if; - - when S_GET_BIT => - i2c_byte_x(0) <= SDA_IN; - NEXT_STATE <= S_SET_SCL2; - - when S_SET_SCL2 => - if (wait_timer_done = '0') then - NEXT_STATE <= S_SET_SCL2; - else - wait_timer_init_x <= I2C_SPEED srl 2; - NEXT_STATE <= S_UNSET_SCL2; - end if; - - when S_UNSET_SCL2 => - scl_o <= '0'; - if (wait_timer_done = '0') then - NEXT_STATE <= S_UNSET_SCL2; - else - NEXT_STATE <= S_NEXT_BIT; - end if; - - when S_NEXT_BIT => - scl_o <= '0'; - if (bit_ctr > 0) then - bit_ctr_x <= bit_ctr - 1; - i2c_byte_x <= i2c_byte sll 1; - wait_timer_init_x <= I2C_SPEED srl 2; - NEXT_STATE <= S_UNSET_SCL1; - else - wait_timer_init_x <= I2C_SPEED srl 2; - NEXT_STATE <= S_NACK_SET; - end if; - - -- I2C Send NOT_ACK (NACK) Sequence to tell client to release the bus - when S_NACK_SET => - scl_o <= '0'; - if (wait_timer_done = '0') then - NEXT_STATE <= S_NACK_SET; - else - wait_timer_init_x <= I2C_SPEED srl 1; - NEXT_STATE <= S_NACK_SET_SCL; - end if; - - when S_NACK_SET_SCL => - if (wait_timer_done = '0') then - NEXT_STATE <= S_NACK_SET_SCL; - else - wait_timer_init_x <= I2C_SPEED srl 2; - NEXT_STATE <= S_NACK_UNSET_SCL; - end if; - - when S_NACK_UNSET_SCL => - scl_o <= '0'; - if (wait_timer_done = '0') then - NEXT_STATE <= S_NACK_UNSET_SCL; - else - sequence_done_o_x <= '1'; - NEXT_STATE <= S_IDLE; - end if; - - end case; - end process PROC_READ_BYTE; - - ----------------------------------------------------------------------------- - -- Output Signals - ----------------------------------------------------------------------------- - - SEQUENCE_DONE_OUT <= sequence_done_o; - BYTE_OUT <= i2c_byte; - - -- I2c Outputs - SDA_OUT <= sda_o; - SCL_OUT <= scl_o; - -end Behavioral; +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.nxyter_components.all; + + +entity nx_i2c_readbyte is + generic ( + I2C_SPEED : unsigned(11 downto 0) := x"3e8" + ); + port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + + START_IN : in std_logic; + BYTE_OUT : out std_logic_vector(7 downto 0); + SEQUENCE_DONE_OUT : out std_logic; + + -- I2C connections + SDA_OUT : out std_logic; + SCL_OUT : out std_logic; + SDA_IN : in std_logic + ); +end entity; + +architecture Behavioral of nx_i2c_readbyte is + + -- Send Byte + signal sda_o : std_logic; + signal scl_o : std_logic; + signal i2c_start : std_logic; + + signal sequence_done_o : std_logic; + signal i2c_byte : unsigned(7 downto 0); + signal bit_ctr : unsigned(3 downto 0); + signal i2c_ack_o : std_logic; + signal wait_timer_init : unsigned(11 downto 0); + + signal sequence_done_o_x : std_logic; + signal i2c_byte_x : unsigned(7 downto 0); + signal bit_ctr_x : unsigned(3 downto 0); + signal i2c_ack_o_x : std_logic; + signal wait_timer_init_x : unsigned(11 downto 0); + + type STATES is (S_IDLE, + S_INIT, + S_INIT_WAIT, + + S_READ_BYTE, + S_UNSET_SCL1, + S_SET_SCL1, + S_GET_BIT, + S_SET_SCL2, + S_UNSET_SCL2, + S_NEXT_BIT, + + S_NACK_SET, + S_NACK_SET_SCL, + S_NACK_UNSET_SCL + ); + signal STATE, NEXT_STATE : STATES; + + -- Wait Timer + signal wait_timer_done : std_logic; + +begin + + -- Timer + nx_timer_1: nx_timer + generic map( + CTR_WIDTH => 12 + ) + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + TIMER_START_IN => wait_timer_init, + TIMER_DONE_OUT => wait_timer_done + ); + + + PROC_READ_BYTE_TRANSFER: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + sequence_done_o <= '0'; + bit_ctr <= (others => '0'); + i2c_ack_o <= '0'; + wait_timer_init <= (others => '0'); + STATE <= S_IDLE; + else + sequence_done_o <= sequence_done_o_x; + i2c_byte <= i2c_byte_x; + bit_ctr <= bit_ctr_x; + i2c_ack_o <= i2c_ack_o_x; + wait_timer_init <= wait_timer_init_x; + STATE <= NEXT_STATE; + end if; + end if; + end process PROC_READ_BYTE_TRANSFER; + + PROC_READ_BYTE: process(STATE, + START_IN, + wait_timer_done, + bit_ctr + ) + begin + sda_o <= '1'; + scl_o <= '1'; + sequence_done_o_x <= '0'; + i2c_byte_x <= i2c_byte; + bit_ctr_x <= bit_ctr; + i2c_ack_o_x <= i2c_ack_o; + wait_timer_init_x <= (others => '0'); + + case STATE is + when S_IDLE => + if (START_IN = '1') then + sda_o <= '0'; + scl_o <= '0'; + i2c_byte_x <= (others => '0'); + NEXT_STATE <= S_INIT; + else + NEXT_STATE <= S_IDLE; + end if; + + -- INIT + when S_INIT => + sda_o <= '0'; + scl_o <= '0'; + wait_timer_init_x <= I2C_SPEED srl 1; + NEXT_STATE <= S_INIT_WAIT; + + when S_INIT_WAIT => + sda_o <= '0'; + scl_o <= '0'; + if (wait_timer_done = '0') then + NEXT_STATE <= S_INIT_WAIT; + else + NEXT_STATE <= S_READ_BYTE; + end if; + + -- I2C Read byte + when S_READ_BYTE => + scl_o <= '0'; + bit_ctr_x <= x"7"; + wait_timer_init_x <= I2C_SPEED srl 2; + NEXT_STATE <= S_UNSET_SCL1; + + when S_UNSET_SCL1 => + scl_o <= '0'; + if (wait_timer_done = '0') then + NEXT_STATE <= S_UNSET_SCL1; + else + wait_timer_init_x <= I2C_SPEED srl 2; + NEXT_STATE <= S_SET_SCL1; + end if; + + when S_SET_SCL1 => + if (wait_timer_done = '0') then + NEXT_STATE <= S_SET_SCL1; + else + wait_timer_init_x <= I2C_SPEED srl 2; + NEXT_STATE <= S_GET_BIT; + end if; + + when S_GET_BIT => + i2c_byte_x(0) <= SDA_IN; + NEXT_STATE <= S_SET_SCL2; + + when S_SET_SCL2 => + if (wait_timer_done = '0') then + NEXT_STATE <= S_SET_SCL2; + else + wait_timer_init_x <= I2C_SPEED srl 2; + NEXT_STATE <= S_UNSET_SCL2; + end if; + + when S_UNSET_SCL2 => + scl_o <= '0'; + if (wait_timer_done = '0') then + NEXT_STATE <= S_UNSET_SCL2; + else + NEXT_STATE <= S_NEXT_BIT; + end if; + + when S_NEXT_BIT => + scl_o <= '0'; + if (bit_ctr > 0) then + bit_ctr_x <= bit_ctr - 1; + i2c_byte_x <= i2c_byte sll 1; + wait_timer_init_x <= I2C_SPEED srl 2; + NEXT_STATE <= S_UNSET_SCL1; + else + wait_timer_init_x <= I2C_SPEED srl 2; + NEXT_STATE <= S_NACK_SET; + end if; + + -- I2C Send NOT_ACK (NACK) Sequence to tell client to release the bus + when S_NACK_SET => + scl_o <= '0'; + if (wait_timer_done = '0') then + NEXT_STATE <= S_NACK_SET; + else + wait_timer_init_x <= I2C_SPEED srl 1; + NEXT_STATE <= S_NACK_SET_SCL; + end if; + + when S_NACK_SET_SCL => + if (wait_timer_done = '0') then + NEXT_STATE <= S_NACK_SET_SCL; + else + wait_timer_init_x <= I2C_SPEED srl 2; + NEXT_STATE <= S_NACK_UNSET_SCL; + end if; + + when S_NACK_UNSET_SCL => + scl_o <= '0'; + if (wait_timer_done = '0') then + NEXT_STATE <= S_NACK_UNSET_SCL; + else + sequence_done_o_x <= '1'; + NEXT_STATE <= S_IDLE; + end if; + + end case; + end process PROC_READ_BYTE; + + ----------------------------------------------------------------------------- + -- Output Signals + ----------------------------------------------------------------------------- + + SEQUENCE_DONE_OUT <= sequence_done_o; + BYTE_OUT <= i2c_byte; + + -- I2c Outputs + SDA_OUT <= sda_o; + SCL_OUT <= scl_o; + +end Behavioral; diff --git a/nxyter/source/nx_i2c_sendbyte.vhd b/nxyter/source/nx_i2c_sendbyte.vhd index 03f525d..5a0eb4e 100644 --- a/nxyter/source/nx_i2c_sendbyte.vhd +++ b/nxyter/source/nx_i2c_sendbyte.vhd @@ -1,285 +1,285 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.nxyter_components.all; - - -entity nx_i2c_sendbyte is - generic ( - I2C_SPEED : unsigned(11 downto 0) := x"3e8" - ); - port( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - - START_IN : in std_logic; - BYTE_IN : in std_logic_vector(7 downto 0); - SEQUENCE_DONE_OUT : out std_logic; - - -- I2C connections - SDA_OUT : out std_logic; - SCL_OUT : out std_logic; - SDA_IN : in std_logic; - SCL_IN : in std_logic; - ACK_OUT : out std_logic - ); -end entity; - -architecture Behavioral of nx_i2c_sendbyte is - - -- Send Byte - signal sda_o : std_logic; - signal scl_o : std_logic; - signal i2c_start : std_logic; - - signal sequence_done_o : std_logic; - signal i2c_byte : unsigned(7 downto 0); - signal bit_ctr : unsigned(3 downto 0); - signal i2c_ack_o : std_logic; - signal wait_timer_init : unsigned(11 downto 0); - signal stretch_timeout : unsigned(19 downto 0); - - signal sequence_done_o_x : std_logic; - signal i2c_byte_x : unsigned(7 downto 0); - signal bit_ctr_x : unsigned(3 downto 0); - signal i2c_ack_o_x : std_logic; - signal wait_timer_init_x : unsigned(11 downto 0); - signal stretch_timeout_x : unsigned(19 downto 0); - - type STATES is (S_IDLE, - S_INIT, - S_INIT_WAIT, - - S_SEND_BYTE, - S_SET_SDA, - S_SET_SCL, - S_UNSET_SCL, - S_NEXT_BIT, - - S_ACK_UNSET_SCL, - S_ACK_SET_SCL, - S_STRETCH_CHECK_SCL, - S_STRETCH_WAIT_SCL, - S_STRETCH_PAUSE, - S_ACK_STORE, - S_ACK_UNSET_SCL2 - ); - signal STATE, NEXT_STATE : STATES; - - -- Wait Timer - signal wait_timer_done : std_logic; - -begin - - -- Timer - nx_timer_1: nx_timer - generic map ( - CTR_WIDTH => 12 - ) - port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - TIMER_START_IN => wait_timer_init, - TIMER_DONE_OUT => wait_timer_done - ); - - - PROC_SEND_BYTE_TRANSFER: process(CLK_IN) - begin - if( rising_edge(CLK_IN) ) then - if( RESET_IN = '1' ) then - sequence_done_o <= '0'; - bit_ctr <= (others => '0'); - i2c_ack_o <= '0'; - wait_timer_init <= (others => '0'); - stretch_timeout <= (others => '0'); - STATE <= S_IDLE; - else - sequence_done_o <= sequence_done_o_x; - i2c_byte <= i2c_byte_x; - bit_ctr <= bit_ctr_x; - i2c_ack_o <= i2c_ack_o_x; - wait_timer_init <= wait_timer_init_x; - stretch_timeout <= stretch_timeout_x; - STATE <= NEXT_STATE; - end if; - end if; - end process PROC_SEND_BYTE_TRANSFER; - - PROC_SEND_BYTE: process(STATE, - START_IN, - wait_timer_done, - bit_ctr - ) - begin - sda_o <= '1'; - scl_o <= '1'; - sequence_done_o_x <= '0'; - i2c_byte_x <= i2c_byte; - bit_ctr_x <= bit_ctr; - i2c_ack_o_x <= i2c_ack_o; - wait_timer_init_x <= (others => '0'); - stretch_timeout_x <= stretch_timeout; - - case STATE is - when S_IDLE => - if (START_IN = '1') then - sda_o <= '0'; - scl_o <= '0'; - i2c_byte_x <= BYTE_IN; - NEXT_STATE <= S_INIT; - else - NEXT_STATE <= S_IDLE; - end if; - - -- INIT - when S_INIT => - sda_o <= '0'; - scl_o <= '0'; - wait_timer_init_x <= I2C_SPEED srl 1; - NEXT_STATE <= S_INIT_WAIT; - - when S_INIT_WAIT => - sda_o <= '0'; - scl_o <= '0'; - if (wait_timer_done = '0') then - NEXT_STATE <= S_INIT_WAIT; - else - NEXT_STATE <= S_SEND_BYTE; - end if; - - -- I2C Send byte - when S_SEND_BYTE => - sda_o <= '0'; - scl_o <= '0'; - bit_ctr_x <= x"7"; - wait_timer_init_x <= I2C_SPEED srl 2; - NEXT_STATE <= S_SET_SDA; - - when S_SET_SDA => - sda_o <= i2c_byte(7); - scl_o <= '0'; - if (wait_timer_done = '0') then - NEXT_STATE <= S_SET_SDA; - else - wait_timer_init_x <= I2C_SPEED srl 1; - NEXT_STATE <= S_SET_SCL; - end if; - - when S_SET_SCL => - sda_o <= i2c_byte(7); - if (wait_timer_done = '0') then - NEXT_STATE <= S_SET_SCL; - else - wait_timer_init_x <= I2C_SPEED srl 2; - NEXT_STATE <= S_UNSET_SCL; - end if; - - when S_UNSET_SCL => - sda_o <= i2c_byte(7); - scl_o <= '0'; - if (wait_timer_done = '0') then - NEXT_STATE <= S_UNSET_SCL; - else - NEXT_STATE <= S_NEXT_BIT; - end if; - - when S_NEXT_BIT => - sda_o <= i2c_byte(7); - scl_o <= '0'; - if (bit_ctr > 0) then - bit_ctr_x <= bit_ctr - 1; - i2c_byte_x <= i2c_byte sll 1; - wait_timer_init_x <= I2C_SPEED srl 2; - NEXT_STATE <= S_SET_SDA; - else - wait_timer_init_x <= I2C_SPEED srl 2; - NEXT_STATE <= S_ACK_UNSET_SCL; - end if; - - -- Get Slave ACK bit - when S_ACK_UNSET_SCL => - scl_o <= '0'; - if (wait_timer_done = '0') then - NEXT_STATE <= S_ACK_UNSET_SCL; - else - wait_timer_init_x <= I2C_SPEED srl 2; - NEXT_STATE <= S_ACK_SET_SCL; - end if; - - when S_ACK_SET_SCL => - if (wait_timer_done = '0') then - NEXT_STATE <= S_ACK_SET_SCL; - else - NEXT_STATE <= S_STRETCH_CHECK_SCL; - end if; - - -- Check for Clock Stretching - when S_STRETCH_CHECK_SCL => - if (SCL_IN = '1') then - wait_timer_init_x <= I2C_SPEED srl 2; - NEXT_STATE <= S_ACK_STORE; - else - stretch_timeout_x <= (others => '0'); - NEXT_STATE <= S_STRETCH_WAIT_SCL; - end if; - - when S_STRETCH_WAIT_SCL => - if (SCL_IN = '0') then - if (stretch_timeout < x"30d40") then - stretch_timeout_x <= stretch_timeout + 1; - NEXT_STATE <= S_STRETCH_WAIT_SCL; - else - i2c_ack_o_x <= '0'; - wait_timer_init_x <= I2C_SPEED srl 2; - NEXT_STATE <= S_ACK_UNSET_SCL; - end if; - else - wait_timer_init_x <= I2C_SPEED srl 2; - NEXT_STATE <= S_STRETCH_PAUSE; - end if; - - when S_STRETCH_PAUSE => - if (wait_timer_done = '0') then - NEXT_STATE <= S_STRETCH_PAUSE; - else - wait_timer_init_x <= I2C_SPEED srl 2; - NEXT_STATE <= S_ACK_STORE; - end if; - - -- Read ACK Bit - when S_ACK_STORE => - if (wait_timer_done = '0') then - NEXT_STATE <= S_ACK_STORE; - else - i2c_ack_o_x <= not SDA_IN; - wait_timer_init_x <= I2C_SPEED srl 2; - NEXT_STATE <= S_ACK_UNSET_SCL2; - end if; - - when S_ACK_UNSET_SCL2 => - scl_o <= '0'; - if (wait_timer_done = '0') then - NEXT_STATE <= S_ACK_UNSET_SCL2; - else - sequence_done_o_x <= '1'; - NEXT_STATE <= S_IDLE; - end if; - - end case; - end process PROC_SEND_BYTE; - - ----------------------------------------------------------------------------- - -- Output Signals - ----------------------------------------------------------------------------- - - SEQUENCE_DONE_OUT <= sequence_done_o; - ACK_OUT <= i2c_ack_o; - - -- I2c Outputs - SDA_OUT <= sda_o; - SCL_OUT <= scl_o; - -end Behavioral; +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.nxyter_components.all; + + +entity nx_i2c_sendbyte is + generic ( + I2C_SPEED : unsigned(11 downto 0) := x"3e8" + ); + port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + + START_IN : in std_logic; + BYTE_IN : in std_logic_vector(7 downto 0); + SEQUENCE_DONE_OUT : out std_logic; + + -- I2C connections + SDA_OUT : out std_logic; + SCL_OUT : out std_logic; + SDA_IN : in std_logic; + SCL_IN : in std_logic; + ACK_OUT : out std_logic + ); +end entity; + +architecture Behavioral of nx_i2c_sendbyte is + + -- Send Byte + signal sda_o : std_logic; + signal scl_o : std_logic; + signal i2c_start : std_logic; + + signal sequence_done_o : std_logic; + signal i2c_byte : unsigned(7 downto 0); + signal bit_ctr : unsigned(3 downto 0); + signal i2c_ack_o : std_logic; + signal wait_timer_init : unsigned(11 downto 0); + signal stretch_timeout : unsigned(19 downto 0); + + signal sequence_done_o_x : std_logic; + signal i2c_byte_x : unsigned(7 downto 0); + signal bit_ctr_x : unsigned(3 downto 0); + signal i2c_ack_o_x : std_logic; + signal wait_timer_init_x : unsigned(11 downto 0); + signal stretch_timeout_x : unsigned(19 downto 0); + + type STATES is (S_IDLE, + S_INIT, + S_INIT_WAIT, + + S_SEND_BYTE, + S_SET_SDA, + S_SET_SCL, + S_UNSET_SCL, + S_NEXT_BIT, + + S_ACK_UNSET_SCL, + S_ACK_SET_SCL, + S_STRETCH_CHECK_SCL, + S_STRETCH_WAIT_SCL, + S_STRETCH_PAUSE, + S_ACK_STORE, + S_ACK_UNSET_SCL2 + ); + signal STATE, NEXT_STATE : STATES; + + -- Wait Timer + signal wait_timer_done : std_logic; + +begin + + -- Timer + nx_timer_1: nx_timer + generic map ( + CTR_WIDTH => 12 + ) + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + TIMER_START_IN => wait_timer_init, + TIMER_DONE_OUT => wait_timer_done + ); + + + PROC_SEND_BYTE_TRANSFER: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + sequence_done_o <= '0'; + bit_ctr <= (others => '0'); + i2c_ack_o <= '0'; + wait_timer_init <= (others => '0'); + stretch_timeout <= (others => '0'); + STATE <= S_IDLE; + else + sequence_done_o <= sequence_done_o_x; + i2c_byte <= i2c_byte_x; + bit_ctr <= bit_ctr_x; + i2c_ack_o <= i2c_ack_o_x; + wait_timer_init <= wait_timer_init_x; + stretch_timeout <= stretch_timeout_x; + STATE <= NEXT_STATE; + end if; + end if; + end process PROC_SEND_BYTE_TRANSFER; + + PROC_SEND_BYTE: process(STATE, + START_IN, + wait_timer_done, + bit_ctr + ) + begin + sda_o <= '1'; + scl_o <= '1'; + sequence_done_o_x <= '0'; + i2c_byte_x <= i2c_byte; + bit_ctr_x <= bit_ctr; + i2c_ack_o_x <= i2c_ack_o; + wait_timer_init_x <= (others => '0'); + stretch_timeout_x <= stretch_timeout; + + case STATE is + when S_IDLE => + if (START_IN = '1') then + sda_o <= '0'; + scl_o <= '0'; + i2c_byte_x <= BYTE_IN; + NEXT_STATE <= S_INIT; + else + NEXT_STATE <= S_IDLE; + end if; + + -- INIT + when S_INIT => + sda_o <= '0'; + scl_o <= '0'; + wait_timer_init_x <= I2C_SPEED srl 1; + NEXT_STATE <= S_INIT_WAIT; + + when S_INIT_WAIT => + sda_o <= '0'; + scl_o <= '0'; + if (wait_timer_done = '0') then + NEXT_STATE <= S_INIT_WAIT; + else + NEXT_STATE <= S_SEND_BYTE; + end if; + + -- I2C Send byte + when S_SEND_BYTE => + sda_o <= '0'; + scl_o <= '0'; + bit_ctr_x <= x"7"; + wait_timer_init_x <= I2C_SPEED srl 2; + NEXT_STATE <= S_SET_SDA; + + when S_SET_SDA => + sda_o <= i2c_byte(7); + scl_o <= '0'; + if (wait_timer_done = '0') then + NEXT_STATE <= S_SET_SDA; + else + wait_timer_init_x <= I2C_SPEED srl 1; + NEXT_STATE <= S_SET_SCL; + end if; + + when S_SET_SCL => + sda_o <= i2c_byte(7); + if (wait_timer_done = '0') then + NEXT_STATE <= S_SET_SCL; + else + wait_timer_init_x <= I2C_SPEED srl 2; + NEXT_STATE <= S_UNSET_SCL; + end if; + + when S_UNSET_SCL => + sda_o <= i2c_byte(7); + scl_o <= '0'; + if (wait_timer_done = '0') then + NEXT_STATE <= S_UNSET_SCL; + else + NEXT_STATE <= S_NEXT_BIT; + end if; + + when S_NEXT_BIT => + sda_o <= i2c_byte(7); + scl_o <= '0'; + if (bit_ctr > 0) then + bit_ctr_x <= bit_ctr - 1; + i2c_byte_x <= i2c_byte sll 1; + wait_timer_init_x <= I2C_SPEED srl 2; + NEXT_STATE <= S_SET_SDA; + else + wait_timer_init_x <= I2C_SPEED srl 2; + NEXT_STATE <= S_ACK_UNSET_SCL; + end if; + + -- Get Slave ACK bit + when S_ACK_UNSET_SCL => + scl_o <= '0'; + if (wait_timer_done = '0') then + NEXT_STATE <= S_ACK_UNSET_SCL; + else + wait_timer_init_x <= I2C_SPEED srl 2; + NEXT_STATE <= S_ACK_SET_SCL; + end if; + + when S_ACK_SET_SCL => + if (wait_timer_done = '0') then + NEXT_STATE <= S_ACK_SET_SCL; + else + NEXT_STATE <= S_STRETCH_CHECK_SCL; + end if; + + -- Check for Clock Stretching + when S_STRETCH_CHECK_SCL => + if (SCL_IN = '1') then + wait_timer_init_x <= I2C_SPEED srl 2; + NEXT_STATE <= S_ACK_STORE; + else + stretch_timeout_x <= (others => '0'); + NEXT_STATE <= S_STRETCH_WAIT_SCL; + end if; + + when S_STRETCH_WAIT_SCL => + if (SCL_IN = '0') then + if (stretch_timeout < x"30d40") then + stretch_timeout_x <= stretch_timeout + 1; + NEXT_STATE <= S_STRETCH_WAIT_SCL; + else + i2c_ack_o_x <= '0'; + wait_timer_init_x <= I2C_SPEED srl 2; + NEXT_STATE <= S_ACK_UNSET_SCL; + end if; + else + wait_timer_init_x <= I2C_SPEED srl 2; + NEXT_STATE <= S_STRETCH_PAUSE; + end if; + + when S_STRETCH_PAUSE => + if (wait_timer_done = '0') then + NEXT_STATE <= S_STRETCH_PAUSE; + else + wait_timer_init_x <= I2C_SPEED srl 2; + NEXT_STATE <= S_ACK_STORE; + end if; + + -- Read ACK Bit + when S_ACK_STORE => + if (wait_timer_done = '0') then + NEXT_STATE <= S_ACK_STORE; + else + i2c_ack_o_x <= not SDA_IN; + wait_timer_init_x <= I2C_SPEED srl 2; + NEXT_STATE <= S_ACK_UNSET_SCL2; + end if; + + when S_ACK_UNSET_SCL2 => + scl_o <= '0'; + if (wait_timer_done = '0') then + NEXT_STATE <= S_ACK_UNSET_SCL2; + else + sequence_done_o_x <= '1'; + NEXT_STATE <= S_IDLE; + end if; + + end case; + end process PROC_SEND_BYTE; + + ----------------------------------------------------------------------------- + -- Output Signals + ----------------------------------------------------------------------------- + + SEQUENCE_DONE_OUT <= sequence_done_o; + ACK_OUT <= i2c_ack_o; + + -- I2c Outputs + SDA_OUT <= sda_o; + SCL_OUT <= scl_o; + +end Behavioral; diff --git a/nxyter/source/nx_i2c_startstop.vhd b/nxyter/source/nx_i2c_startstop.vhd index b5b4a49..949fe9a 100644 --- a/nxyter/source/nx_i2c_startstop.vhd +++ b/nxyter/source/nx_i2c_startstop.vhd @@ -1,188 +1,188 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.nxyter_components.all; - -entity nx_i2c_startstop is - generic ( - I2C_SPEED : unsigned(11 downto 0) := x"3e8" - ); - port( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - - START_IN : in std_logic; -- Start Sequence - SELECT_IN : in std_logic; -- '1' -> Start, '0'-> Stop - SEQUENCE_DONE_OUT : out std_logic; - - -- I2C connections - SDA_OUT : out std_logic; - SCL_OUT : out std_logic; - NREADY_OUT : out std_logic - ); -end entity; - -architecture Behavioral of nx_i2c_startstop is - - -- I2C Bus - signal sda_o : std_logic; - signal scl_o : std_logic; - signal sequence_done_o : std_logic; - signal wait_timer_init : unsigned(11 downto 0); - - signal sequence_done_o_x : std_logic; - signal wait_timer_init_x : unsigned(11 downto 0); - - type STATES is (S_IDLE, - S_START, - S_WAIT_START_1, - S_WAIT_START_2, - S_WAIT_START_3, - - S_STOP, - S_WAIT_STOP_1, - S_WAIT_STOP_2, - S_WAIT_STOP_3 - ); - signal STATE, NEXT_STATE : STATES; - - -- I2C Timer - signal wait_timer_done : std_logic; - -begin - - -- Timer - nx_timer_1: nx_timer - generic map ( - CTR_WIDTH => 12 - ) - port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - TIMER_START_IN => wait_timer_init, - TIMER_DONE_OUT => wait_timer_done - ); - - PROC_START_STOP_TRANSFER: process(CLK_IN) - begin - if( rising_edge(CLK_IN) ) then - if( RESET_IN = '1' ) then - sequence_done_o <= '0'; - wait_timer_init <= (others => '0'); - STATE <= S_IDLE; - else - sequence_done_o <= sequence_done_o_x; - wait_timer_init <= wait_timer_init_x; - STATE <= NEXT_STATE; - end if; - end if; - end process PROC_START_STOP_TRANSFER; - - PROC_START_STOP: process(STATE, - START_IN, - SELECT_IN, - wait_timer_done - ) - begin - sda_o <= '1'; - scl_o <= '1'; - wait_timer_init_x <= (others => '0'); - sequence_done_o_x <= '0'; - - case STATE is - when S_IDLE => - if (START_IN = '1') then - if (SELECT_IN = '1') then - NEXT_STATE <= S_START; - else - sda_o <= '0'; - scl_o <= '0'; - NEXT_STATE <= S_STOP; - end if; - else - NEXT_STATE <= S_IDLE; - end if; - - -- I2C START Sequence - when S_START => - wait_timer_init_x <= I2C_SPEED srl 1; - NEXT_STATE <= S_WAIT_START_1; - - when S_WAIT_START_1 => - if (wait_timer_done = '0') then - NEXT_STATE <= S_WAIT_START_1; - else - wait_timer_init_x <= I2C_SPEED srl 1; - NEXT_STATE <= S_WAIT_START_2; - end if; - - when S_WAIT_START_2 => - sda_o <= '0'; - if (wait_timer_done = '0') then - NEXT_STATE <= S_WAIT_START_2; - else - wait_timer_init_x <= I2C_SPEED srl 1; - NEXT_STATE <= S_WAIT_START_3; - end if; - - when S_WAIT_START_3 => - sda_o <= '0'; - scl_o <= '0'; - if (wait_timer_done = '0') then - NEXT_STATE <= S_WAIT_START_3; - else - sequence_done_o_x <= '1'; - NEXT_STATE <= S_IDLE; - end if; - - -- I2C STOP Sequence - when S_STOP => - sda_o <= '0'; - scl_o <= '0'; - wait_timer_init_x <= I2C_SPEED srl 1; - NEXT_STATE <= S_WAIT_STOP_1; - - when S_WAIT_STOP_1 => - sda_o <= '0'; - scl_o <= '0'; - if (wait_timer_done = '0') then - NEXT_STATE <= S_WAIT_STOP_1; - else - wait_timer_init_x <= I2C_SPEED srl 1; - NEXT_STATE <= S_WAIT_STOP_2; - end if; - - when S_WAIT_STOP_2 => - sda_o <= '0'; - if (wait_timer_done = '0') then - NEXT_STATE <= S_WAIT_STOP_2; - else - wait_timer_init_x <= I2C_SPEED srl 1; - NEXT_STATE <= S_WAIT_STOP_3; - end if; - - when S_WAIT_STOP_3 => - if (wait_timer_done = '0') then - NEXT_STATE <= S_WAIT_STOP_3; - else - sequence_done_o_x <= '1'; - NEXT_STATE <= S_IDLE; - end if; - - end case; - end process PROC_START_STOP; - - - - ----------------------------------------------------------------------------- - -- Output Signals - ----------------------------------------------------------------------------- - - SEQUENCE_DONE_OUT <= sequence_done_o; - SDA_OUT <= sda_o; - SCL_OUT <= scl_o; - NREADY_OUT <= '0'; - -end Behavioral; +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.nxyter_components.all; + +entity nx_i2c_startstop is + generic ( + I2C_SPEED : unsigned(11 downto 0) := x"3e8" + ); + port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + + START_IN : in std_logic; -- Start Sequence + SELECT_IN : in std_logic; -- '1' -> Start, '0'-> Stop + SEQUENCE_DONE_OUT : out std_logic; + + -- I2C connections + SDA_OUT : out std_logic; + SCL_OUT : out std_logic; + NREADY_OUT : out std_logic + ); +end entity; + +architecture Behavioral of nx_i2c_startstop is + + -- I2C Bus + signal sda_o : std_logic; + signal scl_o : std_logic; + signal sequence_done_o : std_logic; + signal wait_timer_init : unsigned(11 downto 0); + + signal sequence_done_o_x : std_logic; + signal wait_timer_init_x : unsigned(11 downto 0); + + type STATES is (S_IDLE, + S_START, + S_WAIT_START_1, + S_WAIT_START_2, + S_WAIT_START_3, + + S_STOP, + S_WAIT_STOP_1, + S_WAIT_STOP_2, + S_WAIT_STOP_3 + ); + signal STATE, NEXT_STATE : STATES; + + -- I2C Timer + signal wait_timer_done : std_logic; + +begin + + -- Timer + nx_timer_1: nx_timer + generic map ( + CTR_WIDTH => 12 + ) + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + TIMER_START_IN => wait_timer_init, + TIMER_DONE_OUT => wait_timer_done + ); + + PROC_START_STOP_TRANSFER: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + sequence_done_o <= '0'; + wait_timer_init <= (others => '0'); + STATE <= S_IDLE; + else + sequence_done_o <= sequence_done_o_x; + wait_timer_init <= wait_timer_init_x; + STATE <= NEXT_STATE; + end if; + end if; + end process PROC_START_STOP_TRANSFER; + + PROC_START_STOP: process(STATE, + START_IN, + SELECT_IN, + wait_timer_done + ) + begin + sda_o <= '1'; + scl_o <= '1'; + wait_timer_init_x <= (others => '0'); + sequence_done_o_x <= '0'; + + case STATE is + when S_IDLE => + if (START_IN = '1') then + if (SELECT_IN = '1') then + NEXT_STATE <= S_START; + else + sda_o <= '0'; + scl_o <= '0'; + NEXT_STATE <= S_STOP; + end if; + else + NEXT_STATE <= S_IDLE; + end if; + + -- I2C START Sequence + when S_START => + wait_timer_init_x <= I2C_SPEED srl 1; + NEXT_STATE <= S_WAIT_START_1; + + when S_WAIT_START_1 => + if (wait_timer_done = '0') then + NEXT_STATE <= S_WAIT_START_1; + else + wait_timer_init_x <= I2C_SPEED srl 1; + NEXT_STATE <= S_WAIT_START_2; + end if; + + when S_WAIT_START_2 => + sda_o <= '0'; + if (wait_timer_done = '0') then + NEXT_STATE <= S_WAIT_START_2; + else + wait_timer_init_x <= I2C_SPEED srl 1; + NEXT_STATE <= S_WAIT_START_3; + end if; + + when S_WAIT_START_3 => + sda_o <= '0'; + scl_o <= '0'; + if (wait_timer_done = '0') then + NEXT_STATE <= S_WAIT_START_3; + else + sequence_done_o_x <= '1'; + NEXT_STATE <= S_IDLE; + end if; + + -- I2C STOP Sequence + when S_STOP => + sda_o <= '0'; + scl_o <= '0'; + wait_timer_init_x <= I2C_SPEED srl 1; + NEXT_STATE <= S_WAIT_STOP_1; + + when S_WAIT_STOP_1 => + sda_o <= '0'; + scl_o <= '0'; + if (wait_timer_done = '0') then + NEXT_STATE <= S_WAIT_STOP_1; + else + wait_timer_init_x <= I2C_SPEED srl 1; + NEXT_STATE <= S_WAIT_STOP_2; + end if; + + when S_WAIT_STOP_2 => + sda_o <= '0'; + if (wait_timer_done = '0') then + NEXT_STATE <= S_WAIT_STOP_2; + else + wait_timer_init_x <= I2C_SPEED srl 1; + NEXT_STATE <= S_WAIT_STOP_3; + end if; + + when S_WAIT_STOP_3 => + if (wait_timer_done = '0') then + NEXT_STATE <= S_WAIT_STOP_3; + else + sequence_done_o_x <= '1'; + NEXT_STATE <= S_IDLE; + end if; + + end case; + end process PROC_START_STOP; + + + + ----------------------------------------------------------------------------- + -- Output Signals + ----------------------------------------------------------------------------- + + SEQUENCE_DONE_OUT <= sequence_done_o; + SDA_OUT <= sda_o; + SCL_OUT <= scl_o; + NREADY_OUT <= '0'; + +end Behavioral; diff --git a/nxyter/source/nx_setup.vhd b/nxyter/source/nx_setup.vhd index 2a619df..dcc3209 100644 --- a/nxyter/source/nx_setup.vhd +++ b/nxyter/source/nx_setup.vhd @@ -1,624 +1,692 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; - -entity nx_setup is - port( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - - I2C_COMMAND_OUT : out std_logic_vector(31 downto 0); - I2C_COMMAND_BUSY_IN : in std_logic; - I2C_DATA_IN : in std_logic_vector(31 downto 0); - I2C_LOCK : out std_logic; - - SPI_COMMAND_OUT : out std_logic_vector(31 downto 0); - SPI_COMMAND_BUSY_IN : in std_logic; - SPI_DATA_IN : in std_logic_vector(31 downto 0); - SPI_LOCK : out std_logic; - - -- Slave bus - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_ADDR_IN : in std_logic_vector(15 downto 0); - SLV_ACK_OUT : out std_logic; - SLV_NO_MORE_DATA_OUT : out std_logic; - SLV_UNKNOWN_ADDR_OUT : out std_logic; - - -- Debug Line - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); -end entity; - -architecture Behavioral of nx_setup is - - -- Send I2C Command - type I2C_STATES is (I2C_IDLE, - I2C_WAIT_BUSY_HIGH, - I2C_WAIT_BUSY_LOW - ); - - signal I2C_STATE : I2C_STATES; - - signal spi_command_o : std_logic_vector(31 downto 0); - signal i2c_lock_o : std_logic; - signal i2c_command_o : std_logic_vector(31 downto 0); - signal i2c_command : std_logic_vector(31 downto 0); - signal i2c_command_busy : std_logic; - signal i2c_command_done : std_logic; - signal i2c_data : std_logic_vector(31 downto 0); - - -- Write I2C Registers - type W_STATES is (W_IDLE, - W_NEXT_REGISTER, - W_REGISTER, - W_WAIT_DONE - ); - - signal W_STATE, W_STATE_RETURN : W_STATES; - - - signal nx_write_i2c_command : std_logic_vector(31 downto 0); - signal nx_write_i2c_lock : std_logic; - signal w_register_ctr : unsigned(5 downto 0); - - -- Read I2C Registers - type R_STATES is (R_IDLE, - R_REGISTER, - R_NEXT_REGISTER, - R_WAIT_DONE - ); - - signal R_STATE, R_STATE_RETURN : R_STATES; - - signal nx_read_i2c_command : std_logic_vector(31 downto 0); - signal nx_read_i2c_lock : std_logic; - signal r_register_ctr : unsigned(5 downto 0); - - -- Write DAC I2C Registers - type DW_STATES is (DW_IDLE, - DW_NEXT_REGISTER, - DW_REGISTER, - DW_WAIT_DONE - ); - signal DW_STATE, DW_STATE_RETURN : DW_STATES; - - signal dac_write_i2c_command : std_logic_vector(31 downto 0); - signal dac_write_i2c_lock : std_logic; - signal w_fifo_ctr : unsigned(7 downto 0); - - -- Read DAC I2C Registers - type DR_STATES is (DR_IDLE, - DR_REGISTER, - DR_WRITE_BACK, - DR_NEXT_REGISTER, - DR_WAIT_DONE - ); - - signal DR_STATE, DR_STATE_RETURN : DR_STATES; - - - signal dac_read_i2c_command : std_logic_vector(31 downto 0); - signal dac_read_i2c_lock : std_logic; - signal r_fifo_ctr : unsigned(7 downto 0); - - -- TRBNet Slave Bus - signal slv_data_out_o : std_logic_vector(31 downto 0); - signal slv_no_more_data_o : std_logic; - signal slv_unknown_addr_o : std_logic; - signal slv_ack_o : std_logic; - - signal read_nx_i2c_all_start : std_logic; - signal write_nx_i2c_all_start : std_logic; - - signal read_dac_all_start : std_logic; - signal write_dac_all_start : std_logic; - - -- I2C Register Ram - type i2c_ram_t is array(0 to 45) of std_logic_vector(7 downto 0); - signal i2c_ram : i2c_ram_t; - signal i2c_ram_write_0 : std_logic; - signal i2c_ram_write_1 : std_logic; - signal i2c_ram_input_addr_0 : unsigned(5 downto 0); - signal i2c_ram_input_addr_1 : unsigned(5 downto 0); - signal i2c_ram_input_0 : std_logic_vector(7 downto 0); - signal i2c_ram_input_1 : std_logic_vector(7 downto 0); - - type register_access_type_t is array(0 to 45) of std_logic; - constant register_access_type : register_access_type_t := - ('1', '1', '1', '1', '1', '1', '1', '1', -- 0 -> 7 - '1', '1', '1', '1', '1', '1', '1', '1', -- 8 -> 15 - '1', '1', '1', '1', '1', '1', '1', '1', -- 16 -> 23 - '1', '1', '1', '1', '1', '1', '0', '0', -- 24 -> 31 - '1', '1', '0', '0', '0', '0', '1', '1', -- 32 -> 39 - '0', '0', '0', '1', '1', '1' -- 40 -> 45 - ); - - -- DAC Trim FIFO RAM - type dac_ram_t is array(0 to 129) of std_logic_vector(5 downto 0); - signal dac_ram : dac_ram_t; - signal dac_ram_write_0 : std_logic; - signal dac_ram_write_1 : std_logic; - signal dac_ram_input_addr_0 : unsigned(7 downto 0); - signal dac_ram_input_addr_1 : unsigned(7 downto 0); - signal dac_ram_input_0 : std_logic_vector(5 downto 0); - signal dac_ram_input_1 : std_logic_vector(5 downto 0); - - signal ctr : std_logic_vector(5 downto 0); - signal i2c_ram_write_d : std_logic; - signal dac_ram_write_d : std_logic; -begin - - ----------------------------------------------------------------------------- - -- DEBUG - ----------------------------------------------------------------------------- - - DEBUG_OUT(0) <= CLK_IN; - DEBUG_OUT(1) <= read_nx_i2c_all_start; - DEBUG_OUT(2) <= write_nx_i2c_all_start; - DEBUG_OUT(3) <= read_dac_all_start; - DEBUG_OUT(4) <= write_dac_all_start; - - DEBUG_OUT(5) <= i2c_lock_o; - DEBUG_OUT(6) <= i2c_command_busy; - DEBUG_OUT(7) <= i2c_command_done; - DEBUG_OUT(8) <= I2C_COMMAND_BUSY_IN; - - DEBUG_OUT(9) <= i2c_ram_write_d; - DEBUG_OUT(10) <= i2c_ram_write_0; - DEBUG_OUT(11) <= i2c_ram_write_1; - DEBUG_OUT(12) <= dac_ram_write_d; - DEBUG_OUT(13) <= dac_ram_write_0; - DEBUG_OUT(14) <= dac_ram_write_1; - DEBUG_OUT(15) <= '0'; - - --DEBUG_OUT(14 downto 9) <= ctr; - ctr <= std_logic_vector(r_register_ctr) or std_logic_vector(w_register_ctr); - - ----------------------------------------------------------------------------- - - PROC_I2C_RAM_WRITE_HANDLER: process(CLK_IN) - begin - if( rising_edge(CLK_IN) ) then - if( RESET_IN = '1' ) then - i2c_ram_write_d <= '0'; - else - i2c_ram_write_d <= '0'; - if (i2c_ram_write_0 = '1') then - i2c_ram(to_integer(i2c_ram_input_addr_0)) <= i2c_ram_input_0; - i2c_ram_write_d <= '1'; - elsif (i2c_ram_write_1 = '1') then - i2c_ram(to_integer(i2c_ram_input_addr_1)) <= i2c_ram_input_1; - i2c_ram_write_d <= '1'; - end if; - end if; - end if; - end process PROC_I2C_RAM_WRITE_HANDLER; - - PROC_DAC_RAM_WRITE_HANDLER: process(CLK_IN) - begin - if( rising_edge(CLK_IN) ) then - if( RESET_IN = '1' ) then - dac_ram_write_d <= '0'; - else - dac_ram_write_d <= '0'; - if (dac_ram_write_0 = '1') then - dac_ram(to_integer(dac_ram_input_addr_0)) <= dac_ram_input_0; - dac_ram_write_d <= '1'; - elsif (dac_ram_write_1 = '1') then - dac_ram(to_integer(dac_ram_input_addr_1)) <= dac_ram_input_1; - dac_ram_write_d <= '1'; - end if; - end if; - end if; - end process PROC_DAC_RAM_WRITE_HANDLER; - - ----------------------------------------------------------------------------- - - i2c_lock_o <= nx_write_i2c_lock or - nx_read_i2c_lock or - dac_read_i2c_lock; - i2c_command <= nx_write_i2c_command or - nx_read_i2c_command or - dac_read_i2c_command; - - PROC_SEND_I2C_COMMAND: process(CLK_IN) - begin - if( rising_edge(CLK_IN) ) then - if( RESET_IN = '1' ) then - i2c_command_o <= (others => '0'); - i2c_command_busy <= '0'; - i2c_command_done <= '0'; - i2c_data <= (others => '0'); - I2C_STATE <= I2C_IDLE; - else - i2c_command_o <= (others => '0'); - i2c_command_busy <= '0'; - i2c_command_done <= '0'; - - case I2C_STATE is - - when I2C_IDLE => - if (i2c_command(31) = '1') then - i2c_command_o <= i2c_command; - i2c_command_busy <= '1'; - I2C_STATE <= I2C_WAIT_BUSY_HIGH; - else - I2C_STATE <= I2C_IDLE; - end if; - - when I2C_WAIT_BUSY_HIGH => - if (I2C_COMMAND_BUSY_IN = '0') then - i2c_command_o <= i2c_command_o; - i2c_command_busy <= '1'; - I2C_STATE <= I2C_WAIT_BUSY_HIGH; - else - i2c_command_busy <= '1'; - I2C_STATE <= I2C_WAIT_BUSY_LOW; - end if; - - when I2C_WAIT_BUSY_LOW => - if (I2C_COMMAND_BUSY_IN = '1') then - i2c_command_busy <= '1'; - I2C_STATE <= I2C_WAIT_BUSY_LOW; - else - i2c_data <= I2C_DATA_IN; - i2c_command_done <= '1'; - i2c_command_busy <= '1'; - I2C_STATE <= I2C_IDLE; - end if; - end case; - - end if; - end if; - end process PROC_SEND_I2C_COMMAND; - - ----------------------------------------------------------------------------- - - PROC_READ_NX_REGISTERS: process(CLK_IN) - begin - if( rising_edge(CLK_IN) ) then - if( RESET_IN = '1' ) then - nx_read_i2c_command <= (others => '0'); - nx_read_i2c_lock <= '0'; - i2c_ram_input_0 <= (others => '0'); - i2c_ram_input_addr_0 <= (others => '0'); - i2c_ram_write_0 <= '0'; - r_register_ctr <= (others => '0'); - - R_STATE_RETURN <= R_IDLE; - R_STATE <= R_IDLE; - else - nx_read_i2c_command <= (others => '0'); - nx_read_i2c_lock <= '1'; - i2c_ram_input_0 <= (others => '0'); - i2c_ram_input_addr_0 <= (others => '0'); - i2c_ram_write_0 <= '0'; - - case R_STATE is - when R_IDLE => - if (read_nx_i2c_all_start = '1') then - R_STATE <= R_REGISTER; - else - nx_read_i2c_lock <= '0'; - R_STATE <= R_IDLE; - end if; - r_register_ctr <= (others => '0'); - - when R_REGISTER => - if (register_access_type(to_integer(r_register_ctr)) = '1') then - nx_read_i2c_command(31 downto 16) <= x"ff08"; - nx_read_i2c_command(15 downto 14) <= (others => '0'); - nx_read_i2c_command(13 downto 8) <= r_register_ctr; - nx_read_i2c_command( 7 downto 0) <= (others => '0'); - R_STATE_RETURN <= R_NEXT_REGISTER; - R_STATE <= R_WAIT_DONE; - else - R_STATE <= R_NEXT_REGISTER; - end if; - - when R_NEXT_REGISTER => - if (register_access_type(to_integer(r_register_ctr)) = '1') then - i2c_ram_input_0 <= i2c_data(7 downto 0); - else - i2c_ram_input_0 <= x"be"; - end if; - i2c_ram_input_addr_0 <= r_register_ctr; - i2c_ram_write_0 <= '1'; - - if (r_register_ctr <= x"2d") then - r_register_ctr <= r_register_ctr + 1; - R_STATE <= R_REGISTER; - else - R_STATE <= R_IDLE; - end if; - - when R_WAIT_DONE => - if (i2c_command_done = '0') then - R_STATE <= R_WAIT_DONE; - else - R_STATE <= R_STATE_RETURN; - end if; - - end case; - end if; - end if; - end process PROC_READ_NX_REGISTERS; - - PROC_WRITE_NX_REGISTERS: process(CLK_IN) - begin - if( rising_edge(CLK_IN) ) then - if( RESET_IN = '1' ) then - nx_write_i2c_lock <= '0'; - nx_write_i2c_command <= (others => '0'); - w_register_ctr <= (others => '0'); - - W_STATE_RETURN <= W_IDLE; - W_STATE <= W_IDLE; - else - nx_write_i2c_command <= (others => '0'); - nx_write_i2c_lock <= '1'; - - case W_STATE is - - when W_IDLE => - if (write_nx_i2c_all_start = '1') then - W_STATE <= W_NEXT_REGISTER; - else - nx_write_i2c_lock <= '0'; - W_STATE <= W_IDLE; - end if; - w_register_ctr <= (others => '0'); - - when W_NEXT_REGISTER => - if (w_register_ctr <= x"2d") then - W_STATE <= W_REGISTER; - else - W_STATE <= W_IDLE; - end if; - - when W_REGISTER => - if (register_access_type( - to_integer(unsigned(w_register_ctr))) = '1') - then - nx_write_i2c_command(31 downto 16) <= x"bf08"; - nx_write_i2c_command(15 downto 14) <= (others => '0'); - nx_write_i2c_command(13 downto 8) <= w_register_ctr; - nx_write_i2c_command( 7 downto 0) <= - i2c_ram(to_integer(unsigned(w_register_ctr))); - W_STATE_RETURN <= W_NEXT_REGISTER; - W_STATE <= W_WAIT_DONE; - else - W_STATE <= W_NEXT_REGISTER; - end if; - - w_register_ctr <= w_register_ctr + 1; - - when W_WAIT_DONE => - if (i2c_command_done = '0') then - W_STATE <= W_WAIT_DONE; - else - W_STATE <= W_STATE_RETURN; - end if; - - end case; - end if; - end if; - end process PROC_WRITE_NX_REGISTERS; - - ----------------------------------------------------------------------------- - - PROC_READ_DAC_REGISTERS: process(CLK_IN) - begin - if( rising_edge(CLK_IN) ) then - if( RESET_IN = '1' ) then - dac_read_i2c_command <= (others => '0'); - dac_read_i2c_lock <= '0'; - dac_ram_write_0 <= '0'; - dac_ram_input_addr_0 <= (others => '0'); - dac_ram_input_0 <= (others => '0'); - r_fifo_ctr <= (others => '0'); - - DR_STATE_RETURN <= DR_IDLE; - DR_STATE <= DR_IDLE; - else - dac_read_i2c_command <= (others => '0'); - dac_read_i2c_lock <= '1'; - dac_ram_write_0 <= '0'; - dac_ram_input_addr_0 <= (others => '0'); - dac_ram_input_0 <= (others => '0'); - - case DR_STATE is - when DR_IDLE => - if (read_dac_all_start = '1') then - DR_STATE <= DR_REGISTER; - else - dac_read_i2c_lock <= '0'; - DR_STATE <= DR_IDLE; - end if; - r_fifo_ctr <= (others => '0'); - - when DR_REGISTER => - dac_read_i2c_command(31 downto 16) <= x"ff08"; - dac_read_i2c_command(15 downto 8) <= x"2a"; -- DAC Reg 42 - dac_read_i2c_command(7 downto 0) <= (others => '0'); - DR_STATE_RETURN <= DR_WRITE_BACK; - DR_STATE <= DR_WAIT_DONE; - - when DR_WRITE_BACK => - -- Store FIFO Entry - dac_ram_input_0 <= i2c_data(5 downto 0); - dac_ram_input_addr_0 <= r_fifo_ctr; - dac_ram_write_0 <= '1'; - - -- Write Data Back to FIFO - dac_read_i2c_command(31 downto 16) <= x"bf08"; - dac_read_i2c_command(15 downto 8) <= x"2a"; -- DAC Reg 42 - dac_read_i2c_command(4 downto 0) <= i2c_data(4 downto 0); - dac_read_i2c_command(7 downto 5) <= (others => '0'); - DR_STATE_RETURN <= DR_NEXT_REGISTER; - DR_STATE <= DR_WAIT_DONE; - - when DR_NEXT_REGISTER => - if (r_fifo_ctr <= x"81") then - r_fifo_ctr <= r_fifo_ctr + 1; - DR_STATE <= DR_REGISTER; - else - DR_STATE <= DR_IDLE; - end if; - - when DR_WAIT_DONE => - if (i2c_command_done = '0') then - DR_STATE <= DR_WAIT_DONE; - else - DR_STATE <= DR_STATE_RETURN; - end if; - - end case; - end if; - end if; - end process PROC_READ_DAC_REGISTERS; - - ----------------------------------------------------------------------------- - - PROC_SLAVE_BUS: process(CLK_IN) - variable mem_address : unsigned(7 downto 0) := x"00"; - - begin - if( rising_edge(CLK_IN) ) then - if( RESET_IN = '1' ) then - slv_data_out_o <= (others => '0'); - slv_no_more_data_o <= '0'; - slv_unknown_addr_o <= '0'; - slv_ack_o <= '0'; - - read_nx_i2c_all_start <= '0'; - write_nx_i2c_all_start <= '0'; - read_dac_all_start <= '0'; - write_dac_all_start <= '0'; - - i2c_ram_input_1 <= (others => '0'); - i2c_ram_input_addr_1 <= (others => '0'); - i2c_ram_write_1 <= '0'; - dac_ram_input_1 <= (others => '0'); - dac_ram_input_addr_1 <= (others => '0'); - dac_ram_write_1 <= '0'; - else - slv_data_out_o <= (others => '0'); - slv_unknown_addr_o <= '0'; - slv_no_more_data_o <= '0'; - - read_nx_i2c_all_start <= '0'; - write_nx_i2c_all_start <= '0'; - read_dac_all_start <= '0'; - write_dac_all_start <= '0'; - - i2c_ram_input_1 <= (others => '0'); - i2c_ram_input_addr_1 <= (others => '0'); - i2c_ram_write_1 <= '0'; - dac_ram_input_1 <= (others => '0'); - dac_ram_input_addr_1 <= (others => '0'); - dac_ram_write_1 <= '0'; - - if (SLV_WRITE_IN = '1') then - if (SLV_ADDR_IN >= x"0000" and SLV_ADDR_IN <= x"002d") then - if (i2c_lock_o = '1') then - slv_no_more_data_o <= '1'; - slv_ack_o <= '0'; - else - if (register_access_type( - to_integer(unsigned(SLV_ADDR_IN(5 downto 0)))) = '1') - then - -- Write value to ram - i2c_ram_input_1 <= SLV_DATA_IN(7 downto 0); - i2c_ram_input_addr_1 <= unsigned(SLV_ADDR_IN(5 downto 0)); - i2c_ram_write_1 <= '1'; - slv_ack_o <= '1'; - end if; - slv_ack_o <= '1'; - end if; - - elsif (SLV_ADDR_IN >= x"0060" and SLV_ADDR_IN <= x"00e0") then - if (i2c_lock_o = '1') then - slv_no_more_data_o <= '1'; - slv_ack_o <= '0'; - else - -- Write value to ram - mem_address := unsigned(SLV_ADDR_IN(7 downto 0)) - x"60"; - dac_ram_input_1 <= SLV_DATA_IN(5 downto 0); - dac_ram_input_addr_1 <= SLV_ADDR_IN(7 downto 0); - dac_ram_write_1 <= '1'; - slv_ack_o <= '1'; - end if; - - else - case SLV_ADDR_IN is - when x"0040" => - read_nx_i2c_all_start <= '1'; - slv_ack_o <= '1'; - - when x"0041" => - write_nx_i2c_all_start <= '1'; - slv_ack_o <= '1'; - - when x"0042" => - read_dac_all_start <= '1'; - slv_ack_o <= '1'; - - when x"0043" => - write_dac_all_start <= '1'; - slv_ack_o <= '1'; - - when others => - slv_unknown_addr_o <= '1'; - slv_ack_o <= '0'; - - end case; - end if; - - elsif (SLV_READ_IN = '1') then - if (SLV_ADDR_IN >= x"0000" and SLV_ADDR_IN <= x"002d") then - slv_data_out_o(7 downto 0) <= - i2c_ram(to_integer(unsigned(SLV_ADDR_IN(5 downto 0)))); - slv_data_out_o(31 downto 8) <= (others => '0'); - slv_ack_o <= '1'; - elsif (SLV_ADDR_IN >= x"0060" and SLV_ADDR_IN <= x"00e0") then - mem_address := unsigned(SLV_ADDR_IN(7 downto 0)) - x"60"; - slv_data_out_o(5 downto 0) <= dac_ram(to_integer(mem_address)); - slv_data_out_o(31 downto 6) <= (others => '0'); - slv_ack_o <= '1'; - else - slv_unknown_addr_o <= '1'; - slv_ack_o <= '0'; - end if; - else - slv_ack_o <= '0'; - end if; - - end if; - end if; - end process PROC_SLAVE_BUS; - - ----------------------------------------------------------------------------- - -- Output Signals - ----------------------------------------------------------------------------- - - I2C_COMMAND_OUT <= i2c_command_o; - I2C_LOCK <= i2c_lock_o; - - SPI_COMMAND_OUT <= spi_command_o; - spi_command_o <= (others => '0'); - - -- Slave Bus - SLV_DATA_OUT <= slv_data_out_o; - SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; - SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o; - SLV_ACK_OUT <= slv_ack_o; - -end Behavioral; +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; + +entity nx_setup is + port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + + I2C_COMMAND_OUT : out std_logic_vector(31 downto 0); + I2C_COMMAND_BUSY_IN : in std_logic; + I2C_DATA_IN : in std_logic_vector(31 downto 0); + I2C_LOCK : out std_logic; + + SPI_COMMAND_OUT : out std_logic_vector(31 downto 0); + SPI_COMMAND_BUSY_IN : in std_logic; + SPI_DATA_IN : in std_logic_vector(31 downto 0); + SPI_LOCK : out std_logic; + + -- Slave bus + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ADDR_IN : in std_logic_vector(15 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic; + + -- Debug Line + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); +end entity; + +architecture Behavioral of nx_setup is + + -- Send I2C Command + type I2C_STATES is (I2C_IDLE, + I2C_WAIT_BUSY_HIGH, + I2C_WAIT_BUSY_LOW + ); + + signal I2C_STATE : I2C_STATES; + + signal spi_command_o : std_logic_vector(31 downto 0); + signal i2c_lock_o : std_logic; + signal i2c_command_o : std_logic_vector(31 downto 0); + signal i2c_command : std_logic_vector(31 downto 0); + signal i2c_command_busy : std_logic; + signal i2c_command_done : std_logic; + signal i2c_data : std_logic_vector(31 downto 0); + + -- Read I2C Registers + type R_STATES is (R_IDLE, + R_REGISTER, + R_REGISTER_STORE, + R_NEXT_REGISTER, + R_WAIT_DONE + ); + + signal R_STATE, R_STATE_RETURN : R_STATES; + + signal nx_read_i2c_command : std_logic_vector(31 downto 0); + signal nx_read_i2c_lock : std_logic; + signal r_register_ctr : unsigned(5 downto 0); + + -- Write I2C Registers + type W_STATES is (W_IDLE, + W_REGISTER, + W_NEXT_REGISTER, + W_WAIT_DONE + ); + + signal W_STATE, W_STATE_RETURN : W_STATES; + + + signal nx_write_i2c_command : std_logic_vector(31 downto 0); + signal nx_write_i2c_lock : std_logic; + signal w_register_ctr : unsigned(5 downto 0); + + + -- Read DAC I2C Registers + type DR_STATES is (DR_IDLE, + DR_REGISTER, + DR_WRITE_BACK, + DR_NEXT_REGISTER, + DR_WAIT_DONE + ); + + signal DR_STATE, DR_STATE_RETURN : DR_STATES; + + + signal dac_read_i2c_command : std_logic_vector(31 downto 0); + signal dac_read_i2c_lock : std_logic; + signal r_fifo_ctr : unsigned(7 downto 0); + + -- Write DAC I2C Registers + type DW_STATES is (DW_IDLE, + DW_REGISTER, + DW_WRITE_BACK, + DW_NEXT_REGISTER, + DW_WAIT_DONE + ); + signal DW_STATE, DW_STATE_RETURN : DW_STATES; + + signal dac_write_i2c_command : std_logic_vector(31 downto 0); + signal dac_write_i2c_lock : std_logic; + signal w_fifo_ctr : unsigned(7 downto 0); + + + -- TRBNet Slave Bus + signal slv_data_out_o : std_logic_vector(31 downto 0); + signal slv_no_more_data_o : std_logic; + signal slv_unknown_addr_o : std_logic; + signal slv_ack_o : std_logic; + + signal read_nx_i2c_all_start : std_logic; + signal write_nx_i2c_all_start : std_logic; + + signal read_dac_all_start : std_logic; + signal write_dac_all_start : std_logic; + + -- I2C Register Ram + type i2c_ram_t is array(0 to 45) of std_logic_vector(7 downto 0); + signal i2c_ram : i2c_ram_t; + signal i2c_ram_write_0 : std_logic; + signal i2c_ram_write_1 : std_logic; + signal i2c_ram_input_addr_0 : unsigned(5 downto 0); + signal i2c_ram_input_addr_1 : unsigned(5 downto 0); + signal i2c_ram_input_0 : std_logic_vector(7 downto 0); + signal i2c_ram_input_1 : std_logic_vector(7 downto 0); + + type register_access_type_t is array(0 to 45) of std_logic; + constant register_access_type : register_access_type_t := + ('1', '1', '1', '1', '1', '1', '1', '1', -- 0 -> 7 + '1', '1', '1', '1', '1', '1', '1', '1', -- 8 -> 15 + '1', '1', '1', '1', '1', '1', '1', '1', -- 16 -> 23 + '1', '1', '1', '1', '1', '1', '0', '0', -- 24 -> 31 + '1', '1', '0', '0', '0', '0', '1', '1', -- 32 -> 39 + '0', '0', '0', '1', '1', '1' -- 40 -> 45 + ); + + -- DAC Trim FIFO RAM + type dac_ram_t is array(0 to 130) of std_logic_vector(5 downto 0); + signal dac_ram : dac_ram_t; + signal dac_ram_write_0 : std_logic; + signal dac_ram_write_1 : std_logic; + signal dac_ram_input_addr_0 : unsigned(7 downto 0); + signal dac_ram_input_addr_1 : unsigned(7 downto 0); + signal dac_ram_input_0 : std_logic_vector(5 downto 0); + signal dac_ram_input_1 : std_logic_vector(5 downto 0); + + signal ctr : std_logic_vector(5 downto 0); + signal i2c_ram_write_d : std_logic; + signal dac_ram_write_d : std_logic; +begin + + ----------------------------------------------------------------------------- + -- DEBUG + ----------------------------------------------------------------------------- + + DEBUG_OUT(0) <= CLK_IN; + DEBUG_OUT(1) <= read_nx_i2c_all_start; + DEBUG_OUT(2) <= write_nx_i2c_all_start; + DEBUG_OUT(3) <= read_dac_all_start; + DEBUG_OUT(4) <= write_dac_all_start; + + DEBUG_OUT(5) <= i2c_lock_o; + DEBUG_OUT(6) <= i2c_command_busy; + DEBUG_OUT(7) <= i2c_command_done; + DEBUG_OUT(8) <= I2C_COMMAND_BUSY_IN; + + DEBUG_OUT(9) <= i2c_ram_write_d; + DEBUG_OUT(10) <= i2c_ram_write_0; + DEBUG_OUT(11) <= i2c_ram_write_1; + DEBUG_OUT(12) <= dac_ram_write_d; + DEBUG_OUT(13) <= dac_ram_write_0; + DEBUG_OUT(14) <= dac_ram_write_1; + DEBUG_OUT(15) <= '0'; + + --DEBUG_OUT(14 downto 9) <= ctr; + ctr <= std_logic_vector(r_register_ctr) or std_logic_vector(w_register_ctr); + + ----------------------------------------------------------------------------- + + PROC_I2C_RAM_WRITE_HANDLER: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + i2c_ram_write_d <= '0'; + else + i2c_ram_write_d <= '0'; + if (i2c_ram_write_0 = '1') then + i2c_ram(to_integer(i2c_ram_input_addr_0)) <= i2c_ram_input_0; + i2c_ram_write_d <= '1'; + elsif (i2c_ram_write_1 = '1') then + i2c_ram(to_integer(i2c_ram_input_addr_1)) <= i2c_ram_input_1; + i2c_ram_write_d <= '1'; + end if; + end if; + end if; + end process PROC_I2C_RAM_WRITE_HANDLER; + + PROC_DAC_RAM_WRITE_HANDLER: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + dac_ram_write_d <= '0'; + else + dac_ram_write_d <= '0'; + if (dac_ram_write_0 = '1') then + dac_ram(to_integer(dac_ram_input_addr_0)) <= dac_ram_input_0; + dac_ram_write_d <= '1'; + elsif (dac_ram_write_1 = '1') then + dac_ram(to_integer(dac_ram_input_addr_1)) <= dac_ram_input_1; + dac_ram_write_d <= '1'; + end if; + end if; + end if; + end process PROC_DAC_RAM_WRITE_HANDLER; + + ----------------------------------------------------------------------------- + + i2c_lock_o <= nx_write_i2c_lock or + nx_read_i2c_lock or + dac_read_i2c_lock or + dac_write_i2c_lock; + i2c_command <= nx_write_i2c_command or + nx_read_i2c_command or + dac_read_i2c_command or + dac_write_i2c_command; + + PROC_SEND_I2C_COMMAND: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + i2c_command_o <= (others => '0'); + i2c_command_busy <= '0'; + i2c_command_done <= '0'; + i2c_data <= (others => '0'); + I2C_STATE <= I2C_IDLE; + else + i2c_command_o <= (others => '0'); + i2c_command_busy <= '0'; + i2c_command_done <= '0'; + + case I2C_STATE is + + when I2C_IDLE => + if (i2c_command(31) = '1') then + i2c_command_o <= i2c_command; + i2c_command_busy <= '1'; + I2C_STATE <= I2C_WAIT_BUSY_HIGH; + else + I2C_STATE <= I2C_IDLE; + end if; + + when I2C_WAIT_BUSY_HIGH => + if (I2C_COMMAND_BUSY_IN = '0') then + i2c_command_o <= i2c_command_o; + i2c_command_busy <= '1'; + I2C_STATE <= I2C_WAIT_BUSY_HIGH; + else + i2c_command_busy <= '1'; + I2C_STATE <= I2C_WAIT_BUSY_LOW; + end if; + + when I2C_WAIT_BUSY_LOW => + if (I2C_COMMAND_BUSY_IN = '1') then + i2c_command_busy <= '1'; + I2C_STATE <= I2C_WAIT_BUSY_LOW; + else + i2c_data <= I2C_DATA_IN; + i2c_command_done <= '1'; + i2c_command_busy <= '1'; + I2C_STATE <= I2C_IDLE; + end if; + end case; + + end if; + end if; + end process PROC_SEND_I2C_COMMAND; + + ----------------------------------------------------------------------------- + + PROC_READ_NX_REGISTERS: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + nx_read_i2c_command <= (others => '0'); + nx_read_i2c_lock <= '0'; + i2c_ram_input_0 <= (others => '0'); + i2c_ram_input_addr_0 <= (others => '0'); + i2c_ram_write_0 <= '0'; + r_register_ctr <= (others => '0'); + + R_STATE_RETURN <= R_IDLE; + R_STATE <= R_IDLE; + else + nx_read_i2c_command <= (others => '0'); + nx_read_i2c_lock <= '1'; + i2c_ram_input_0 <= (others => '0'); + i2c_ram_input_addr_0 <= (others => '0'); + i2c_ram_write_0 <= '0'; + + case R_STATE is + when R_IDLE => + if (read_nx_i2c_all_start = '1') then + R_STATE <= R_REGISTER; + else + nx_read_i2c_lock <= '0'; + R_STATE <= R_IDLE; + end if; + r_register_ctr <= (others => '0'); + + when R_REGISTER => + if (register_access_type(to_integer(r_register_ctr)) = '1') then + nx_read_i2c_command(31 downto 16) <= x"ff08"; + nx_read_i2c_command(15 downto 14) <= (others => '0'); + nx_read_i2c_command(13 downto 8) <= r_register_ctr; + nx_read_i2c_command( 7 downto 0) <= (others => '0'); + R_STATE_RETURN <= R_REGISTER_STORE; + R_STATE <= R_WAIT_DONE; + else + R_STATE <= R_REGISTER_STORE; + end if; + + when R_REGISTER_STORE => + if (register_access_type(to_integer(r_register_ctr)) = '1') then + i2c_ram_input_0 <= i2c_data(7 downto 0); + else + i2c_ram_input_0 <= x"be"; + end if; + i2c_ram_input_addr_0 <= r_register_ctr; + i2c_ram_write_0 <= '1'; + r_register_ctr <= r_register_ctr + 1; + R_STATE <= R_NEXT_REGISTER; + + when R_NEXT_REGISTER => + if (r_register_ctr < x"2e") then + R_STATE <= R_REGISTER; + else + R_STATE <= R_IDLE; + end if; + + when R_WAIT_DONE => + if (i2c_command_done = '0') then + R_STATE <= R_WAIT_DONE; + else + R_STATE <= R_STATE_RETURN; + end if; + + end case; + end if; + end if; + end process PROC_READ_NX_REGISTERS; + + PROC_WRITE_NX_REGISTERS: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + nx_write_i2c_lock <= '0'; + nx_write_i2c_command <= (others => '0'); + w_register_ctr <= (others => '0'); + + W_STATE_RETURN <= W_IDLE; + W_STATE <= W_IDLE; + else + nx_write_i2c_command <= (others => '0'); + nx_write_i2c_lock <= '1'; + + case W_STATE is + + when W_IDLE => + if (write_nx_i2c_all_start = '1') then + W_STATE <= W_REGISTER; + else + nx_write_i2c_lock <= '0'; + W_STATE <= W_IDLE; + end if; + w_register_ctr <= (others => '0'); + + when W_REGISTER => + if (register_access_type( + to_integer(unsigned(w_register_ctr))) = '1') + then + nx_write_i2c_command(31 downto 16) <= x"bf08"; + nx_write_i2c_command(15 downto 14) <= (others => '0'); + nx_write_i2c_command(13 downto 8) <= w_register_ctr; + nx_write_i2c_command( 7 downto 0) <= + i2c_ram(to_integer(unsigned(w_register_ctr))); + W_STATE_RETURN <= W_NEXT_REGISTER; + W_STATE <= W_WAIT_DONE; + else + W_STATE <= W_NEXT_REGISTER; + end if; + w_register_ctr <= w_register_ctr + 1; + + when W_NEXT_REGISTER => + if (w_register_ctr < x"2e") then + W_STATE <= W_REGISTER; + else + W_STATE <= W_IDLE; + end if; + + when W_WAIT_DONE => + if (i2c_command_done = '0') then + W_STATE <= W_WAIT_DONE; + else + W_STATE <= W_STATE_RETURN; + end if; + + end case; + end if; + end if; + end process PROC_WRITE_NX_REGISTERS; + + ----------------------------------------------------------------------------- + + PROC_READ_DAC_REGISTERS: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + dac_read_i2c_command <= (others => '0'); + dac_read_i2c_lock <= '0'; + dac_ram_write_0 <= '0'; + dac_ram_input_addr_0 <= (others => '0'); + dac_ram_input_0 <= (others => '0'); + r_fifo_ctr <= (others => '0'); + + DR_STATE_RETURN <= DR_IDLE; + DR_STATE <= DR_IDLE; + else + dac_read_i2c_command <= (others => '0'); + dac_read_i2c_lock <= '1'; + dac_ram_write_0 <= '0'; + dac_ram_input_addr_0 <= (others => '0'); + dac_ram_input_0 <= (others => '0'); + + case DR_STATE is + when DR_IDLE => + if (read_dac_all_start = '1') then + DR_STATE <= DR_REGISTER; + else + dac_read_i2c_lock <= '0'; + DR_STATE <= DR_IDLE; + end if; + r_fifo_ctr <= (others => '0'); + + when DR_REGISTER => + dac_read_i2c_command(31 downto 16) <= x"ff08"; + dac_read_i2c_command(15 downto 8) <= x"2a"; -- DAC Reg 42 + dac_read_i2c_command(7 downto 0) <= (others => '0'); + DR_STATE_RETURN <= DR_WRITE_BACK; + DR_STATE <= DR_WAIT_DONE; + + when DR_WRITE_BACK => + -- Store FIFO Entry + dac_ram_input_0 <= i2c_data(5 downto 0); + dac_ram_input_addr_0 <= r_fifo_ctr; + dac_ram_write_0 <= '1'; + + -- Write Data Back to FIFO + dac_read_i2c_command(31 downto 16) <= x"bf08"; + dac_read_i2c_command(15 downto 8) <= x"2a"; -- DAC Reg 42 + dac_read_i2c_command(5 downto 0) <= i2c_data(5 downto 0); + dac_read_i2c_command(7 downto 6) <= (others => '0'); + r_fifo_ctr <= r_fifo_ctr + 1; + DR_STATE_RETURN <= DR_NEXT_REGISTER; + DR_STATE <= DR_WAIT_DONE; + + when DR_NEXT_REGISTER => + if (r_fifo_ctr < x"81") then + DR_STATE <= DR_REGISTER; + else + DR_STATE <= DR_IDLE; + end if; + + when DR_WAIT_DONE => + if (i2c_command_done = '0') then + DR_STATE <= DR_WAIT_DONE; + else + DR_STATE <= DR_STATE_RETURN; + end if; + + end case; + end if; + end if; + end process PROC_READ_DAC_REGISTERS; + + PROC_WRITE_DAC_REGISTERS: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + dac_write_i2c_command <= (others => '0'); + dac_write_i2c_lock <= '0'; + w_fifo_ctr <= (others => '0'); + + DW_STATE_RETURN <= DW_IDLE; + DW_STATE <= DW_IDLE; + else + dac_write_i2c_command <= (others => '0'); + dac_write_i2c_lock <= '1'; + + case DW_STATE is + when DW_IDLE => + if (write_dac_all_start = '1') then + DW_STATE <= DW_REGISTER; + else + dac_write_i2c_lock <= '0'; + DW_STATE <= DW_IDLE; + end if; + w_fifo_ctr <= (others => '0'); + + when DW_REGISTER => + dac_write_i2c_command(31 downto 16) <= x"ff08"; + dac_write_i2c_command(15 downto 8) <= x"2a"; -- DAC Reg 42 + dac_write_i2c_command(7 downto 0) <= (others => '0'); + DW_STATE_RETURN <= DW_WRITE_BACK; + DW_STATE <= DW_WAIT_DONE; + + when DW_WRITE_BACK => + -- Write Data Back to FIFO + dac_write_i2c_command(31 downto 16) <= x"bf08"; + dac_write_i2c_command(15 downto 8) <= x"2a"; -- DAC Reg 42 + dac_write_i2c_command(7 downto 6) <= (others => '0'); + dac_write_i2c_command(5 downto 0) <= + dac_ram(to_integer(w_fifo_ctr)); + w_fifo_ctr <= w_fifo_ctr + 1; + DW_STATE_RETURN <= DW_NEXT_REGISTER; + DW_STATE <= DW_WAIT_DONE; + + when DW_NEXT_REGISTER => + if (w_fifo_ctr < x"81") then + DW_STATE <= DW_REGISTER; + else + DW_STATE <= DW_IDLE; + end if; + + when DW_WAIT_DONE => + if (i2c_command_done = '0') then + DW_STATE <= DW_WAIT_DONE; + else + DW_STATE <= DW_STATE_RETURN; + end if; + + end case; + end if; + end if; + end process PROC_WRITE_DAC_REGISTERS; + + ----------------------------------------------------------------------------- + + PROC_SLAVE_BUS: process(CLK_IN) + variable mem_address : unsigned(7 downto 0) := x"00"; + + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + slv_data_out_o <= (others => '0'); + slv_no_more_data_o <= '0'; + slv_unknown_addr_o <= '0'; + slv_ack_o <= '0'; + + read_nx_i2c_all_start <= '0'; + write_nx_i2c_all_start <= '0'; + read_dac_all_start <= '0'; + write_dac_all_start <= '0'; + + i2c_ram_input_1 <= (others => '0'); + i2c_ram_input_addr_1 <= (others => '0'); + i2c_ram_write_1 <= '0'; + dac_ram_input_1 <= (others => '0'); + dac_ram_input_addr_1 <= (others => '0'); + dac_ram_write_1 <= '0'; + else + slv_data_out_o <= (others => '0'); + slv_unknown_addr_o <= '0'; + slv_no_more_data_o <= '0'; + + read_nx_i2c_all_start <= '0'; + write_nx_i2c_all_start <= '0'; + read_dac_all_start <= '0'; + write_dac_all_start <= '0'; + + i2c_ram_input_1 <= (others => '0'); + i2c_ram_input_addr_1 <= (others => '0'); + i2c_ram_write_1 <= '0'; + dac_ram_input_1 <= (others => '0'); + dac_ram_input_addr_1 <= (others => '0'); + dac_ram_write_1 <= '0'; + + if (SLV_WRITE_IN = '1') then + if (SLV_ADDR_IN >= x"0000" and SLV_ADDR_IN <= x"002d") then + if (i2c_lock_o = '1') then + slv_no_more_data_o <= '1'; + slv_ack_o <= '0'; + else + if (register_access_type( + to_integer(unsigned(SLV_ADDR_IN(5 downto 0)))) = '1') + then + -- Write value to ram + i2c_ram_input_1 <= SLV_DATA_IN(7 downto 0); + i2c_ram_input_addr_1 <= unsigned(SLV_ADDR_IN(5 downto 0)); + i2c_ram_write_1 <= '1'; + slv_ack_o <= '1'; + end if; + slv_ack_o <= '1'; + end if; + + elsif (SLV_ADDR_IN >= x"0060" and SLV_ADDR_IN <= x"00e0") then + if (i2c_lock_o = '1') then + slv_no_more_data_o <= '1'; + slv_ack_o <= '0'; + else + -- Write value to ram + mem_address := unsigned(SLV_ADDR_IN(7 downto 0)) - x"60"; + dac_ram_input_1 <= SLV_DATA_IN(5 downto 0); + dac_ram_input_addr_1 <= mem_address; + dac_ram_write_1 <= '1'; + slv_ack_o <= '1'; + end if; + + else + case SLV_ADDR_IN is + when x"0040" => + read_nx_i2c_all_start <= '1'; + slv_ack_o <= '1'; + + when x"0041" => + write_nx_i2c_all_start <= '1'; + slv_ack_o <= '1'; + + when x"0042" => + read_dac_all_start <= '1'; + slv_ack_o <= '1'; + + when x"0043" => + write_dac_all_start <= '1'; + slv_ack_o <= '1'; + + when others => + slv_unknown_addr_o <= '1'; + slv_ack_o <= '0'; + + end case; + end if; + + elsif (SLV_READ_IN = '1') then + if (SLV_ADDR_IN >= x"0000" and SLV_ADDR_IN <= x"002d") then + slv_data_out_o(7 downto 0) <= + i2c_ram(to_integer(unsigned(SLV_ADDR_IN(5 downto 0)))); + slv_data_out_o(31 downto 8) <= (others => '0'); + slv_ack_o <= '1'; + elsif (SLV_ADDR_IN >= x"0060" and SLV_ADDR_IN <= x"00e0") then + mem_address := unsigned(SLV_ADDR_IN(7 downto 0)) - x"60"; + slv_data_out_o(5 downto 0) <= dac_ram(to_integer(mem_address)); + slv_data_out_o(31 downto 6) <= (others => '0'); + slv_ack_o <= '1'; + else + slv_unknown_addr_o <= '1'; + slv_ack_o <= '0'; + end if; + else + slv_ack_o <= '0'; + end if; + + end if; + end if; + end process PROC_SLAVE_BUS; + + ----------------------------------------------------------------------------- + -- Output Signals + ----------------------------------------------------------------------------- + + I2C_COMMAND_OUT <= i2c_command_o; + I2C_LOCK <= i2c_lock_o; + + SPI_COMMAND_OUT <= spi_command_o; + spi_command_o <= (others => '0'); + + -- Slave Bus + SLV_DATA_OUT <= slv_data_out_o; + SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; + SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o; + SLV_ACK_OUT <= slv_ack_o; + +end Behavioral; diff --git a/nxyter/source/nx_timer.vhd b/nxyter/source/nx_timer.vhd index 520818b..23993ea 100644 --- a/nxyter/source/nx_timer.vhd +++ b/nxyter/source/nx_timer.vhd @@ -1,79 +1,79 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity nx_timer is - generic ( - CTR_WIDTH : integer := 12 - ); - port( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - - TIMER_START_IN : in unsigned(CTR_WIDTH - 1 downto 0); - TIMER_DONE_OUT : out std_logic - ); -end entity; - -architecture Behavioral of nx_timer is - - -- Timer - signal timer_ctr : unsigned(CTR_WIDTH - 1 downto 0); - signal timer_done_o : std_logic; - - type STATES is (S_IDLE, - S_COUNT, - S_DONE - ); - signal STATE : STATES; - -begin - - PROC_TIMER: process(CLK_IN) - begin - if( rising_edge(CLK_IN) ) then - if( RESET_IN = '1' ) then - timer_ctr <= (others => '0'); - timer_done_o <= '0'; - STATE <= S_IDLE; - else - timer_done_o <= '0'; - - if (TIMER_START_IN > 0) then - timer_ctr <= TIMER_START_IN; - STATE <= S_COUNT; - else - case STATE is - when S_IDLE => - if (TIMER_START_IN = 0) then - STATE <= S_IDLE; - else - timer_ctr <= TIMER_START_IN; - STATE <= S_COUNT; - end if; - - when S_COUNT => - if (timer_ctr > 0) then - timer_ctr <= timer_ctr - 1; - STATE <= S_COUNT; - else - STATE <= S_DONE; - end if; - - when S_DONE => - timer_done_o <= '1'; - STATE <= S_IDLE; - - end case; - end if; - end if; - end if; - end process PROC_TIMER; - - ----------------------------------------------------------------------------- - -- Output Signals - ----------------------------------------------------------------------------- - - TIMER_DONE_OUT <= timer_done_o; - -end Behavioral; +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity nx_timer is + generic ( + CTR_WIDTH : integer := 12 + ); + port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + + TIMER_START_IN : in unsigned(CTR_WIDTH - 1 downto 0); + TIMER_DONE_OUT : out std_logic + ); +end entity; + +architecture Behavioral of nx_timer is + + -- Timer + signal timer_ctr : unsigned(CTR_WIDTH - 1 downto 0); + signal timer_done_o : std_logic; + + type STATES is (S_IDLE, + S_COUNT, + S_DONE + ); + signal STATE : STATES; + +begin + + PROC_TIMER: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + timer_ctr <= (others => '0'); + timer_done_o <= '0'; + STATE <= S_IDLE; + else + timer_done_o <= '0'; + + if (TIMER_START_IN > 0) then + timer_ctr <= TIMER_START_IN; + STATE <= S_COUNT; + else + case STATE is + when S_IDLE => + if (TIMER_START_IN = 0) then + STATE <= S_IDLE; + else + timer_ctr <= TIMER_START_IN; + STATE <= S_COUNT; + end if; + + when S_COUNT => + if (timer_ctr > 0) then + timer_ctr <= timer_ctr - 1; + STATE <= S_COUNT; + else + STATE <= S_DONE; + end if; + + when S_DONE => + timer_done_o <= '1'; + STATE <= S_IDLE; + + end case; + end if; + end if; + end if; + end process PROC_TIMER; + + ----------------------------------------------------------------------------- + -- Output Signals + ----------------------------------------------------------------------------- + + TIMER_DONE_OUT <= timer_done_o; + +end Behavioral; diff --git a/nxyter/source/nx_timestamp_sim.vhd b/nxyter/source/nx_timestamp_sim.vhd index fb94d01..133f368 100644 --- a/nxyter/source/nx_timestamp_sim.vhd +++ b/nxyter/source/nx_timestamp_sim.vhd @@ -1,101 +1,101 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.nxyter_components.all; - -entity nxyter_timestamp_sim is - port( - CLK_IN : in std_logic; -- Clock 128MHz - RESET_IN : in std_logic; - - TIMESTAMP_OUT : out std_logic_vector(7 downto 0); - CLK128_OUT : out std_logic - ); -end entity; - -architecture Behavioral of nxyter_timestamp_sim is - - signal timestamp_n : std_logic_vector(7 downto 0); - signal timestamp_g : std_logic_vector(7 downto 0); - signal counter : unsigned(1 downto 0); - signal counter2 : unsigned(3 downto 0); - signal counter3 : unsigned(1 downto 0); - -begin - - PROC_NX_TIMESTAMP: process(CLK_IN) - begin - if( rising_edge(CLK_IN) ) then - if( RESET_IN = '1' ) then - timestamp_n <= (others => '0'); - counter <= (others => '0'); - counter2 <= (others => '0'); - counter3 <= (others => '0'); - - else - - if (counter3 /= 0) then - case counter is - when "11" => timestamp_n <= x"06"; - counter3 <= counter3 + 1; - - when "10" => timestamp_n <= x"7f"; - - when "01" => timestamp_n <= x"7f"; - - when "00" => timestamp_n <= x"7f"; - end case; - - else - case counter is - when "11" => - timestamp_n(7) <= '0'; - timestamp_n(6 downto 4) <= (others => '0'); - timestamp_n(3 downto 0) <= counter2; - counter3 <= counter3 + 1; - - when "10" => - timestamp_n(7) <= '0'; - timestamp_n(6 downto 4) <= (others => '0'); - timestamp_n(3 downto 0) <= counter2; - - when "01" => - timestamp_n(7) <= '0'; - timestamp_n(6 downto 4) <= (others => '0'); - timestamp_n(3 downto 0) <= counter2; - - when "00" => - timestamp_n(7) <= '0'; - timestamp_n(6 downto 4) <= (others => '0'); - timestamp_n(3 downto 0) <= counter2; - - end case; - counter2 <= counter2 + 1; - end if; - - counter <= counter + 1; - end if; - end if; - end process PROC_NX_TIMESTAMP; - --- Gray_Encoder_1: Gray_Encoder --- generic map ( --- WIDTH => 8 --- ) --- port map ( --- CLK_IN => CLK_IN, --- RESET_IN => RESET_IN, --- BINARY_IN => timestamp_n, --- GRAY_OUT => timestamp_g --- ); --- --- timestamp_g <= timestamp_n; - - --- Output Signals - TIMESTAMP_OUT <= timestamp_n; - CLK128_OUT <= CLK_IN; - -end Behavioral; +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.nxyter_components.all; + +entity nxyter_timestamp_sim is + port( + CLK_IN : in std_logic; -- Clock 128MHz + RESET_IN : in std_logic; + + TIMESTAMP_OUT : out std_logic_vector(7 downto 0); + CLK128_OUT : out std_logic + ); +end entity; + +architecture Behavioral of nxyter_timestamp_sim is + + signal timestamp_n : std_logic_vector(7 downto 0); + signal timestamp_g : std_logic_vector(7 downto 0); + signal counter : unsigned(1 downto 0); + signal counter2 : unsigned(3 downto 0); + signal counter3 : unsigned(1 downto 0); + +begin + + PROC_NX_TIMESTAMP: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + timestamp_n <= (others => '0'); + counter <= (others => '0'); + counter2 <= (others => '0'); + counter3 <= (others => '0'); + + else + + if (counter3 /= 0) then + case counter is + when "11" => timestamp_n <= x"06"; + counter3 <= counter3 + 1; + + when "10" => timestamp_n <= x"7f"; + + when "01" => timestamp_n <= x"7f"; + + when "00" => timestamp_n <= x"7f"; + end case; + + else + case counter is + when "11" => + timestamp_n(7) <= '0'; + timestamp_n(6 downto 4) <= (others => '0'); + timestamp_n(3 downto 0) <= counter2; + counter3 <= counter3 + 1; + + when "10" => + timestamp_n(7) <= '0'; + timestamp_n(6 downto 4) <= (others => '0'); + timestamp_n(3 downto 0) <= counter2; + + when "01" => + timestamp_n(7) <= '0'; + timestamp_n(6 downto 4) <= (others => '0'); + timestamp_n(3 downto 0) <= counter2; + + when "00" => + timestamp_n(7) <= '0'; + timestamp_n(6 downto 4) <= (others => '0'); + timestamp_n(3 downto 0) <= counter2; + + end case; + counter2 <= counter2 + 1; + end if; + + counter <= counter + 1; + end if; + end if; + end process PROC_NX_TIMESTAMP; + +-- Gray_Encoder_1: Gray_Encoder +-- generic map ( +-- WIDTH => 8 +-- ) +-- port map ( +-- CLK_IN => CLK_IN, +-- RESET_IN => RESET_IN, +-- BINARY_IN => timestamp_n, +-- GRAY_OUT => timestamp_g +-- ); +-- +-- timestamp_g <= timestamp_n; + + +-- Output Signals + TIMESTAMP_OUT <= timestamp_n; + CLK128_OUT <= CLK_IN; + +end Behavioral; diff --git a/nxyter/source/nx_trigger_generator.vhd b/nxyter/source/nx_trigger_generator.vhd index b6dbb89..d23c3bb 100644 --- a/nxyter/source/nx_trigger_generator.vhd +++ b/nxyter/source/nx_trigger_generator.vhd @@ -1,261 +1,362 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.nxyter_components.all; - -entity nx_trigger_generator is - port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - - TRIGGER_IN : in std_logic; - - TRIGGER_OUT : out std_logic; - TS_RESET_OUT : out std_logic; - TESTPULSE_OUT : out std_logic; - - -- Slave bus - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_ADDR_IN : in std_logic_vector(15 downto 0); - SLV_ACK_OUT : out std_logic; - SLV_NO_MORE_DATA_OUT : out std_logic; - SLV_UNKNOWN_ADDR_OUT : out std_logic; - - -- Debug Line - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); -end entity; - -architecture Behavioral of nx_trigger_generator is - - signal start_cycle : std_logic; - signal trigger_cycle_ctr : unsigned(7 downto 0); - signal wait_timer_init : unsigned(15 downto 0); - signal wait_timer_done : std_logic; - signal trigger_o : std_logic; - signal ts_reset_o : std_logic; - signal testpulse_o : std_logic; - signal extern_trigger : std_logic; - - type STATES is (S_IDLE, - S_NEXT_CYCLE, - S_SET_TESTPULSE, - S_WAIT_TRIGGER_END - ); - signal STATE : STATES; - - -- TRBNet Slave Bus - signal slv_data_out_o : std_logic_vector(31 downto 0); - signal slv_no_more_data_o : std_logic; - signal slv_unknown_addr_o : std_logic; - signal slv_ack_o : std_logic; - - signal reg_trigger_period : unsigned(15 downto 0); - signal reg_testpulse_length : unsigned(15 downto 0); - signal reg_trigger_num_cycles : unsigned(7 downto 0); - signal reg_ts_reset_on : std_logic; - -begin - - -- Debug Line - DEBUG_OUT(0) <= CLK_IN; - DEBUG_OUT(1) <= trigger_o; - DEBUG_OUT(2) <= start_cycle; - DEBUG_OUT(3) <= wait_timer_done; - DEBUG_OUT(4) <= ts_reset_o; - DEBUG_OUT(5) <= testpulse_o; - DEBUG_OUT(6) <= TRIGGER_IN; - DEBUG_OUT(7) <= extern_trigger; - DEBUG_OUT(15 downto 8) <= trigger_cycle_ctr; - - -- Timer - nx_timer_1: nx_timer - generic map ( - CTR_WIDTH => 16 - ) - port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - TIMER_START_IN => wait_timer_init, - TIMER_DONE_OUT => wait_timer_done - ); - - ----------------------------------------------------------------------------- - -- Gernerate Trigger - ----------------------------------------------------------------------------- - - PROC_TRIGGER_OUT: process(CLK_IN) - begin - if( rising_edge(CLK_IN) ) then - if (RESET_IN = '1') then - trigger_o <= '0'; - testpulse_o <= '0'; - ts_reset_o <= '0'; - wait_timer_init <= (others => '0'); - trigger_cycle_ctr <= (others => '0'); - extern_trigger <= '0'; - STATE <= S_IDLE; - else - trigger_o <= '0'; - testpulse_o <= '0'; - ts_reset_o <= '0'; - wait_timer_init <= (others => '0'); - - case STATE is - when S_IDLE => - if (start_cycle = '1') then - trigger_cycle_ctr <= reg_trigger_num_cycles; - if (reg_ts_reset_on = '1') then - ts_reset_o <= '1'; - wait_timer_init <= reg_trigger_period; - STATE <= S_WAIT_TRIGGER_END; - else - STATE <= S_NEXT_CYCLE; - end if; - extern_trigger <= '0'; - elsif (TRIGGER_IN = '1') then - trigger_cycle_ctr <= (others => '0'); - wait_timer_init <= reg_testpulse_length; - extern_trigger <= '1'; - STATE <= S_SET_TESTPULSE; - else - extern_trigger <= '0'; - STATE <= S_IDLE; - end if; - - when S_NEXT_CYCLE => - if (trigger_cycle_ctr > 0) then - trigger_o <= '1'; - trigger_cycle_ctr <= trigger_cycle_ctr - 1; - if (reg_testpulse_length > 0) then - wait_timer_init <= reg_testpulse_length; - STATE <= S_SET_TESTPULSE; - else - wait_timer_init <= reg_trigger_period; - STATE <= S_WAIT_TRIGGER_END; - end if; - else - STATE <= S_IDLE; - end if; - - when S_SET_TESTPULSE => - testpulse_o <= '1'; - if (wait_timer_done = '0') then - STATE <= S_SET_TESTPULSE; - else - if (extern_trigger = '0') then - wait_timer_init <= reg_trigger_period - reg_testpulse_length; - else - wait_timer_init <= x"0001"; - end if; - STATE <= S_WAIT_TRIGGER_END; - end if; - - when S_WAIT_TRIGGER_END => - if (wait_timer_done = '0') then - STATE <= S_WAIT_TRIGGER_END; - else - STATE <= S_NEXT_CYCLE; - end if; - - end case; - end if; - end if; - end process PROC_TRIGGER_OUT; - - ----------------------------------------------------------------------------- - -- TRBNet Slave Bus - ----------------------------------------------------------------------------- - - PROC_SLAVE_BUS: process(CLK_IN) - begin - if( rising_edge(CLK_IN) ) then - if( RESET_IN = '1' ) then - reg_trigger_period <= x"00ff"; - reg_trigger_num_cycles <= x"01"; - reg_testpulse_length <= (others => '0'); - reg_ts_reset_on <= '0'; - slv_data_out_o <= (others => '0'); - slv_no_more_data_o <= '0'; - slv_unknown_addr_o <= '0'; - start_cycle <= '0'; - slv_ack_o <= '0'; - else - slv_unknown_addr_o <= '0'; - slv_no_more_data_o <= '0'; - slv_data_out_o <= (others => '0'); - start_cycle <= '0'; - - - if (SLV_WRITE_IN = '1') then - case SLV_ADDR_IN is - when x"0000" => - start_cycle <= '1'; - slv_ack_o <= '1'; - when x"0001" => - reg_trigger_period <= unsigned(SLV_DATA_IN(15 downto 0)); - slv_ack_o <= '1'; - when x"0002" => - reg_trigger_num_cycles <= unsigned(SLV_DATA_IN(7 downto 0)); - slv_ack_o <= '1'; - when x"0003" => - reg_testpulse_length <= unsigned(SLV_DATA_IN(15 downto 0)); - slv_ack_o <= '1'; - when x"0004" => - reg_ts_reset_on <= SLV_DATA_IN(0); - slv_ack_o <= '1'; - when others => - slv_unknown_addr_o <= '1'; - slv_ack_o <= '0'; - end case; - - elsif (SLV_READ_IN = '1') then - case SLV_ADDR_IN is - when x"0001" => - slv_data_out_o(15 downto 0) <= - std_logic_vector(reg_trigger_period); - slv_ack_o <= '1'; - when x"0002" => - slv_data_out_o(7 downto 0) <= - std_logic_vector(reg_trigger_num_cycles); - slv_ack_o <= '1'; - when x"0003" => - slv_data_out_o(15 downto 0) <= - std_logic_vector(reg_testpulse_length); - slv_ack_o <= '1'; - when x"0004" => - slv_data_out_o(0) <= reg_ts_reset_on; - slv_ack_o <= '1'; - when others => - slv_unknown_addr_o <= '1'; - slv_ack_o <= '0'; - end case; - - else - slv_ack_o <= '0'; - end if; - end if; - end if; - end process PROC_SLAVE_BUS; - - ----------------------------------------------------------------------------- - -- Output Signals - ----------------------------------------------------------------------------- - - -- Trigger Output - TRIGGER_OUT <= trigger_o; - TS_RESET_OUT <= ts_reset_o; - TESTPULSE_OUT <= testpulse_o; - - -- Slave Bus - SLV_DATA_OUT <= slv_data_out_o; - SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; - SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o; - SLV_ACK_OUT <= slv_ack_o; - -end Behavioral; +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.nxyter_components.all; + +entity nx_trigger_generator is + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + + TRIGGER_IN : in std_logic; + + TRIGGER_OUT : out std_logic; + TS_RESET_OUT : out std_logic; + TESTPULSE_OUT : out std_logic; + + -- Slave bus + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ADDR_IN : in std_logic_vector(15 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic; + + -- Debug Line + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); +end entity; + +architecture Behavioral of nx_trigger_generator is + + signal start_cycle : std_logic; + signal trigger_cycle_ctr : unsigned(7 downto 0); + signal wait_timer_init : unsigned(15 downto 0); + signal wait_timer_done : std_logic; + signal trigger_o : std_logic; + signal ts_reset_o : std_logic; + signal testpulse_o : std_logic; + signal extern_trigger : std_logic; + + type STATES is (S_IDLE, + S_NEXT_CYCLE, + S_SET_TESTPULSE, + S_WAIT_TRIGGER_END + ); + signal STATE : STATES; + + -- Rate Calculation + signal testpulse_p : std_logic; + signal testpulse_rate_t : unsigned(27 downto 0); + signal rate_timer : unsigned(27 downto 0); + + -- TRBNet Slave Bus + signal slv_data_out_o : std_logic_vector(31 downto 0); + signal slv_no_more_data_o : std_logic; + signal slv_unknown_addr_o : std_logic; + signal slv_ack_o : std_logic; + + signal reg_trigger_period : unsigned(15 downto 0); + signal reg_testpulse_length : unsigned(15 downto 0); + signal reg_trigger_num_cycles : unsigned(7 downto 0); + signal reg_ts_reset_on : std_logic; + signal testpulse_rate : unsigned(27 downto 0); + +begin + + -- Debug Line + DEBUG_OUT(0) <= CLK_IN; + DEBUG_OUT(1) <= trigger_o; + DEBUG_OUT(2) <= start_cycle; + DEBUG_OUT(3) <= wait_timer_done; + DEBUG_OUT(4) <= ts_reset_o; + DEBUG_OUT(5) <= testpulse_o; + DEBUG_OUT(6) <= TRIGGER_IN; + DEBUG_OUT(7) <= extern_trigger; + DEBUG_OUT(15 downto 8) <= trigger_cycle_ctr; + + -- Timer + nx_timer_1: nx_timer + generic map ( + CTR_WIDTH => 16 + ) + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + TIMER_START_IN => wait_timer_init, + TIMER_DONE_OUT => wait_timer_done + ); + + ----------------------------------------------------------------------------- + -- Gernerate Trigger + ----------------------------------------------------------------------------- + + PROC_TRIGGER_OUT: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if (RESET_IN = '1') then + trigger_o <= '0'; + testpulse_o <= '0'; + ts_reset_o <= '0'; + wait_timer_init <= (others => '0'); + trigger_cycle_ctr <= (others => '0'); + extern_trigger <= '0'; + STATE <= S_IDLE; + else + trigger_o <= '0'; + testpulse_o <= '0'; + ts_reset_o <= '0'; + wait_timer_init <= (others => '0'); + + case STATE is + when S_IDLE => + if (TRIGGER_IN = '1') then + extern_trigger <= '1'; + wait_timer_init <= reg_testpulse_length; + STATE <= S_SET_TESTPULSE; + else + extern_trigger <= '0'; + STATE <= S_IDLE; + end if; + + when S_SET_TESTPULSE => + testpulse_o <= '1'; + if (wait_timer_done = '0') then + STATE <= S_SET_TESTPULSE; + else + STATE <= S_IDLE; + end if; + + when others => + STATE <= S_IDLE; + end case; + end if; + end if; + end process PROC_TRIGGER_OUT; + + -- PROC_TRIGGER_OUT: process(CLK_IN) + -- begin + -- if( rising_edge(CLK_IN) ) then + -- if (RESET_IN = '1') then + -- trigger_o <= '0'; + -- testpulse_o <= '0'; + -- ts_reset_o <= '0'; + -- wait_timer_init <= (others => '0'); + -- trigger_cycle_ctr <= (others => '0'); + -- extern_trigger <= '0'; + -- STATE <= S_IDLE; + -- else + -- trigger_o <= '0'; + -- testpulse_o <= '0'; + -- ts_reset_o <= '0'; + -- wait_timer_init <= (others => '0'); + -- + -- case STATE is + -- when S_IDLE => + -- if (start_cycle = '1') then + -- trigger_cycle_ctr <= reg_trigger_num_cycles; + -- if (reg_ts_reset_on = '1') then + -- ts_reset_o <= '1'; + -- wait_timer_init <= reg_trigger_period; + -- STATE <= S_WAIT_TRIGGER_END; + -- else + -- STATE <= S_NEXT_CYCLE; + -- end if; + -- extern_trigger <= '0'; + -- elsif (TRIGGER_IN = '1') then + -- trigger_cycle_ctr <= (others => '0'); + -- extern_trigger <= '1'; + -- if (reg_testpulse_length > 0) then + -- wait_timer_init <= reg_testpulse_length; + -- STATE <= S_SET_TESTPULSE; + -- end if; + -- STATE <= S_NEXT_CYCLE ; + -- + -- else + -- extern_trigger <= '0'; + -- STATE <= S_IDLE; + -- end if; + -- + -- when S_NEXT_CYCLE => + -- if (trigger_cycle_ctr > 0) then + -- trigger_o <= '1'; + -- trigger_cycle_ctr <= trigger_cycle_ctr - 1; + -- if (reg_testpulse_length > 0) then + -- wait_timer_init <= reg_testpulse_length; + -- STATE <= S_SET_TESTPULSE; + -- else + -- wait_timer_init <= reg_trigger_period; + -- STATE <= S_WAIT_TRIGGER_END; + -- end if; + -- else + -- STATE <= S_IDLE; + -- end if; + -- + -- when S_SET_TESTPULSE => + -- testpulse_o <= '1'; + -- if (wait_timer_done = '0') then + -- STATE <= S_SET_TESTPULSE; + -- else + -- if (extern_trigger = '0') then + -- wait_timer_init <= reg_trigger_period - reg_testpulse_length; + -- else + -- wait_timer_init <= x"0001"; + -- end if; + -- STATE <= S_WAIT_TRIGGER_END; + -- end if; + -- + -- when S_WAIT_TRIGGER_END => + -- if (wait_timer_done = '0') then + -- STATE <= S_WAIT_TRIGGER_END; + -- else + -- STATE <= S_NEXT_CYCLE; + -- end if; + -- + -- end case; + -- end if; + -- end if; + -- end process PROC_TRIGGER_OUT; + + -- Convert TRIGGER_IN to Pulse + level_to_pulse_1: level_to_pulse + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + LEVEL_IN => testpulse_o, + PULSE_OUT => testpulse_p + ); + + PROC_CAL_RATES: process (CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if (RESET_IN = '1') then + testpulse_rate_t <= (others => '0'); + testpulse_rate <= (others => '0'); + rate_timer <= (others => '0'); + else + if (rate_timer < x"5f5e100") then + if ( testpulse_p = '1') then + testpulse_rate_t <= testpulse_rate_t + 1; + end if; + rate_timer <= rate_timer + 1; + else + testpulse_rate <= testpulse_rate_t; + testpulse_rate_t <= (others => '0'); + rate_timer <= (others => '0'); + end if; + end if; + end if; + end process PROC_CAL_RATES; + + ----------------------------------------------------------------------------- + -- TRBNet Slave Bus + ----------------------------------------------------------------------------- + + PROC_SLAVE_BUS: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + reg_trigger_period <= x"00ff"; + reg_trigger_num_cycles <= x"01"; + --reg_testpulse_length <= (others => '0'); + reg_testpulse_length <= x"0005"; + reg_ts_reset_on <= '0'; + slv_data_out_o <= (others => '0'); + slv_no_more_data_o <= '0'; + slv_unknown_addr_o <= '0'; + start_cycle <= '0'; + slv_ack_o <= '0'; + else + slv_unknown_addr_o <= '0'; + slv_no_more_data_o <= '0'; + slv_data_out_o <= (others => '0'); + start_cycle <= '0'; + + + if (SLV_WRITE_IN = '1') then + case SLV_ADDR_IN is + when x"0000" => + start_cycle <= '1'; + slv_ack_o <= '1'; + + when x"0001" => + reg_trigger_period <= unsigned(SLV_DATA_IN(15 downto 0)); + slv_ack_o <= '1'; + + when x"0002" => + reg_trigger_num_cycles <= unsigned(SLV_DATA_IN(7 downto 0)); + slv_ack_o <= '1'; + + when x"0003" => + if (reg_testpulse_length > 0) then + reg_testpulse_length <= unsigned(SLV_DATA_IN(15 downto 0)); + end if; + slv_ack_o <= '1'; + + when x"0004" => + reg_ts_reset_on <= SLV_DATA_IN(0); + slv_ack_o <= '1'; + + when others => + slv_unknown_addr_o <= '1'; + slv_ack_o <= '0'; + end case; + + elsif (SLV_READ_IN = '1') then + case SLV_ADDR_IN is + when x"0001" => + slv_data_out_o(15 downto 0) <= + std_logic_vector(reg_trigger_period); + slv_ack_o <= '1'; + + when x"0002" => + slv_data_out_o(7 downto 0) <= + std_logic_vector(reg_trigger_num_cycles); + slv_ack_o <= '1'; + + when x"0003" => + slv_data_out_o(15 downto 0) <= + std_logic_vector(reg_testpulse_length); + slv_ack_o <= '1'; + + when x"0004" => + slv_data_out_o(0) <= reg_ts_reset_on; + slv_ack_o <= '1'; + + when x"0005" => + slv_data_out_o(27 downto 0) <= std_logic_vector(testpulse_rate); + slv_data_out_o(31 downto 28) <= (others => '0'); + slv_ack_o <= '1'; + + when others => + slv_unknown_addr_o <= '1'; + slv_ack_o <= '0'; + end case; + + else + slv_ack_o <= '0'; + end if; + end if; + end if; + end process PROC_SLAVE_BUS; + + ----------------------------------------------------------------------------- + -- Output Signals + ----------------------------------------------------------------------------- + + -- Trigger Output + TRIGGER_OUT <= trigger_o; + TS_RESET_OUT <= ts_reset_o; + TESTPULSE_OUT <= testpulse_o; + + -- Slave Bus + SLV_DATA_OUT <= slv_data_out_o; + SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; + SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o; + SLV_ACK_OUT <= slv_ack_o; + +end Behavioral; diff --git a/nxyter/source/nx_trigger_handler.vhd b/nxyter/source/nx_trigger_handler.vhd index 8bec403..8df99a7 100644 --- a/nxyter/source/nx_trigger_handler.vhd +++ b/nxyter/source/nx_trigger_handler.vhd @@ -1,374 +1,411 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.nxyter_components.all; - -entity nx_trigger_handler is - port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - - NXYTER_OFFLINE_IN : in std_logic; - - --LVL1 trigger - LVL1_TRG_DATA_VALID_IN : in std_logic; -- timing trigger valid, later - LVL1_VALID_TIMING_TRG_IN : in std_logic; -- timing trigger synced - LVL1_VALID_NOTIMING_TRG_IN : in std_logic; -- timing trigger raw - LVL1_INVALID_TRG_IN : in std_logic; -- ??? - - LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0); - LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); - LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0); - LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0); - LVL1_INT_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); - - FEE_TRG_RELEASE_OUT : out std_logic; - FEE_TRG_STATUSBITS_OUT : out std_logic_vector(31 downto 0); - - -- Internal FPGA Trigger - INTERNAL_TRIGGER_IN : in std_logic; - - -- Trigger FeedBack - TRIGGER_VALIDATE_BUSY_IN : in std_logic; - LVL2_TRIGGER_BUSY_IN : in std_logic; - - -- OUT - VALIDATE_TRIGGER_OUT : out std_logic; - TIMESTAMP_HOLD_OUT : out std_logic; - LVL2_TRIGGER_OUT : out std_logic; - EVENT_BUFFER_CLEAR_OUT : out std_logic; - FAST_CLEAR_OUT : out std_logic; - TRIGGER_BUSY_OUT : out std_logic; - - -- Pulser - TRIGGER_TESTPULSE_OUT : out std_logic; - - -- Slave bus - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_ADDR_IN : in std_logic_vector(15 downto 0); - SLV_ACK_OUT : out std_logic; - SLV_NO_MORE_DATA_OUT : out std_logic; - SLV_UNKNOWN_ADDR_OUT : out std_logic; - - -- Debug Line - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); -end entity; - -architecture Behavioral of nx_trigger_handler is - - -- Trigger Handler - signal validate_trigger_o : std_logic; - signal timestamp_hold : std_logic; - signal lvl2_trigger_o : std_logic; - signal event_buffer_clear_o : std_logic; - signal fast_clear_o : std_logic; - signal trigger_busy_o : std_logic; - signal fee_trg_release_o : std_logic; - signal fee_trg_statusbits_o : std_logic_vector(31 downto 0); - signal trigger_testpulse_o : std_logic; - - type STATES is (S_IDLE, - S_CTS_TRIGGER, - S_WAIT_TRG_DATA_VALID, - S_WAIT_LVL2_TRIGGER_DONE, - S_FEE_TRIGGER_RELEASE, - S_WAIT_FEE_TRIGGER_RELEASE_ACK, - S_INTERNAL_TRIGGER, - S_WAIT_TRIGGER_VALIDATE_ACK, - S_WAIT_TRIGGER_VALIDATE_DONE - ); - signal STATE : STATES; - - -- Timestamp Hold Handler - type TS_STATES is (TS_IDLE, - TS_WAIT_TIMER_DONE - ); - signal TS_STATE : TS_STATES; - - signal timestamp_hold_o : std_logic; - signal wait_timer_reset : std_logic; - signal wait_timer_init : unsigned(7 downto 0); - signal wait_timer_done : std_logic; - - -- TRBNet Slave Bus - signal slv_data_out_o : std_logic_vector(31 downto 0); - signal slv_no_more_data_o : std_logic; - signal slv_unknown_addr_o : std_logic; - signal slv_ack_o : std_logic; - - signal reg_timestamp_hold_delay : unsigned(7 downto 0); - signal reg_testpulse_enable : std_logic; - -begin - - -- Debug Line - DEBUG_OUT(0) <= CLK_IN; - DEBUG_OUT(1) <= LVL1_VALID_TIMING_TRG_IN; - DEBUG_OUT(2) <= LVL1_TRG_DATA_VALID_IN; - DEBUG_OUT(3) <= INTERNAL_TRIGGER_IN; - DEBUG_OUT(4) <= TRIGGER_VALIDATE_BUSY_IN; - DEBUG_OUT(5) <= LVL2_TRIGGER_BUSY_IN; - - DEBUG_OUT(6) <= validate_trigger_o; - DEBUG_OUT(7) <= timestamp_hold_o; - DEBUG_OUT(8) <= lvl2_trigger_o; - DEBUG_OUT(9) <= event_buffer_clear_o; - DEBUG_OUT(10) <= fee_trg_release_o; - DEBUG_OUT(11) <= trigger_busy_o; - - DEBUG_OUT(15 downto 12) <= (others => '0'); - - -- Timer - nx_timer_1: nx_timer - generic map ( - CTR_WIDTH => 8 - ) - port map ( - CLK_IN => CLK_IN, - RESET_IN => wait_timer_reset, - TIMER_START_IN => wait_timer_init, - TIMER_DONE_OUT => wait_timer_done - ); - - wait_timer_reset <= RESET_IN or fast_clear_o; - - ----------------------------------------------------------------------------- - -- Trigger Handler - ----------------------------------------------------------------------------- - - PROC_TRIGGER_HANDLER: process(CLK_IN) - begin - if( rising_edge(CLK_IN) ) then - if (RESET_IN = '1') then - validate_trigger_o <= '0'; - timestamp_hold <= '0'; - lvl2_trigger_o <= '0'; - fee_trg_release_o <= '0'; - fee_trg_statusbits_o <= (others => '0'); - fast_clear_o <= '0'; - event_buffer_clear_o <= '0'; - trigger_busy_o <= '0'; - trigger_testpulse_o <= '0'; - STATE <= S_IDLE; - else - validate_trigger_o <= '0'; - timestamp_hold <= '0'; - lvl2_trigger_o <= '0'; - fee_trg_release_o <= '0'; - fee_trg_statusbits_o <= (others => '0'); - fast_clear_o <= '0'; - event_buffer_clear_o <= '0'; - trigger_busy_o <= '1'; - trigger_testpulse_o <= '0'; - - if (LVL1_INVALID_TRG_IN = '1') then - fast_clear_o <= '1'; - fee_trg_release_o <= '1'; - STATE <= S_IDLE; - else - case STATE is - when S_IDLE => - if (LVL1_VALID_NOTIMING_TRG_IN = '1') then - STATE <= S_WAIT_TRG_DATA_VALID; - - elsif (LVL1_VALID_TIMING_TRG_IN = '1') then - if (NXYTER_OFFLINE_IN = '1') then - STATE <= S_WAIT_TRG_DATA_VALID; - else - STATE <= S_CTS_TRIGGER; - end if; - elsif (INTERNAL_TRIGGER_IN = '1') then - STATE <= S_INTERNAL_TRIGGER; - else - trigger_busy_o <= '0'; - STATE <= S_IDLE; - end if; - - -- CTS Trigger Handler - when S_CTS_TRIGGER => - event_buffer_clear_o <= '1'; - validate_trigger_o <= '1'; - timestamp_hold <= '1'; - lvl2_trigger_o <= '1'; - if (reg_testpulse_enable = '1') then - trigger_testpulse_o <= '1'; - end if; - STATE <= S_WAIT_TRG_DATA_VALID; - - when S_WAIT_TRG_DATA_VALID => - if (LVL1_TRG_DATA_VALID_IN = '0') then - STATE <= S_WAIT_TRG_DATA_VALID; - else - STATE <= S_WAIT_LVL2_TRIGGER_DONE; - end if; - - when S_WAIT_LVL2_TRIGGER_DONE => - if (LVL2_TRIGGER_BUSY_IN = '1') then - STATE <= S_WAIT_LVL2_TRIGGER_DONE; - else - STATE <= S_FEE_TRIGGER_RELEASE; - end if; - - when S_FEE_TRIGGER_RELEASE => - fee_trg_release_o <= '1'; - STATE <= S_WAIT_FEE_TRIGGER_RELEASE_ACK; - - when S_WAIT_FEE_TRIGGER_RELEASE_ACK => - if (LVL1_TRG_DATA_VALID_IN = '1') then - STATE <= S_WAIT_FEE_TRIGGER_RELEASE_ACK; - else - STATE <= S_IDLE; - end if; - - -- Internal Trigger Handler - when S_INTERNAL_TRIGGER => - validate_trigger_o <= '1'; - timestamp_hold <= '1'; - event_buffer_clear_o <= '1'; - STATE <= S_WAIT_TRIGGER_VALIDATE_ACK; - - when S_WAIT_TRIGGER_VALIDATE_ACK => - if (TRIGGER_VALIDATE_BUSY_IN = '0') then - STATE <= S_WAIT_TRIGGER_VALIDATE_ACK; - else - STATE <= S_WAIT_TRIGGER_VALIDATE_DONE; - end if; - - when S_WAIT_TRIGGER_VALIDATE_DONE => - if (TRIGGER_VALIDATE_BUSY_IN = '1') then - STATE <= S_WAIT_TRIGGER_VALIDATE_DONE; - else - STATE <= S_IDLE; - end if; - - end case; - end if; - end if; - end if; - end process PROC_TRIGGER_HANDLER; - - PROC_SEND_TIMSTAMP_HOLD: process(CLK_IN) - begin - if( rising_edge(CLK_IN) ) then - if (RESET_IN = '1' or NXYTER_OFFLINE_IN = '1') then - wait_timer_init <= (others => '0'); - timestamp_hold_o <= '0'; - TS_STATE <= TS_IDLE; - else - wait_timer_init <= (others => '0'); - timestamp_hold_o <= '0'; - - case TS_STATE is - - when TS_IDLE => - if (timestamp_hold = '0') then - TS_STATE <= TS_IDLE; - else - wait_timer_init <= reg_timestamp_hold_delay; - TS_STATE <= TS_WAIT_TIMER_DONE; - end if; - - when TS_WAIT_TIMER_DONE => - if (wait_timer_done = '0') then - TS_STATE <= TS_WAIT_TIMER_DONE; - else - timestamp_hold_o <= '1'; - TS_STATE <= TS_IDLE; - end if; - - end case; - - end if; - end if; - end process PROC_SEND_TIMSTAMP_HOLD; - - ----------------------------------------------------------------------------- - -- TRBNet Slave Bus - ----------------------------------------------------------------------------- - - PROC_SLAVE_BUS: process(CLK_IN) - begin - if( rising_edge(CLK_IN) ) then - if( RESET_IN = '1' ) then - slv_data_out_o <= (others => '0'); - slv_no_more_data_o <= '0'; - slv_unknown_addr_o <= '0'; - slv_ack_o <= '0'; - reg_timestamp_hold_delay <= x"01"; - reg_testpulse_enable <= '0'; - else - slv_unknown_addr_o <= '0'; - slv_no_more_data_o <= '0'; - slv_data_out_o <= (others => '0'); - slv_ack_o <= '0'; - - if (SLV_WRITE_IN = '1') then - case SLV_ADDR_IN is - when x"0000" => - if (unsigned(SLV_DATA_IN(7 downto 0)) > 0) then - reg_timestamp_hold_delay <= unsigned(SLV_DATA_IN(7 downto 0)); - end if; - slv_ack_o <= '1'; - - when x"0001" => - reg_testpulse_enable <= SLV_DATA_IN(0); - slv_ack_o <= '1'; - - when others => - slv_unknown_addr_o <= '1'; - - end case; - - elsif (SLV_READ_IN = '1') then - case SLV_ADDR_IN is - - when x"0000" => - slv_data_out_o(7 downto 0) <= - std_logic_vector(reg_timestamp_hold_delay); - slv_data_out_o(31 downto 8) <= (others => '0'); - slv_ack_o <= '1'; - - when x"0001" => - slv_data_out_o(0) <= reg_testpulse_enable; - slv_data_out_o(31 downto 1) <= (others => '0'); - slv_ack_o <= '1'; - - when others => - slv_unknown_addr_o <= '1'; - - end case; - - end if; - end if; - end if; - end process PROC_SLAVE_BUS; - - ----------------------------------------------------------------------------- - -- Output Signals - ----------------------------------------------------------------------------- - - -- Trigger Output - VALIDATE_TRIGGER_OUT <= validate_trigger_o; - TIMESTAMP_HOLD_OUT <= timestamp_hold_o; - LVL2_TRIGGER_OUT <= lvl2_trigger_o; - EVENT_BUFFER_CLEAR_OUT <= event_buffer_clear_o; - FAST_CLEAR_OUT <= fast_clear_o; - TRIGGER_BUSY_OUT <= trigger_busy_o; - FEE_TRG_RELEASE_OUT <= fee_trg_release_o; - FEE_TRG_STATUSBITS_OUT <= fee_trg_statusbits_o; - - TRIGGER_TESTPULSE_OUT <= trigger_testpulse_o; - - -- Slave Bus - SLV_DATA_OUT <= slv_data_out_o; - SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; - SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o; - SLV_ACK_OUT <= slv_ack_o; - -end Behavioral; +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.nxyter_components.all; + +entity nx_trigger_handler is + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + + NXYTER_OFFLINE_IN : in std_logic; + + --LVL1 trigger + LVL1_TRG_DATA_VALID_IN : in std_logic; -- timing trigger valid, later + LVL1_VALID_TIMING_TRG_IN : in std_logic; -- timing trigger synced + LVL1_VALID_NOTIMING_TRG_IN : in std_logic; -- timing trigger raw + LVL1_INVALID_TRG_IN : in std_logic; -- ??? + + LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0); + LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); + LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0); + LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0); + LVL1_INT_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); + + FEE_TRG_RELEASE_OUT : out std_logic; + FEE_TRG_STATUSBITS_OUT : out std_logic_vector(31 downto 0); + + -- Internal FPGA Trigger + INTERNAL_TRIGGER_IN : in std_logic; + + -- Trigger FeedBack + TRIGGER_VALIDATE_BUSY_IN : in std_logic; + LVL2_TRIGGER_BUSY_IN : in std_logic; + + -- OUT + VALIDATE_TRIGGER_OUT : out std_logic; + TIMESTAMP_TRIGGER_OUT : out std_logic; + LVL2_TRIGGER_OUT : out std_logic; + EVENT_BUFFER_CLEAR_OUT : out std_logic; + FAST_CLEAR_OUT : out std_logic; + TRIGGER_BUSY_OUT : out std_logic; + + -- Pulser + TRIGGER_TESTPULSE_OUT : out std_logic; + + -- Slave bus + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ADDR_IN : in std_logic_vector(15 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic; + + -- Debug Line + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); +end entity; + +architecture Behavioral of nx_trigger_handler is + + -- Trigger Handler + signal validate_trigger_o : std_logic; + signal timestamp_hold : std_logic; + signal lvl2_trigger_o : std_logic; + signal event_buffer_clear_o : std_logic; + signal fast_clear_o : std_logic; + signal trigger_busy_o : std_logic; + signal fee_trg_release_o : std_logic; + signal fee_trg_statusbits_o : std_logic_vector(31 downto 0); + signal trigger_testpulse_o : std_logic; + + type STATES is (S_IDLE, + S_CTS_TRIGGER, + S_WAIT_TRG_DATA_VALID, + S_WAIT_LVL2_TRIGGER_DONE, + S_FEE_TRIGGER_RELEASE, + S_WAIT_FEE_TRIGGER_RELEASE_ACK, + S_INTERNAL_TRIGGER, + S_WAIT_TRIGGER_VALIDATE_ACK, + S_WAIT_TRIGGER_VALIDATE_DONE + ); + signal STATE : STATES; + + -- Timestamp Hold Handler + type TS_STATES is (TS_IDLE, + TS_WAIT_TIMER_DONE + ); + signal TS_STATE : TS_STATES; + + signal timestamp_trigger_o : std_logic; + signal wait_timer_reset : std_logic; + signal wait_timer_init : unsigned(7 downto 0); + signal wait_timer_done : std_logic; + + -- Rate Calculation + signal accepted_trigger_rate_t : unsigned(27 downto 0); + signal rate_timer : unsigned(27 downto 0); + + -- TRBNet Slave Bus + signal slv_data_out_o : std_logic_vector(31 downto 0); + signal slv_no_more_data_o : std_logic; + signal slv_unknown_addr_o : std_logic; + signal slv_ack_o : std_logic; + + signal reg_timestamp_trigger_delay : unsigned(7 downto 0); + signal reg_testpulse_enable : std_logic; + signal accepted_trigger_rate : unsigned(27 downto 0); + +begin + + -- Debug Line + DEBUG_OUT(0) <= CLK_IN; + DEBUG_OUT(1) <= LVL1_VALID_TIMING_TRG_IN; + DEBUG_OUT(2) <= LVL1_TRG_DATA_VALID_IN; + DEBUG_OUT(3) <= INTERNAL_TRIGGER_IN; + DEBUG_OUT(4) <= TRIGGER_VALIDATE_BUSY_IN; + DEBUG_OUT(5) <= LVL2_TRIGGER_BUSY_IN; + + DEBUG_OUT(6) <= validate_trigger_o; + DEBUG_OUT(7) <= timestamp_trigger_o; + DEBUG_OUT(8) <= lvl2_trigger_o; + DEBUG_OUT(9) <= event_buffer_clear_o; + DEBUG_OUT(10) <= fee_trg_release_o; + DEBUG_OUT(11) <= trigger_busy_o; + DEBUG_OUT(12) <= trigger_testpulse_o; + DEBUG_OUT(13) <= slv_unknown_addr_o; + DEBUG_OUT(14) <= slv_no_more_data_o; + DEBUG_OUT(15) <= slv_unknown_addr_o; +-- DEBUG_OUT(15 downto 13) <= (others => '0'); + + -- Timer + nx_timer_1: nx_timer + generic map ( + CTR_WIDTH => 8 + ) + port map ( + CLK_IN => CLK_IN, + RESET_IN => wait_timer_reset, + TIMER_START_IN => wait_timer_init, + TIMER_DONE_OUT => wait_timer_done + ); + + wait_timer_reset <= RESET_IN or fast_clear_o; + + ----------------------------------------------------------------------------- + -- Trigger Handler + ----------------------------------------------------------------------------- + + PROC_TRIGGER_HANDLER: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if (RESET_IN = '1') then + validate_trigger_o <= '0'; + timestamp_hold <= '0'; + lvl2_trigger_o <= '0'; + fee_trg_release_o <= '0'; + fee_trg_statusbits_o <= (others => '0'); + fast_clear_o <= '0'; + event_buffer_clear_o <= '0'; + trigger_busy_o <= '0'; + trigger_testpulse_o <= '0'; + STATE <= S_IDLE; + else + validate_trigger_o <= '0'; + timestamp_hold <= '0'; + lvl2_trigger_o <= '0'; + fee_trg_release_o <= '0'; + fee_trg_statusbits_o <= (others => '0'); + fast_clear_o <= '0'; + event_buffer_clear_o <= '0'; + trigger_busy_o <= '1'; + trigger_testpulse_o <= '0'; + + if (LVL1_INVALID_TRG_IN = '1') then + fast_clear_o <= '1'; + fee_trg_release_o <= '1'; + STATE <= S_IDLE; + else + case STATE is + when S_IDLE => + if (LVL1_VALID_NOTIMING_TRG_IN = '1') then + STATE <= S_WAIT_TRG_DATA_VALID; + + elsif (LVL1_VALID_TIMING_TRG_IN = '1') then + if (NXYTER_OFFLINE_IN = '1') then + STATE <= S_WAIT_TRG_DATA_VALID; + else + STATE <= S_CTS_TRIGGER; + end if; + elsif (INTERNAL_TRIGGER_IN = '1') then + STATE <= S_INTERNAL_TRIGGER; + else + trigger_busy_o <= '0'; + STATE <= S_IDLE; + end if; + + -- CTS Trigger Handler + when S_CTS_TRIGGER => + event_buffer_clear_o <= '1'; + validate_trigger_o <= '1'; + timestamp_hold <= '1'; + lvl2_trigger_o <= '1'; + if (reg_testpulse_enable = '1') then + trigger_testpulse_o <= '1'; + end if; + STATE <= S_WAIT_TRG_DATA_VALID; + + when S_WAIT_TRG_DATA_VALID => + if (LVL1_TRG_DATA_VALID_IN = '0') then + STATE <= S_WAIT_TRG_DATA_VALID; + else + STATE <= S_WAIT_LVL2_TRIGGER_DONE; + end if; + + when S_WAIT_LVL2_TRIGGER_DONE => + if (LVL2_TRIGGER_BUSY_IN = '1') then + STATE <= S_WAIT_LVL2_TRIGGER_DONE; + else + STATE <= S_FEE_TRIGGER_RELEASE; + end if; + + when S_FEE_TRIGGER_RELEASE => + fee_trg_release_o <= '1'; + STATE <= S_WAIT_FEE_TRIGGER_RELEASE_ACK; + + when S_WAIT_FEE_TRIGGER_RELEASE_ACK => + if (LVL1_TRG_DATA_VALID_IN = '1') then + STATE <= S_WAIT_FEE_TRIGGER_RELEASE_ACK; + else + STATE <= S_IDLE; + end if; + + -- Internal Trigger Handler + when S_INTERNAL_TRIGGER => + validate_trigger_o <= '1'; + timestamp_hold <= '1'; + event_buffer_clear_o <= '1'; + STATE <= S_WAIT_TRIGGER_VALIDATE_ACK; + + when S_WAIT_TRIGGER_VALIDATE_ACK => + if (TRIGGER_VALIDATE_BUSY_IN = '0') then + STATE <= S_WAIT_TRIGGER_VALIDATE_ACK; + else + STATE <= S_WAIT_TRIGGER_VALIDATE_DONE; + end if; + + when S_WAIT_TRIGGER_VALIDATE_DONE => + if (TRIGGER_VALIDATE_BUSY_IN = '1') then + STATE <= S_WAIT_TRIGGER_VALIDATE_DONE; + else + STATE <= S_IDLE; + end if; + + end case; + end if; + end if; + end if; + end process PROC_TRIGGER_HANDLER; + + PROC_SEND_TIMSTAMP_TRIGGER: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if (RESET_IN = '1' or NXYTER_OFFLINE_IN = '1') then + wait_timer_init <= (others => '0'); + timestamp_trigger_o <= '0'; + TS_STATE <= TS_IDLE; + else + wait_timer_init <= (others => '0'); + timestamp_trigger_o <= '0'; + + case TS_STATE is + + when TS_IDLE => + if (timestamp_hold = '0') then + TS_STATE <= TS_IDLE; + else + wait_timer_init <= reg_timestamp_trigger_delay; + TS_STATE <= TS_WAIT_TIMER_DONE; + end if; + + when TS_WAIT_TIMER_DONE => + if (wait_timer_done = '0') then + TS_STATE <= TS_WAIT_TIMER_DONE; + else + timestamp_trigger_o <= '1'; + TS_STATE <= TS_IDLE; + end if; + + end case; + + end if; + end if; + end process PROC_SEND_TIMSTAMP_TRIGGER; + + PROC_CAL_RATES: process (CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if (RESET_IN = '1') then + accepted_trigger_rate_t <= (others => '0'); + accepted_trigger_rate <= (others => '0'); + rate_timer <= (others => '0'); + else + if (rate_timer < x"5f5e100") then + if (lvl2_trigger_o = '1') then + accepted_trigger_rate_t <= accepted_trigger_rate_t + 1; + end if; + rate_timer <= rate_timer + 1; + else + accepted_trigger_rate <= accepted_trigger_rate_t; + accepted_trigger_rate_t <= (others => '0'); + rate_timer <= (others => '0'); + end if; + end if; + end if; + end process PROC_CAL_RATES; + + ----------------------------------------------------------------------------- + -- TRBNet Slave Bus + ----------------------------------------------------------------------------- + + PROC_SLAVE_BUS: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + slv_data_out_o <= (others => '0'); + slv_no_more_data_o <= '0'; + slv_unknown_addr_o <= '0'; + slv_ack_o <= '0'; + reg_timestamp_trigger_delay <= x"01"; + reg_testpulse_enable <= '0'; + else + slv_unknown_addr_o <= '0'; + slv_no_more_data_o <= '0'; + slv_data_out_o <= (others => '0'); + slv_ack_o <= '0'; + + if (SLV_WRITE_IN = '1') then + case SLV_ADDR_IN is + when x"0000" => + if (unsigned(SLV_DATA_IN(7 downto 0)) > 0) then + reg_timestamp_trigger_delay <= + unsigned(SLV_DATA_IN(7 downto 0)); + end if; + slv_ack_o <= '1'; + + when x"0001" => + reg_testpulse_enable <= SLV_DATA_IN(0); + slv_ack_o <= '1'; + + when others => + slv_unknown_addr_o <= '1'; + + end case; + + elsif (SLV_READ_IN = '1') then + case SLV_ADDR_IN is + + when x"0000" => + slv_data_out_o(7 downto 0) <= + std_logic_vector(reg_timestamp_trigger_delay); + slv_data_out_o(31 downto 8) <= (others => '0'); + slv_ack_o <= '1'; + + when x"0001" => + slv_data_out_o(0) <= reg_testpulse_enable; + slv_data_out_o(31 downto 1) <= (others => '0'); + slv_ack_o <= '1'; + + when x"0002" => + slv_data_out_o(27 downto 0) <= + std_logic_vector(accepted_trigger_rate); + slv_data_out_o(31 downto 28) <= (others => '0'); + slv_ack_o <= '1'; + + when others => + slv_unknown_addr_o <= '1'; + + end case; + + end if; + end if; + end if; + end process PROC_SLAVE_BUS; + + ----------------------------------------------------------------------------- + -- Output Signals + ----------------------------------------------------------------------------- + + -- Trigger Output + VALIDATE_TRIGGER_OUT <= validate_trigger_o; + TIMESTAMP_TRIGGER_OUT <= timestamp_trigger_o; + LVL2_TRIGGER_OUT <= lvl2_trigger_o; + EVENT_BUFFER_CLEAR_OUT <= event_buffer_clear_o; + FAST_CLEAR_OUT <= fast_clear_o; + TRIGGER_BUSY_OUT <= trigger_busy_o; + FEE_TRG_RELEASE_OUT <= fee_trg_release_o; + FEE_TRG_STATUSBITS_OUT <= fee_trg_statusbits_o; + + TRIGGER_TESTPULSE_OUT <= trigger_testpulse_o; + + -- Slave Bus + SLV_DATA_OUT <= slv_data_out_o; + SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; + SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o; + SLV_ACK_OUT <= slv_ack_o; + +end Behavioral; diff --git a/nxyter/source/nx_trigger_validate.vhd b/nxyter/source/nx_trigger_validate.vhd index 600b3c3..462b1a6 100644 --- a/nxyter/source/nx_trigger_validate.vhd +++ b/nxyter/source/nx_trigger_validate.vhd @@ -6,6 +6,9 @@ library work; use work.nxyter_components.all; entity nx_trigger_validate is + generic ( + BOARD_ID : std_logic_vector(15 downto 0) := x"ffff" + ); port ( CLK_IN : in std_logic; RESET_IN : in std_logic; @@ -87,6 +90,7 @@ architecture Behavioral of nx_trigger_validate is type STATES is (S_IDLE, S_TRIGGER, S_WAIT_DATA, + S_WRITE_HEADER, S_PROCESS_START, S_WAIT_PROCESS_END, S_WRITE_TRAILER, @@ -302,7 +306,7 @@ begin PROC_TRIGGER_HANDLER: process(CLK_IN) variable min_validation_time : unsigned(11 downto 0); - + variable ts_ref : unsigned(11 downto 0); begin if( rising_edge(CLK_IN) ) then if (RESET_IN = '1' or FAST_CLEAR_IN = '1') then @@ -332,7 +336,7 @@ begin (trigger_window_delay / 2) + (trigger_window_width / 2); - + case STATE is when S_IDLE => @@ -348,14 +352,22 @@ begin ch_status_cmd_tr <= CS_RESET; wait_timer_init <= x"020"; -- wait 320ns for first event STATE <= S_WAIT_DATA; - + when S_WAIT_DATA => if (wait_timer_done = '0') then STATE <= S_WAIT_DATA; else - STATE <= S_PROCESS_START; + STATE <= S_WRITE_HEADER; end if; - + + when S_WRITE_HEADER => + --ts_ref := timestamp_ref - x"010"; + t_data_o(11 downto 0) <= timestamp_ref; + t_data_o(15 downto 12) <= (others => '0'); + t_data_o(31 downto 16) <= BOARD_ID; + t_data_clk_o <= '1'; + STATE <= S_PROCESS_START; + when S_PROCESS_START => token_return_ctr <= '0'; wait_timer_init <= readout_time_max; @@ -388,7 +400,9 @@ begin end if; when S_WRITE_TRAILER => - t_data_o <= x"deadaffe"; + t_data_o(11 downto 0) <= busy_time_ctr; + t_data_o(15 downto 12) <= (others => '0'); + t_data_o(31 downto 16) <= BOARD_ID; t_data_clk_o <= '1'; ch_status_cmd_tr <= CS_RESET; STATE <= S_SET_NOMORE_DATA; diff --git a/nxyter/source/nxyter_components.vhd b/nxyter/source/nxyter_components.vhd index 400d900..c9b3484 100644 --- a/nxyter/source/nxyter_components.vhd +++ b/nxyter/source/nxyter_components.vhd @@ -18,6 +18,7 @@ package nxyter_components is CLK_NX_IN : in std_logic; CLK_ADC_IN : in std_logic; + TRIGGER_OUT : out std_logic; I2C_SDA_INOUT : inout std_logic; I2C_SCL_INOUT : inout std_logic; @@ -276,11 +277,24 @@ component fifo_ts_32to32_dc RdEn : in std_logic; Reset : in std_logic; RPReset : in std_logic; - AmEmptyThresh : in std_logic_vector(4 downto 0); Q : out std_logic_vector(31 downto 0); Empty : out std_logic; + Full : out std_logic + ); +end component; + +component fifo_44_data_delay + port ( + Data : in std_logic_vector(43 downto 0); + Clock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + AmEmptyThresh : in std_logic_vector(6 downto 0); + Q : out std_logic_vector(43 downto 0); + Empty : out std_logic; Full : out std_logic; - AlmostEmpty : out std_logic + AlmostEmpty : out std_logic ); end component; @@ -302,6 +316,7 @@ component nx_data_receiver port ( CLK_IN : in std_logic; RESET_IN : in std_logic; + TRIGGER_IN : in std_logic; NX_TIMESTAMP_CLK_IN : in std_logic; NX_TIMESTAMP_IN : in std_logic_vector (7 downto 0); ADC_CLK_DAT_IN : in std_logic; @@ -315,6 +330,29 @@ component nx_data_receiver NX_TIMESTAMP_OUT : out std_logic_vector(31 downto 0); ADC_DATA_OUT : out std_logic_vector(11 downto 0); NEW_DATA_OUT : out std_logic; + TIMESTAMP_CURRENT_IN : in unsigned(11 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ADDR_IN : in std_logic_vector(15 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); +end component; + +component nx_data_delay + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + NX_FRAME_IN : in std_logic_vector(31 downto 0); + ADC_DATA_IN : in std_logic_vector(11 downto 0); + NEW_DATA_IN : in std_logic; + NX_FRAME_OUT : out std_logic_vector(31 downto 0); + ADC_DATA_OUT : out std_logic_vector(11 downto 0); + NEW_DATA_OUT : out std_logic; SLV_READ_IN : in std_logic; SLV_WRITE_IN : in std_logic; SLV_DATA_OUT : out std_logic_vector(31 downto 0); @@ -354,6 +392,9 @@ component nx_data_validate end component; component nx_trigger_validate + generic ( + BOARD_ID : std_logic_vector(15 downto 0) := x"ffff" + ); port ( CLK_IN : in std_logic; RESET_IN : in std_logic; @@ -539,8 +580,9 @@ component nx_fpga_timestamp RESET_IN : in std_logic; TIMESTAMP_SYNC_IN : in std_logic; TRIGGER_IN : in std_logic; - TIMESTAMP_OUT : out unsigned(11 downto 0); - NX_TIMESTAMP_SYNC_OUT : in std_logic; + TIMESTAMP_CURRENT_OUT : out unsigned(11 downto 0); + TIMESTAMP_HOLD_OUT : out unsigned(11 downto 0); + NX_TIMESTAMP_SYNC_OUT : out std_logic; SLV_READ_IN : in std_logic; SLV_WRITE_IN : in std_logic; SLV_DATA_OUT : out std_logic_vector(31 downto 0); @@ -572,7 +614,7 @@ component nx_trigger_handler TRIGGER_VALIDATE_BUSY_IN : in std_logic; LVL2_TRIGGER_BUSY_IN : in std_logic; VALIDATE_TRIGGER_OUT : out std_logic; - TIMESTAMP_HOLD_OUT : out std_logic; + TIMESTAMP_TRIGGER_OUT : out std_logic; LVL2_TRIGGER_OUT : out std_logic; EVENT_BUFFER_CLEAR_OUT : out std_logic; FAST_CLEAR_OUT : out std_logic; diff --git a/nxyter/source/nxyter_fee_board.vhd b/nxyter/source/nxyter_fee_board.vhd index 8a89422..4404c6c 100644 --- a/nxyter/source/nxyter_fee_board.vhd +++ b/nxyter/source/nxyter_fee_board.vhd @@ -22,7 +22,8 @@ entity nXyter_FEE_board is RESET_IN : in std_logic; CLK_NX_IN : in std_logic; CLK_ADC_IN : in std_logic; - + TRIGGER_OUT : out std_logic; + -- I2C Ports I2C_SDA_INOUT : inout std_logic; -- nXyter I2C fdata line I2C_SCL_INOUT : inout std_logic; -- nXyter I2C Clock line @@ -98,7 +99,7 @@ architecture Behavioral of nXyter_FEE_board is signal clk_250_o : std_logic; -- Bus Handler - constant NUM_PORTS : integer := 12; + constant NUM_PORTS : integer := 13; signal slv_read : std_logic_vector(NUM_PORTS-1 downto 0); signal slv_write : std_logic_vector(NUM_PORTS-1 downto 0); @@ -137,6 +138,11 @@ architecture Behavioral of nXyter_FEE_board is signal new_timestamp : std_logic_vector(31 downto 0); signal new_adc_data : std_logic_vector(11 downto 0); signal new_data : std_logic; + + -- Data Delay + signal new_timestamp_delayed : std_logic_vector(31 downto 0); + signal new_adc_data_delayed : std_logic_vector(11 downto 0); + signal new_data_delayed : std_logic; -- Data Validate signal timestamp : std_logic_vector(13 downto 0); @@ -168,7 +174,7 @@ architecture Behavioral of nXyter_FEE_board is -- Trigger Handler signal trigger : std_logic; - signal timestamp_hold : std_logic; + signal timestamp_trigger : std_logic; signal lvl2_trigger : std_logic; signal trigger_busy : std_logic; signal fast_clear : std_logic; @@ -176,8 +182,9 @@ architecture Behavioral of nXyter_FEE_board is signal fee_trg_release_o : std_logic; signal trigger_testpulse : std_logic; - -- FPGA Timestamp - signal timestamp_trigger : unsigned(11 downto 0); + -- FPGA Timestamp + signal timestamp_current : unsigned(11 downto 0); + signal timestamp_hold : unsigned(11 downto 0); signal nx_timestamp_sync : std_logic; -- Trigger Generator @@ -185,7 +192,7 @@ architecture Behavioral of nXyter_FEE_board is signal nx_testpulse_o : std_logic; -- Debug Handler - constant DEBUG_NUM_PORTS : integer := 12; + constant DEBUG_NUM_PORTS : integer := 13; signal debug_line : debug_array_t(0 to DEBUG_NUM_PORTS-1); begin @@ -200,7 +207,7 @@ begin -- DEBUG_LINE_OUT(15 downto 8) <= NX_TIMESTAMP_IN; -- DEBUG_LINE_OUT(4) <= nx_new_timestamp; -- DEBUG_LINE_OUT(5) <= timestamp_valid; --- DEBUG_LINE_OUT(6) <= timestamp_hold; +-- DEBUG_LINE_OUT(6) <= timestamp_trigger; -- DEBUG_LINE_OUT(7) <= nx_token_return; -- DEBUG_LINE_OUT(8) <= nx_nomore_data; -- DEBUG_LINE_OUT(9) <= trigger; @@ -260,7 +267,8 @@ begin 9 => x"0200", -- NX Register Setup 10 => x"0800", -- NX Histograms 11 => x"0020", -- Debug Handler - others => x"0000" + 12 => x"0130", -- Data Delay + others => x"0000" ), PORT_ADDR_MASK => ( 0 => 3, -- Control Register Handler @@ -270,12 +278,13 @@ begin 4 => 0, -- SPI Master 5 => 3, -- Trigger Generator 6 => 4, -- Data Validate - 7 => 1, -- Trigger Handler + 7 => 2, -- Trigger Handler 8 => 4, -- Trigger Validate 9 => 8, -- NX Register Setup 10 => 8, -- NX Histograms 11 => 0, -- Debug Handler - others => 0 + 12 => 2, -- Data Delay + others => 0 ), PORT_MASK_ENABLE => 1 @@ -332,7 +341,7 @@ begin I2C_REG_RESET_OUT => i2c_reg_reset_o, NX_TS_RESET_OUT => nx_ts_reset_1, OFFLINE_OUT => nxyter_offline, - --DEBUG_OUT => DEBUG_LINE_OUT + DEBUG_OUT => debug_line(0) ); @@ -356,7 +365,7 @@ begin SLV_ACK_OUT => slv_ack(9), SLV_NO_MORE_DATA_OUT => slv_no_more_data(9), SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(9), - --DEBUG_OUT => DEBUG_LINE_OUT + DEBUG_OUT => debug_line(1) ); @@ -384,7 +393,7 @@ begin SLV_ACK_OUT => slv_ack(1), SLV_NO_MORE_DATA_OUT => slv_no_more_data(1), SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(1), - --DEBUG_OUT => DEBUG_LINE_OUT + DEBUG_OUT => debug_line(2) ); @@ -413,7 +422,7 @@ begin SLV_ACK_OUT => slv_ack(4), SLV_NO_MORE_DATA_OUT => slv_no_more_data(4), SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(4), - -- DEBUG_OUT => DEBUG_LINE_OUT + DEBUG_OUT => debug_line(3) ); @@ -426,8 +435,9 @@ begin CLK_IN => CLK_NX_IN, RESET_IN => RESET_IN, TIMESTAMP_SYNC_IN => nx_ts_reset_o, - TRIGGER_IN => timestamp_hold, - TIMESTAMP_OUT => timestamp_trigger, + TRIGGER_IN => timestamp_trigger, + TIMESTAMP_CURRENT_OUT => timestamp_current, + TIMESTAMP_HOLD_OUT => timestamp_hold, NX_TIMESTAMP_SYNC_OUT => nx_timestamp_sync, SLV_READ_IN => open, SLV_WRITE_IN => open, @@ -436,7 +446,7 @@ begin SLV_ACK_OUT => open, SLV_NO_MORE_DATA_OUT => open, SLV_UNKNOWN_ADDR_OUT => open, - -- DEBUG_OUT => DEBUG_LINE_OUT + DEBUG_OUT => debug_line(4) ); @@ -470,7 +480,7 @@ begin LVL2_TRIGGER_BUSY_IN => trigger_evt_busy, VALIDATE_TRIGGER_OUT => trigger, - TIMESTAMP_HOLD_OUT => timestamp_hold, + TIMESTAMP_TRIGGER_OUT => timestamp_trigger, LVL2_TRIGGER_OUT => lvl2_trigger, EVENT_BUFFER_CLEAR_OUT => event_buffer_clear, FAST_CLEAR_OUT => fast_clear, @@ -487,7 +497,6 @@ begin SLV_NO_MORE_DATA_OUT => slv_no_more_data(7), SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(7), - --DEBUG_OUT => DEBUG_LINE_OUT DEBUG_OUT => debug_line(5) ); @@ -511,7 +520,7 @@ begin SLV_ACK_OUT => slv_ack(5), SLV_NO_MORE_DATA_OUT => slv_no_more_data(5), SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(5), - --DEBUG_OUT => DEBUG_LINE_OUT + DEBUG_OUT => debug_line(6) ); @@ -523,10 +532,11 @@ begin port map ( CLK_IN => CLK_IN, RESET_IN => RESET_IN, + TRIGGER_IN => lvl2_trigger, NX_TIMESTAMP_CLK_IN => NX_CLK128_IN, NX_TIMESTAMP_IN => NX_TIMESTAMP_IN, - + ADC_CLK_DAT_IN => CLK_ADC_IN, ADC_FCLK_IN => ADC_FCLK_IN, ADC_DCLK_IN => ADC_DCLK_IN, @@ -540,6 +550,8 @@ begin ADC_DATA_OUT => new_adc_data, NEW_DATA_OUT => new_data, + TIMESTAMP_CURRENT_IN => timestamp_current, + SLV_READ_IN => slv_read(2), SLV_WRITE_IN => slv_write(2), SLV_DATA_OUT => slv_data_rd(2*32+31 downto 2*32), @@ -548,9 +560,35 @@ begin SLV_ACK_OUT => slv_ack(2), SLV_NO_MORE_DATA_OUT => slv_no_more_data(2), SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(2), - --DEBUG_OUT => DEBUG_LINE_OUT DEBUG_OUT => debug_line(7) ); + +------------------------------------------------------------------------------- +-- NX and ADC Data Delay FIFO +------------------------------------------------------------------------------- + nx_data_delay_1: nx_data_delay + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + + NX_FRAME_IN => new_timestamp, + ADC_DATA_IN => new_adc_data, + NEW_DATA_IN => new_data, + NX_FRAME_OUT => new_timestamp_delayed, + ADC_DATA_OUT => new_adc_data_delayed, + NEW_DATA_OUT => new_data_delayed, + + SLV_READ_IN => slv_read(12), + SLV_WRITE_IN => slv_write(12), + SLV_DATA_OUT => slv_data_rd(12*32+31 downto 12*32), + SLV_DATA_IN => slv_data_wr(12*32+31 downto 12*32), + SLV_ADDR_IN => slv_addr(12*16+15 downto 12*16), + SLV_ACK_OUT => slv_ack(12), + SLV_NO_MORE_DATA_OUT => slv_no_more_data(12), + SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(12), + + DEBUG_OUT => debug_line(8) + ); ------------------------------------------------------------------------------- -- Timestamp Decoder and Valid Data Filter @@ -561,9 +599,9 @@ begin CLK_IN => CLK_IN, RESET_IN => RESET_IN, - NX_TIMESTAMP_IN => new_timestamp, - ADC_DATA_IN => new_adc_data, - NEW_DATA_IN => new_data, + NX_TIMESTAMP_IN => new_timestamp_delayed, + ADC_DATA_IN => new_adc_data_delayed, + NEW_DATA_IN => new_data_delayed, TIMESTAMP_OUT => timestamp, CHANNEL_OUT => timestamp_channel_id, @@ -582,8 +620,8 @@ begin SLV_ACK_OUT => slv_ack(6), SLV_NO_MORE_DATA_OUT => slv_no_more_data(6), SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(6), - --DEBUG_OUT => DEBUG_LINE_OUT - DEBUG_OUT => debug_line(8) + + DEBUG_OUT => debug_line(9) ); ------------------------------------------------------------------------------- @@ -591,6 +629,9 @@ begin ------------------------------------------------------------------------------- nx_trigger_validate_1: nx_trigger_validate + generic map ( + BOARD_ID => BOARD_ID + ) port map ( CLK_IN => CLK_IN, RESET_IN => RESET_IN, @@ -606,7 +647,7 @@ begin TRIGGER_IN => trigger, FAST_CLEAR_IN => fast_clear, TRIGGER_BUSY_OUT => trigger_validate_busy, - TIMESTAMP_REF_IN => timestamp_trigger, + TIMESTAMP_REF_IN => timestamp_hold, DATA_OUT => trigger_data, DATA_CLK_OUT => trigger_data_clk, @@ -623,8 +664,8 @@ begin SLV_ACK_OUT => slv_ack(8), SLV_NO_MORE_DATA_OUT => slv_no_more_data(8), SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(8), - --DEBUG_OUT => DEBUG_LINE_OUT - DEBUG_OUT => debug_line(9) + + DEBUG_OUT => debug_line(10) ); ------------------------------------------------------------------------------- @@ -663,8 +704,7 @@ begin SLV_NO_MORE_DATA_OUT => slv_no_more_data(3), SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(3), - --DEBUG_OUT => DEBUG_LINE_OUT - DEBUG_OUT => debug_line(10) + DEBUG_OUT => debug_line(11) ); nx_histograms_1: nx_histograms @@ -689,8 +729,7 @@ begin SLV_NO_MORE_DATA_OUT => slv_no_more_data(10), SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(10), - --DEBUG_OUT => DEBUG_LINE_OUT - DEBUG_OUT => debug_line(11) + DEBUG_OUT => debug_line(12) ); ------------------------------------------------------------------------------- diff --git a/nxyter/source/nxyter_registers.vhd b/nxyter/source/nxyter_registers.vhd index 9f98ad7..b9f5891 100644 --- a/nxyter/source/nxyter_registers.vhd +++ b/nxyter/source/nxyter_registers.vhd @@ -1,224 +1,224 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.nxyter_components.all; - -entity nxyter_registers is - port( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - - -- Slave bus - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_ADDR_IN : in std_logic_vector(15 downto 0); - SLV_ACK_OUT : out std_logic; - SLV_NO_MORE_DATA_OUT : out std_logic; - SLV_UNKNOWN_ADDR_OUT : out std_logic; - - -- Signals - I2C_SM_RESET_OUT : out std_logic; - I2C_REG_RESET_OUT : out std_logic; - NX_TS_RESET_OUT : out std_logic; - OFFLINE_OUT : out std_logic; - - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); -end entity; - -architecture Behavioral of nxyter_registers is - - signal slv_data_out_o : std_logic_vector(31 downto 0); - signal slv_no_more_data_o : std_logic; - signal slv_unknown_addr_o : std_logic; - signal slv_ack_o : std_logic; - - - -- I2C Reset - signal i2c_sm_reset_start : std_logic; - signal i2c_reg_reset_start : std_logic; - signal nx_ts_reset_start : std_logic; - - signal i2c_sm_reset_o : std_logic; - signal i2c_reg_reset_o : std_logic; - signal nx_ts_reset_o : std_logic; - signal offline_o : std_logic; - - type STATES is (S_IDLE, - S_I2C_SM_RESET, - S_I2C_SM_RESET_WAIT, - S_I2C_REG_RESET, - S_I2C_REG_RESET_WAIT, - S_NX_TS_RESET - ); - - signal STATE : STATES; - - -- Wait Timer - signal wait_timer_init : unsigned(7 downto 0); - signal wait_timer_done : std_logic; - -begin - - DEBUG_OUT(0) <= I2C_SM_RESET_OUT ; - DEBUG_OUT(1) <= I2C_REG_RESET_OUT; - DEBUG_OUT(2) <= NX_TS_RESET_OUT; - - DEBUG_OUT(15 downto 3) <= (others => '0'); - - nx_timer_1: nx_timer - generic map ( - CTR_WIDTH => 8 - ) - port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - TIMER_START_IN => wait_timer_init, - TIMER_DONE_OUT => wait_timer_done - ); - - ----------------------------------------------------------------------------- - -- I2C SM Reset - ----------------------------------------------------------------------------- - - PROC_I2C_SM_RESET: process(CLK_IN) - begin - if( rising_edge(CLK_IN) ) then - if( RESET_IN = '1' ) then - wait_timer_init <= (others => '0'); - i2c_sm_reset_o <= '0'; - i2c_reg_reset_o <= '0'; - nx_ts_reset_o <= '0'; - STATE <= S_IDLE; - else - i2c_sm_reset_o <= '0'; - i2c_reg_reset_o <= '0'; - nx_ts_reset_o <= '0'; - wait_timer_init <= (others => '0'); - - case STATE is - when S_IDLE => - if (i2c_sm_reset_start = '1') then - STATE <= S_I2C_SM_RESET; - elsif (i2c_reg_reset_start = '1') then - STATE <= S_I2C_REG_RESET; - elsif (nx_ts_reset_start = '1') then - STATE <= S_NX_TS_RESET; - else - STATE <= S_IDLE; - end if; - - when S_I2C_SM_RESET => - i2c_sm_reset_o <= '1'; - wait_timer_init <= x"8f"; - STATE <= S_I2C_SM_RESET_WAIT; - - when S_I2C_SM_RESET_WAIT => - i2c_sm_reset_o <= '1'; - if (wait_timer_done = '0') then - STATE <= S_I2C_SM_RESET_WAIT; - else - STATE <= S_IDLE; - end if; - - when S_I2C_REG_RESET => - i2c_reg_reset_o <= '1'; - wait_timer_init <= x"8f"; - STATE <= S_I2C_REG_RESET_WAIT; - - when S_I2C_REG_RESET_WAIT => - i2c_reg_reset_o <= '1'; - if (wait_timer_done = '0') then - STATE <= S_I2C_REG_RESET_WAIT; - else - STATE <= S_IDLE; - end if; - - when S_NX_TS_RESET => - nx_ts_reset_o <= '1'; - STATE <= S_IDLE; - - end case; - end if; - end if; - - end process PROC_I2C_SM_RESET; - - ----------------------------------------------------------------------------- - -- Slave Bus - ----------------------------------------------------------------------------- - - PROC_NX_REGISTERS: process(CLK_IN) - begin - if( rising_edge(CLK_IN) ) then - if( RESET_IN = '1' ) then - slv_data_out_o <= (others => '0'); - slv_no_more_data_o <= '0'; - slv_unknown_addr_o <= '0'; - slv_ack_o <= '0'; - - i2c_sm_reset_start <= '0'; - i2c_reg_reset_start <= '0'; - nx_ts_reset_start <= '0'; - offline_o <= '1'; - else - slv_ack_o <= '1'; - slv_unknown_addr_o <= '0'; - slv_no_more_data_o <= '0'; - slv_data_out_o <= (others => '0'); - i2c_sm_reset_start <= '0'; - i2c_reg_reset_start <= '0'; - nx_ts_reset_start <= '0'; - - if (SLV_WRITE_IN = '1') then - case SLV_ADDR_IN is - when x"0000" => - i2c_sm_reset_start <= '1'; - - when x"0001" => - i2c_reg_reset_start <= '1'; - - when x"0002" => - nx_ts_reset_start <= '1'; - - when x"0003" => - offline_o <= SLV_DATA_IN(0); - - when others => - slv_unknown_addr_o <= '1'; - slv_ack_o <= '0'; - end case; - - elsif (SLV_READ_IN = '1') then - case SLV_ADDR_IN is - when x"0003" => - slv_data_out_o(0) <= offline_o; - slv_data_out_o(31 downto 1) <= (others => '0'); - - when others => - slv_unknown_addr_o <= '1'; - slv_ack_o <= '0'; - end case; - - else - slv_ack_o <= '0'; - end if; - end if; - end if; - end process PROC_NX_REGISTERS; - --- Output Signals - SLV_DATA_OUT <= slv_data_out_o; - SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; - SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o; - SLV_ACK_OUT <= slv_ack_o; - - I2C_SM_RESET_OUT <= i2c_sm_reset_o; - I2C_REG_RESET_OUT <= i2c_reg_reset_o; - NX_TS_RESET_OUT <= nx_ts_reset_o; - OFFLINE_OUT <= offline_o; -end Behavioral; +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.nxyter_components.all; + +entity nxyter_registers is + port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + + -- Slave bus + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ADDR_IN : in std_logic_vector(15 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic; + + -- Signals + I2C_SM_RESET_OUT : out std_logic; + I2C_REG_RESET_OUT : out std_logic; + NX_TS_RESET_OUT : out std_logic; + OFFLINE_OUT : out std_logic; + + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); +end entity; + +architecture Behavioral of nxyter_registers is + + signal slv_data_out_o : std_logic_vector(31 downto 0); + signal slv_no_more_data_o : std_logic; + signal slv_unknown_addr_o : std_logic; + signal slv_ack_o : std_logic; + + + -- I2C Reset + signal i2c_sm_reset_start : std_logic; + signal i2c_reg_reset_start : std_logic; + signal nx_ts_reset_start : std_logic; + + signal i2c_sm_reset_o : std_logic; + signal i2c_reg_reset_o : std_logic; + signal nx_ts_reset_o : std_logic; + signal offline_o : std_logic; + + type STATES is (S_IDLE, + S_I2C_SM_RESET, + S_I2C_SM_RESET_WAIT, + S_I2C_REG_RESET, + S_I2C_REG_RESET_WAIT, + S_NX_TS_RESET + ); + + signal STATE : STATES; + + -- Wait Timer + signal wait_timer_init : unsigned(7 downto 0); + signal wait_timer_done : std_logic; + +begin + + DEBUG_OUT(0) <= I2C_SM_RESET_OUT ; + DEBUG_OUT(1) <= I2C_REG_RESET_OUT; + DEBUG_OUT(2) <= NX_TS_RESET_OUT; + + DEBUG_OUT(15 downto 3) <= (others => '0'); + + nx_timer_1: nx_timer + generic map ( + CTR_WIDTH => 8 + ) + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + TIMER_START_IN => wait_timer_init, + TIMER_DONE_OUT => wait_timer_done + ); + + ----------------------------------------------------------------------------- + -- I2C SM Reset + ----------------------------------------------------------------------------- + + PROC_I2C_SM_RESET: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + wait_timer_init <= (others => '0'); + i2c_sm_reset_o <= '0'; + i2c_reg_reset_o <= '0'; + nx_ts_reset_o <= '0'; + STATE <= S_IDLE; + else + i2c_sm_reset_o <= '0'; + i2c_reg_reset_o <= '0'; + nx_ts_reset_o <= '0'; + wait_timer_init <= (others => '0'); + + case STATE is + when S_IDLE => + if (i2c_sm_reset_start = '1') then + STATE <= S_I2C_SM_RESET; + elsif (i2c_reg_reset_start = '1') then + STATE <= S_I2C_REG_RESET; + elsif (nx_ts_reset_start = '1') then + STATE <= S_NX_TS_RESET; + else + STATE <= S_IDLE; + end if; + + when S_I2C_SM_RESET => + i2c_sm_reset_o <= '1'; + wait_timer_init <= x"8f"; + STATE <= S_I2C_SM_RESET_WAIT; + + when S_I2C_SM_RESET_WAIT => + i2c_sm_reset_o <= '1'; + if (wait_timer_done = '0') then + STATE <= S_I2C_SM_RESET_WAIT; + else + STATE <= S_IDLE; + end if; + + when S_I2C_REG_RESET => + i2c_reg_reset_o <= '1'; + wait_timer_init <= x"8f"; + STATE <= S_I2C_REG_RESET_WAIT; + + when S_I2C_REG_RESET_WAIT => + i2c_reg_reset_o <= '1'; + if (wait_timer_done = '0') then + STATE <= S_I2C_REG_RESET_WAIT; + else + STATE <= S_IDLE; + end if; + + when S_NX_TS_RESET => + nx_ts_reset_o <= '1'; + STATE <= S_IDLE; + + end case; + end if; + end if; + + end process PROC_I2C_SM_RESET; + + ----------------------------------------------------------------------------- + -- Slave Bus + ----------------------------------------------------------------------------- + + PROC_NX_REGISTERS: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + slv_data_out_o <= (others => '0'); + slv_no_more_data_o <= '0'; + slv_unknown_addr_o <= '0'; + slv_ack_o <= '0'; + + i2c_sm_reset_start <= '0'; + i2c_reg_reset_start <= '0'; + nx_ts_reset_start <= '0'; + offline_o <= '1'; + else + slv_ack_o <= '1'; + slv_unknown_addr_o <= '0'; + slv_no_more_data_o <= '0'; + slv_data_out_o <= (others => '0'); + i2c_sm_reset_start <= '0'; + i2c_reg_reset_start <= '0'; + nx_ts_reset_start <= '0'; + + if (SLV_WRITE_IN = '1') then + case SLV_ADDR_IN is + when x"0000" => + i2c_sm_reset_start <= '1'; + + when x"0001" => + i2c_reg_reset_start <= '1'; + + when x"0002" => + nx_ts_reset_start <= '1'; + + when x"0003" => + offline_o <= SLV_DATA_IN(0); + + when others => + slv_unknown_addr_o <= '1'; + slv_ack_o <= '0'; + end case; + + elsif (SLV_READ_IN = '1') then + case SLV_ADDR_IN is + when x"0003" => + slv_data_out_o(0) <= offline_o; + slv_data_out_o(31 downto 1) <= (others => '0'); + + when others => + slv_unknown_addr_o <= '1'; + slv_ack_o <= '0'; + end case; + + else + slv_ack_o <= '0'; + end if; + end if; + end if; + end process PROC_NX_REGISTERS; + +-- Output Signals + SLV_DATA_OUT <= slv_data_out_o; + SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; + SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o; + SLV_ACK_OUT <= slv_ack_o; + + I2C_SM_RESET_OUT <= i2c_sm_reset_o; + I2C_REG_RESET_OUT <= i2c_reg_reset_o; + NX_TS_RESET_OUT <= nx_ts_reset_o; + OFFLINE_OUT <= offline_o; +end Behavioral; diff --git a/nxyter/source/registers.txt b/nxyter/source/registers.txt index ef9beb5..23a706d 100644 --- a/nxyter/source/registers.txt +++ b/nxyter/source/registers.txt @@ -4,26 +4,13 @@ 0x8102 : w w: Reset and Sync Timestamps (nXyter and FPGA) 0x8103 : r/w Put nxyter into offline mode --- NX Data Validate -0x8120 : r/w Invalid Frame Counter (16 bit) / w: clear all counters -0x8121 : r Overflow Counter (16 bit) -0x8122 : r Pileup Counter (16 bit) -0x8123 : r Parity Error Counter (16 bit) -0x8124 : r Trigger Rate (in kHz) - --- NX Trigger Validate -0x8180 : r/w Readout Mode (0:Ref + valid + window, 1: Ref + Valid - 3: Raw and TimeStamp + valid, - 4: Raw, 5: Raw + Valid ) -0x8181 : r/w Trigger Window Delay (12 bit, in 3.9ns) -0x8182 : r/w Trigger Window Width (12 bit, in 3.9ns) -0x8183 : r/w Readout Time Max (12 bit, in 10ns) -0x8184 : r Busy Time Counter (12 bit, in 10ns) - -0x8185 : r done counter -0x8186 : r done counter -0x8187 : r done counter -0x8188 : r done counter +-- NX I2C Setup Handler +0x8200 : r/w I2C Memeory Register (Depth: 0 - 45 ... 0x822c) +0x8260 : r/w DAC Register Memory (Depth: 0 - 128 ... 0x82e0) +0x8240 : w Read all I2C Registers into Memory +0x8241 : w Write all Memory to I2C Registers +0x8242 : w Read Trim DAC Register(129 deep FIFO) to Memory +0x8243 : w Write Memory to Trim DAC Register(129 deep FIFO) -- Trigger Generator 0x8140 : w If writing just start trigger cycle, keep current setting @@ -31,10 +18,12 @@ 0x8142 : r/w Bit0 7-0 : number of triggers to be sent consecutive 0x8143 : r/w Bit 15-0 : Length of trigger pulse (in 10ns), if 0: skip it 0x8144 : r/w Bit0 : 1: send timestamp-reset before trigger +0x8145 : r : Testpulse Rate (in Hz) -- Trigger Handler -0x8160 : r/w Bit 15-0 : Delay Timestamp Hold signal (8bit, 10ns) +0x8160 : r/w Bit 15-0 : Delay Timestamp Hold Signal (8bit, 10ns) 0x8161 : r/w Bit 0 : Enable Testpulse Signal (default: off) +0x8162 : r : Accepted Trigger Rate (in Hz) -- NX Data Receiver 0x8500 : r current Timestamp FIFO value @@ -42,15 +31,13 @@ 0: fifo_full 1: fifo_empty 2: fifo_almost_empty - 4..29: ignore + 3..29: ignore 31: nx_frame_synced w: pll reset 0x8502 : r/w r: Resync Counter(12bit) w: clear Resync Counter 0x8503 : r/w r: Parity Error Counter (12bit) w: clear Parity Error Counter -0x8504 : r/w FIFO Delay, i.e. Trigger Delay (6Bit, in 31.25ns, range 2..60) - default: 8 0x8505 : r/w ADC CLK Delay 4ns steps (3Bit: range 0..7) 0: 4ns after frame_valid 1: 8ns -------"--------- @@ -58,7 +45,37 @@ 6: 28ns -------"--------- 7: 32ns -------"--------- <= this shoud be correct i.e. 2ns before new frame clock -0x8506 : r current ADC FIFO value +0x8506 : r/w debug multiplexer: + 0: no ADC Values, normal Debug + 1: ADC Value Nxyter + 2: ADC Value Testchannel +0x8507 : r current ADC FIFO value + +-- NX Data Delay +0x8130 : r/w FIFO Delay, i.e. Trigger Delay (7Bit, in 10ns, Range 2..120) + default: 10 + +-- NX Data Validate +0x8120 : r/w Invalid Frame Counter (16 bit) / w: clear all counters +0x8121 : r Overflow Counter (16 bit) +0x8122 : r Pileup Counter (16 bit) +0x8123 : r Parity Error Counter (16 bit) +0x8124 : r Trigger Rate (in Hz) +0x8125 : r Frame Rate (in Hz) + +-- NX Trigger Validate +0x8180 : r/w Readout Mode (0:Ref + valid + window, 1: Ref + Valid + 3: Raw and TimeStamp + valid, + 4: Raw, 5: Raw + Valid ) +0x8181 : r/w Trigger Window Delay (12 bit, in 3.9ns) +0x8182 : r/w Trigger Window Width (12 bit, in 3.9ns) +0x8183 : r/w Readout Time Max (12 bit, in 10ns) +0x8184 : r Busy Time Counter (12 bit, in 10ns) + +0x8185 : r done counter +0x8186 : r done counter +0x8187 : r done counter +0x8188 : r done counter -- Event Data Buffer 0x8600 : r read FIFO buffer @@ -66,22 +83,20 @@ 0x8602 : r FIFO flush counter 0x8603 : r read FIFO status +--- DEBUG ------------------------------------------------------------ + -- I2C Master 0x8040 : Access to I2C Interface Chip Ids: 0x08 : nXyter 0x29 : AD7991-1 0x50 : EEPROM - -- SPI Master 0x8060 : Access to SPI Interface --- NX I2C Setup Handler -0x8200 : r/w I2C Memeory Register (Depth: 0 - 45 ... 0x822c) -0x8260 : r/w DAC Register Memory (Depth: 0 - 129 ... 0x82e0) -0x8240 : w Read all I2C Registers into Memory -0x8241 : w Write all Memory to I2C Registers -0x8242 : w Read Trim DAC Register(129 deep FIFO) to Memory -0x8243 : w Write Memory to Trim DAC Register(129 deep FIFO) +-- Histogram Handler +0x8800 : r: Read Channel Statistic (128 channel in a row) + w: reset all Histograms +0x8880 : r: Read Channel Trigger Rate (128 channel in a row, 1/s) -- Debug Multiplexer 0x8020 : r/w Select Debug Entity @@ -93,8 +108,9 @@ 5: nx_trigger_handler 6: nx_trigger_generator 7: nx_data_receiver - 8: nx_data_validate - 9: nx_trigger_validate - 10: nx_event_buffer - 11: nx_histograms + 8: nx_data_delay + 9: nx_data_validate + 10: nx_trigger_validate + 11: nx_event_buffer + 12: nx_histograms diff --git a/nxyter/trb3_periph.prj b/nxyter/trb3_periph.prj index 87acf58..4f94a06 100644 --- a/nxyter/trb3_periph.prj +++ b/nxyter/trb3_periph.prj @@ -148,6 +148,7 @@ add_file -vhdl -lib "work" "cores/pll_nx_clk250.vhd" add_file -vhdl -lib "work" "cores/pll_adc_clk32.vhd" add_file -vhdl -lib "work" "cores/pll_adc_clk192.vhd" add_file -vhdl -lib "work" "cores/fifo_ts_32to32_dc.vhd" +add_file -vhdl -lib "work" "cores/fifo_44_data_delay.vhd" add_file -vhdl -lib "work" "cores/fifo_32_data.vhd" add_file -vhdl -lib "work" "trb3_periph.vhd" @@ -162,6 +163,7 @@ add_file -vhdl -lib "work" "source/debug_multiplexer.vhd" add_file -vhdl -lib "work" "source/nxyter_fee_board.vhd" add_file -vhdl -lib "work" "source/nx_data_receiver.vhd" +add_file -vhdl -lib "work" "source/nx_data_delay.vhd" add_file -vhdl -lib "work" "source/nx_data_validate.vhd" add_file -vhdl -lib "work" "source/nx_trigger_validate.vhd" add_file -vhdl -lib "work" "source/nx_event_buffer.vhd" diff --git a/nxyter/trb3_periph.vhd b/nxyter/trb3_periph.vhd index 583f1b2..a4f3a18 100644 --- a/nxyter/trb3_periph.vhd +++ b/nxyter/trb3_periph.vhd @@ -65,7 +65,7 @@ entity trb3_periph is NX1B_ADC_B_IN : in std_logic; NX1B_ADC_NX_IN : in std_logic; NX1B_ADC_D_IN : in std_logic; - + --Connections to NXYTER-FEB 2 NX2_RESET_OUT : out std_logic; @@ -93,7 +93,9 @@ entity trb3_periph is NX2B_ADC_B_IN : in std_logic; NX2B_ADC_NX_IN : in std_logic; NX2B_ADC_D_IN : in std_logic; - + + ADDON_TRIGGER_OUT : out std_logic; + --------------------------------------------------------------------------- -- END AddonBoard nXyter --------------------------------------------------------------------------- @@ -274,7 +276,7 @@ architecture trb3_periph_arch of trb3_periph is signal time_counter : unsigned(31 downto 0); - -- nXyter-FEE-Board Clocks + -- nXyter-FEB-Board Clocks signal nx_clk256 : std_logic; signal pll_lock_clk256 : std_logic; signal clk_adc_dat : std_logic; @@ -294,7 +296,8 @@ architecture trb3_periph_arch of trb3_periph is signal nx1_timestamp_sim_o : std_logic_vector(7 downto 0); signal nx1_clk128_sim_o : std_logic; - + signal fee1_trigger : std_logic; + -- nXyter 2 Regio Bus signal nx2_regio_addr_in : std_logic_vector (15 downto 0); signal nx2_regio_data_in : std_logic_vector (31 downto 0); @@ -309,7 +312,8 @@ architecture trb3_periph_arch of trb3_periph is signal nx2_timestamp_sim_o : std_logic_vector(7 downto 0); signal nx2_clk128_sim_o : std_logic; - + signal fee2_trigger : std_logic; + begin --------------------------------------------------------------------------- -- Reset Generation @@ -404,7 +408,7 @@ begin BROADCAST_SPECIAL_ADDR => x"48", REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)), REGIO_HARDWARE_VERSION => x"9100_6000", - REGIO_INIT_ADDRESS => x"1100", + REGIO_INIT_ADDRESS => x"8900", REGIO_USE_VAR_ENDPOINT_ID => c_YES, CLOCK_FREQUENCY => 125, TIMING_TRIGGER_RAW => c_YES, @@ -434,7 +438,7 @@ begin --Timing trigger in TRG_TIMING_TRG_RECEIVED_IN => timing_trg_received_i, - --LVL1 trigger to FEE + --LVL1 trigger to FEB LVL1_TRG_DATA_VALID_OUT => trg_data_valid_i, LVL1_VALID_TIMING_TRG_OUT => trg_timing_valid_i, LVL1_VALID_NOTIMING_TRG_OUT => trg_notiming_valid_i, @@ -453,7 +457,7 @@ begin TRG_MISSING_TMG_TRG_OUT => trg_missing_tmg_trg_i, TRG_SPIKE_DETECTED_OUT => trg_spike_detected_i, - --Response from FEE, i.e. nXyter #0 + --Response from FEB, i.e. nXyter #0 FEE_TRG_RELEASE_IN(0) => fee_trg_release_i(0), FEE_TRG_STATUSBITS_IN(0*32+31 downto 0*32) => fee_trg_statusbits_i(0*32+31 downto 0*32), FEE_DATA_IN(0*32+31 downto 0*32) => fee_data_i(0*32+31 downto 0*32), @@ -695,7 +699,8 @@ begin RESET_IN => reset_i, CLK_NX_IN => nx_clk256, CLK_ADC_IN => clk_adc_dat, - + TRIGGER_OUT => fee1_trigger, + I2C_SDA_INOUT => NX1_I2C_SDA_INOUT, I2C_SCL_INOUT => NX1_I2C_SCL_INOUT, I2C_SM_RESET_OUT => NX1_I2C_SM_RESET_OUT, @@ -712,7 +717,7 @@ begin NX_RESET_OUT => NX1_RESET_OUT, NX_TESTPULSE_OUT => NX1_TESTPULSE_OUT, - + ADC_FCLK_IN(0) => NX1_ADC_FCLK_IN, ADC_FCLK_IN(1) => NX1B_ADC_FCLK_IN, ADC_DCLK_IN(0) => NX1_ADC_DCLK_IN, @@ -736,7 +741,7 @@ begin LVL1_TRG_CODE_IN => trg_code_i, LVL1_TRG_INFORMATION_IN => trg_information_i, LVL1_INT_TRG_NUMBER_IN => trg_int_number_i, - + FEE_TRG_RELEASE_OUT => fee_trg_release_i(0), FEE_TRG_STATUSBITS_OUT => fee_trg_statusbits_i(31 downto 0), FEE_DATA_OUT => fee_data_i(31 downto 0), @@ -772,7 +777,8 @@ begin RESET_IN => reset_i, CLK_NX_IN => nx_clk256, CLK_ADC_IN => clk_adc_dat, - + TRIGGER_OUT => fee2_trigger, + I2C_SDA_INOUT => NX2_I2C_SDA_INOUT, I2C_SCL_INOUT => NX2_I2C_SCL_INOUT, I2C_SM_RESET_OUT => NX2_I2C_SM_RESET_OUT, @@ -834,6 +840,9 @@ begin DEBUG_LINE_OUT => open ); + + ADDON_TRIGGER_OUT <= fee1_trigger or fee2_trigger; + ----------------------------------------------------------------------------- -- nXyter common Clocks ----------------------------------------------------------------------------- -- 2.43.0