From b6a1790e3b81baf10893f5859cc29ae1a96f908e Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Mon, 19 Nov 2018 11:24:40 +0100 Subject: [PATCH] remove log files --- base/cores/ecp3/PLL/generate_core.tcl | 100 ---------------------- base/cores/ecp3/PLL/generate_ngd.tcl | 115 -------------------------- base/cores/ecp3/PLL/msg_file.log | 29 ------- 3 files changed, 244 deletions(-) delete mode 100644 base/cores/ecp3/PLL/generate_core.tcl delete mode 100644 base/cores/ecp3/PLL/generate_ngd.tcl delete mode 100644 base/cores/ecp3/PLL/msg_file.log diff --git a/base/cores/ecp3/PLL/generate_core.tcl b/base/cores/ecp3/PLL/generate_core.tcl deleted file mode 100644 index aa2cbac..0000000 --- a/base/cores/ecp3/PLL/generate_core.tcl +++ /dev/null @@ -1,100 +0,0 @@ -#!/usr/local/bin/wish - -proc GetPlatform {} { - global tcl_platform - - set cpu $tcl_platform(machine) - - switch $cpu { - intel - - i*86* { - set cpu ix86 - } - x86_64 { - if {$tcl_platform(wordSize) == 4} { - set cpu ix86 - } - } - } - - switch $tcl_platform(platform) { - windows { - if {$cpu == "amd64"} { - # Do not check wordSize, win32-x64 is an IL32P64 platform. - set cpu x86_64 - } - if {$cpu == "x86_64"} { - return "nt64" - } else { - return "nt" - } - } - unix { - if {$tcl_platform(os) == "Linux"} { - if {$cpu == "x86_64"} { - return "lin64" - } else { - return "lin" - } - } else { - return "sol" - } - } - } - return "nt" -} - -proc GetCmdLine {lpcfile} { - global Para - - if [catch {open $lpcfile r} fileid] { - puts "Cannot open $para_file file!" - exit -1 - } - - seek $fileid 0 start - set default_match 0 - while {[gets $fileid line] >= 0} { - if {[string first "\[Command\]" $line] == 0} { - set default_match 1 - continue - } - if {[string first "\[" $line] == 0} { - set default_match 0 - } - if {$default_match == 1} { - if [regexp {([^=]*)=(.*)} $line match parameter value] { - if [regexp {([ |\t]*;)} $parameter match] {continue} - if [regexp {(.*)[ |\t]*;} $value match temp] { - set Para($parameter) $temp - } else { - set Para($parameter) $value - } - } - } - } - set default_match 0 - close $fileid - - return $Para(cmd_line) -} - -set platformpath [GetPlatform] -set Para(sbp_path) [file dirname [info script]] -set Para(install_dir) $env(TOOLRTF) -set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]" - -set scuba "$Para(FPGAPath)/scuba" -set modulename "pll_in125_out33" -set lang "vhdl" -set lpcfile "$Para(sbp_path)/$modulename.lpc" -set arch "ep5c00" -set cmd_line [GetCmdLine $lpcfile] -set fdcfile "$Para(sbp_path)/$modulename.fdc" -if {[file exists $fdcfile] == 0} { - append scuba " " $cmd_line -} else { - append scuba " " $cmd_line " " -fdc " " $fdcfile -} -set Para(result) [catch {eval exec "$scuba"} msg] -#puts $msg diff --git a/base/cores/ecp3/PLL/generate_ngd.tcl b/base/cores/ecp3/PLL/generate_ngd.tcl deleted file mode 100644 index 59c0863..0000000 --- a/base/cores/ecp3/PLL/generate_ngd.tcl +++ /dev/null @@ -1,115 +0,0 @@ -#!/usr/local/bin/wish - -proc GetPlatform {} { - global tcl_platform - - set cpu $tcl_platform(machine) - - switch $cpu { - intel - - i*86* { - set cpu ix86 - } - x86_64 { - if {$tcl_platform(wordSize) == 4} { - set cpu ix86 - } - } - } - - switch $tcl_platform(platform) { - windows { - if {$cpu == "amd64"} { - # Do not check wordSize, win32-x64 is an IL32P64 platform. - set cpu x86_64 - } - if {$cpu == "x86_64"} { - return "nt64" - } else { - return "nt" - } - } - unix { - if {$tcl_platform(os) == "Linux"} { - if {$cpu == "x86_64"} { - return "lin64" - } else { - return "lin" - } - } else { - return "sol" - } - } - } - return "nt" -} - -set platformpath [GetPlatform] -set Para(sbp_path) [file dirname [info script]] -set Para(install_dir) $env(TOOLRTF) -set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]" -set Para(bin_dir) "[file join $Para(install_dir) bin $platformpath]" - -set Para(ModuleName) "pll_in125_out33" -set Para(Module) "PLL" -set Para(libname) latticeecp3 -set Para(arch_name) ep5c00 -set Para(PartType) "LFE3-150EA" - -set Para(tech_syn) latticeecp3 -set Para(tech_cae) latticeecp3 -set Para(Package) "FPBGA672" -set Para(SpeedGrade) "8" -set Para(FMax) "100" -set fdcfile "$Para(sbp_path)/$Para(ModuleName).fdc" - -#create response file(*.cmd) for Synpwrap -proc CreateCmdFile {} { - global Para - - file mkdir "$Para(sbp_path)/syn_results" - if [catch {open $Para(ModuleName).cmd w} rspFile] { - puts "Cannot create response file $Para(ModuleName).cmd." - exit -1 - } else { - puts $rspFile "PROJECT: $Para(ModuleName) - working_path: \"$Para(sbp_path)/syn_results\" - module: $Para(ModuleName) - verilog_file_list: \"$Para(sbp_path)/$Para(ModuleName).vhd\" - vlog_std_v2001: true - constraint_file_name: \"$Para(sbp_path)/$Para(ModuleName).fdc\" - suffix_name: edn - output_file_name: $Para(ModuleName) - write_prf: true - disable_io_insertion: true - force_gsr: false - frequency: $Para(FMax) - fanout_limit: 50 - retiming: false - pipe: false - part: $Para(PartType) - speed_grade: $Para(SpeedGrade) - " - close $rspFile - } -} - -#synpwrap -CreateCmdFile -set synpwrap "$Para(bin_dir)/synpwrap" -if {[file exists $fdcfile] == 0} { - set Para(result) [catch {eval exec $synpwrap -rem -e $Para(ModuleName) -target $Para(tech_syn)} msg] -} else { - set Para(result) [catch {eval exec $synpwrap -rem -e $Para(ModuleName) -target $Para(tech_syn) -fdc $fdcfile} msg] -} -#puts $msg - -#edif2ngd -set edif2ngd "$Para(FPGAPath)/edif2ngd" -set Para(result) [catch {eval exec $edif2ngd -l $Para(libname) -d $Para(PartType) -nopropwarn \"syn_results/$Para(ModuleName).edn\" $Para(ModuleName).ngo} msg] -#puts $msg - -#ngdbuild -set ngdbuild "$Para(FPGAPath)/ngdbuild" -set Para(result) [catch {eval exec $ngdbuild -addiobuf -dt -a $Para(arch_name) $Para(ModuleName).ngo $Para(ModuleName).ngd} msg] -#puts $msg diff --git a/base/cores/ecp3/PLL/msg_file.log b/base/cores/ecp3/PLL/msg_file.log deleted file mode 100644 index f792fdd..0000000 --- a/base/cores/ecp3/PLL/msg_file.log +++ /dev/null @@ -1,29 +0,0 @@ -SCUBA, Version Diamond (64-bit) 3.4.0.80 -Mon May 11 08:53:40 2015 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved. - -BEGIN SCUBA Module Synthesis - - Issued command : /opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n pll_in125_out33 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 125 -phase_cntl STATIC -fclkop 33.3 -fclkop_tol 0.2 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw - Circuit name : pll_in125_out33 - Module type : pll - Module Version : 5.7 - Ports : - Inputs : CLK - Outputs : CLKOP, LOCK - I/O buffer : not inserted - EDIF output : pll_in125_out33.edn - VHDL output : pll_in125_out33.vhd - VHDL template : pll_in125_out33_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : not used - Report output : pll_in125_out33.srp - Estimated Resource Usage: - -END SCUBA Module Synthesis - -- 2.43.0