From b6de17515562f95e5d5d41639f953969937f4560 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Thu, 25 Aug 2016 17:09:46 +0200 Subject: [PATCH] Fixing conflicts due to reformatting of code --- dirich/dirich.vhd | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/dirich/dirich.vhd b/dirich/dirich.vhd index 2b603d5..06fe157 100644 --- a/dirich/dirich.vhd +++ b/dirich/dirich.vhd @@ -104,7 +104,13 @@ architecture dirich_arch of dirich is signal los_count : unsigned(23 downto 0); attribute syn_keep of GSR_N : signal is true; - attribute syn_preserve of GSR_N : signal is true; + attribute syn_preserve of GSR_N : signal is true; + +-- type a_t is array(0 to 15) of std_logic_vector(4000 downto 0); +-- signal c : a_t; +-- attribute syn_keep of c : signal is true; +-- attribute syn_preserve of c : signal is true; + component usrmclk @@ -353,6 +359,7 @@ begin hdr_io(8) <= TEST_LINE(9); TEST_LINE(10) <= hdr_io(9); TEST_LINE(14 downto 11) <= time_counter(31 downto 28); +-- TEST_LINE(14 downto 1) <= med2int(0).stat_op(13) & clear_i & reset_i & med_stat_debug(18 downto 8); --------------------------------------------------------------------------- -- LCD Data to display @@ -369,12 +376,14 @@ begin --------------------------------------------------------------------------- -- LED --------------------------------------------------------------------------- + LED_GREEN <= not med2int(0).stat_op(9) or led_off; LED_ORANGE <= debug_clock_reset(0) or led_off; LED_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)) or led_off; LED_YELLOW <= led_los_lock or led_off; + --------------------------------------------------------------------------- -- Test Circuits --------------------------------------------------------------------------- @@ -430,6 +439,20 @@ begin end generate Gen_Hit_In_Signals; end generate; + +-- gen_chains : for i in 0 to 15 generate +-- process begin +-- wait until rising_edge(CLOCK_IN); +-- c(i)(4000 downto 1) <= c(i)(3999 downto 0); +-- c(i)(0) <= not c(i)(0) or INPUT(i+1); +-- PWM(i+1) <= c(i)(4000); +-- if reset_i = '1' then +-- c(i)(4000 downto 0) <= (others => '0'); +-- end if; +-- end process; +-- +-- end generate; + end architecture; -- 2.43.0