From b6eb2d1f1e142d203215fb75dbb2c2f7dcaef9aa Mon Sep 17 00:00:00 2001 From: Tobias Weber Date: Fri, 10 Oct 2014 16:02:58 +0100 Subject: [PATCH] Readout is working with somewhat faulty readout data. The event trailer of last event is send first then event header with the data. This is followd by strange data words and the data trailer. --- mupix/sources/EventBuffer.vhd | 24 +++++++++------- mupix/sources/MuPix3_board.vhd | 17 ++++++----- mupix/sources/MuPix3_interface.vhd | 46 +++++++++++++++--------------- mupix/sources/TriggerHandler.vhd | 37 +++++++++++++++--------- mupix/sources/mupix_components.vhd | 4 ++- mupix/trb3_periph.vhd | 4 +-- 6 files changed, 76 insertions(+), 56 deletions(-) diff --git a/mupix/sources/EventBuffer.vhd b/mupix/sources/EventBuffer.vhd index c2fb237..5bc51ff 100644 --- a/mupix/sources/EventBuffer.vhd +++ b/mupix/sources/EventBuffer.vhd @@ -52,15 +52,15 @@ architecture behavioral of eventbuffer is signal fee_data_finished_int : std_logic := '0'; --fifo signals - signal fifo_reset : std_logic; + signal fifo_reset : std_logic := '0'; signal fifo_full : std_logic; signal fifo_empty : std_logic; - signal fifo_write : std_logic; - signal fifo_status : std_logic_vector(31 downto 0); - signal fifo_write_ctr : std_logic_vector(10 downto 0); - signal fifo_data_in : std_logic_vector(31 downto 0); - signal fifo_data_out : std_logic_vector(31 downto 0); - signal fifo_read_enable : std_logic; + signal fifo_write : std_logic := '0'; + signal fifo_status : std_logic_vector(31 downto 0) := (others => '0'); + signal fifo_write_ctr : std_logic_vector(10 downto 0) := (others => '0'); + signal fifo_data_in : std_logic_vector(31 downto 0) := (others => '0'); + signal fifo_data_out : std_logic_vector(31 downto 0) := (others => '0'); + signal fifo_read_enable : std_logic := '0'; --fifo readout via slv_bus type fifo_read_s_states is (idle, wait1, wait2, done); @@ -130,9 +130,13 @@ begin -- behavioral when idle => fifo_read_f_fsm <= idle; if valid_trigger_in = '1' then - fifo_read_f <= '1'; - fifo_read_busy_f <= '1'; - fifo_read_f_fsm <= wait_for_data; + if fifo_empty = '1' then + fifo_read_f_fsm <= done; + else + fifo_read_f <= '1'; + fifo_read_busy_f <= '1'; + fifo_read_f_fsm <= wait_for_data; + end if; end if; when wait_for_data => fifo_read_f <= '1'; diff --git a/mupix/sources/MuPix3_board.vhd b/mupix/sources/MuPix3_board.vhd index 503e454..60ab42e 100644 --- a/mupix/sources/MuPix3_board.vhd +++ b/mupix/sources/MuPix3_board.vhd @@ -94,7 +94,7 @@ architecture Behavioral of MuPix3_Board is --data from mupix interface signal memdata : std_logic_vector(31 downto 0); signal memwren : std_logic; - signal ro_busy : std_logic; + signal ro_mupix_busy : std_logic; --data from event buffer signal buffer_data : std_logic_vector(31 downto 0); @@ -106,6 +106,7 @@ architecture Behavioral of MuPix3_Board is signal status_trigger : std_logic; signal buffer_fast_clear : std_logic; signal flush_buffer : std_logic; + signal trigger_busy_mupix_data_int : std_logic; -- synced signals from board interface signal timestamp_from_mupix_sync : std_logic_vector(7 downto 0); @@ -187,7 +188,7 @@ begin -- Behavioral board_interface_1: entity work.board_interface port map ( - clk_in => clk_in, + clk_in => clk, timestamp_from_mupix => timestamp_from_mupix, rowaddr_from_mupix => rowaddr_from_mupix, coladdr_from_mupix => coladdr_from_mupix, @@ -229,7 +230,8 @@ begin -- Behavioral hit_time => timestamp_from_mupix_sync, memdata => memdata, memwren => memwren, - ro_busy => ro_busy, + trigger_ext => valid_trigger_int, + ro_busy => ro_mupix_busy, SLV_READ_IN => slv_read(0), SLV_WRITE_IN => slv_write(0), SLV_DATA_OUT => slv_data_rd(0*32+31 downto 0*32), @@ -316,12 +318,12 @@ begin -- Behavioral Reset => reset, MuPixData_in => memdata, MuPixDataWr_in => memwren, - MuPixEndOfEvent_in => ro_busy, + MuPixEndOfEvent_in => ro_mupix_busy, FEE_DATA_OUT => buffer_data, FEE_DATA_WRITE_OUT => buffer_data_valid, FEE_DATA_FINISHED_OUT => open, FEE_DATA_ALMOST_FULL_IN => FEE_DATA_ALMOST_FULL_IN, - valid_trigger_in => flush_buffer_int, + valid_trigger_in => flush_buffer, clear_buffer_in => buffer_fast_clear, SLV_READ_IN => slv_read(5), SLV_WRITE_IN => slv_write(5), @@ -354,7 +356,8 @@ begin -- Behavioral FEE_TRG_STATUSBITS_OUT => FEE_TRG_STATUSBITS_OUT, FEE_DATA_0_IN => buffer_data, FEE_DATA_WRITE_0_IN => buffer_data_valid, - TRIGGER_BUSY_MUPIX_DATA_IN => ro_busy or buffer_data_valid, + TRIGGER_BUSY_MUPIX_READ_IN => ro_mupix_busy, + TRIGGER_BUSY_FIFO_READ_IN => buffer_data_valid, VALID_TRIGGER_OUT => valid_trigger_int, TRIGGER_TIMING_OUT => timing_trigger, TRIGGER_STATUS_OUT => status_trigger, @@ -364,7 +367,7 @@ begin -- Behavioral SLV_WRITE_IN => slv_write(6), SLV_DATA_OUT => slv_data_rd(6*32+31 downto 6*32), SLV_DATA_IN => slv_data_wr(6*32+31 downto 6*32), - SLV_ADDR_IN => slv_addr(6*32+31 downto 6*32), + SLV_ADDR_IN => slv_addr(6*16+15 downto 6*16), SLV_ACK_OUT => slv_ack(6), SLV_NO_MORE_DATA_OUT => slv_no_more_data(6), SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(6)); diff --git a/mupix/sources/MuPix3_interface.vhd b/mupix/sources/MuPix3_interface.vhd index e996794..66163c5 100644 --- a/mupix/sources/MuPix3_interface.vhd +++ b/mupix/sources/MuPix3_interface.vhd @@ -54,41 +54,41 @@ architecture RTL of mupix_interface is type ro_state_type is (reset, waiting, readman, loadpix, pulld, loadcol, readcol, hitgenerator, hitgeneratorwait,pause); - signal state : ro_state_type; + signal state : ro_state_type := waiting; - signal delcounter : unsigned(3 downto 0); - signal delaycounters : std_logic_vector(31 downto 0); - signal pauseregister : std_logic_vector(31 downto 0); - signal pausecounter : unsigned (31 downto 0); - signal ro_busy_int : std_logic; - signal graycount : std_logic_vector(7 downto 0); - signal eventcounter : unsigned(31 downto 0); - signal hitcounter : unsigned(10 downto 0); + signal delcounter : unsigned(3 downto 0) := (others => '0'); + signal delaycounters : std_logic_vector(31 downto 0) := (others => '0'); + signal pauseregister : std_logic_vector(31 downto 0) := (others => '0'); + signal pausecounter : unsigned (31 downto 0) := (others => '0'); + signal ro_busy_int : std_logic := '0'; + signal graycount : std_logic_vector(7 downto 0) := (others => '0'); + signal eventcounter : unsigned(31 downto 0) := (others => '0'); + signal hitcounter : unsigned(10 downto 0) := (others => '0'); - signal triggering : std_logic; + signal triggering : std_logic := '0'; signal busy_r : std_logic := '0'; - signal continousread : std_logic; - signal readnow : std_logic; - signal readmanual : std_logic; - signal reseteventcount : std_logic; - signal generatehit : std_logic; - signal generatehits : std_logic; - signal generatetriggeredhits : std_logic; - - signal ngeneratehits : std_logic_vector(15 downto 0); - signal ngeneratehitscounter : unsigned(15 downto 0); - signal generatehitswaitcounter : unsigned(31 downto 0); + signal continousread : std_logic := '0'; + signal readnow : std_logic := '0'; + signal readmanual : std_logic := '0'; + signal reseteventcount : std_logic := '0'; + signal generatehit : std_logic := '0'; + signal generatehits : std_logic := '0'; + signal generatetriggeredhits : std_logic := '0'; + + signal ngeneratehits : std_logic_vector(15 downto 0) := (others => '0'); + signal ngeneratehitscounter : unsigned(15 downto 0) := (others => '0'); + signal generatehitswaitcounter : unsigned(31 downto 0) := (others => '0'); signal gen_hit_col : std_logic_vector(5 downto 0) := (others => '0'); signal gen_hit_row : std_logic_vector(5 downto 0) := (others => '0'); signal gen_hit_time : std_logic_vector(7 downto 0) := (others => '0'); - signal testoutro : std_logic_vector (127 downto 0); + signal testoutro : std_logic_vector (127 downto 0) := (others => '0'); --Control Registers - signal resetgraycounter : std_logic; + signal resetgraycounter : std_logic := '0'; signal roregwritten : std_logic := '0'; signal roregister : std_logic_vector(31 downto 0) := (others => '0'); signal rocontrolbits : std_logic_vector(31 downto 0) := (others => '0'); diff --git a/mupix/sources/TriggerHandler.vhd b/mupix/sources/TriggerHandler.vhd index 710150d..1b2940c 100644 --- a/mupix/sources/TriggerHandler.vhd +++ b/mupix/sources/TriggerHandler.vhd @@ -40,7 +40,8 @@ entity TriggerHandler is FEE_DATA_WRITE_0_IN : in std_logic; -- Trigger FeedBack - TRIGGER_BUSY_MUPIX_DATA_IN : in std_logic; + TRIGGER_BUSY_MUPIX_READ_IN : in std_logic; + TRIGGER_BUSY_FIFO_READ_IN : in std_logic; -- OUT VALID_TRIGGER_OUT : out std_logic; @@ -64,7 +65,9 @@ end entity TriggerHandler; architecture behavioral of TriggerHandler is ---trigger +--trigger + signal reset_trigger_state : std_logic := '0'; + signal reset_trigger_state_edge : std_logic_vector(1 downto 0) := "00"; signal valid_trigger_int : std_logic := '0'; signal timing_trigger_int : std_logic := '0'; signal timing_trigger_edge : std_logic_vector(1 downto 0) := "00"; @@ -73,10 +76,11 @@ architecture behavioral of TriggerHandler is signal fast_clear_int : std_logic := '0'; signal flush_buffer_int : std_logic := '0'; signal trigger_busy_int : std_logic := '0'; - signal mupix_readout_end_int : std_logic_vector(1 downto 0) := "00"; + signal mupix_readout_end_int : std_logic_vector(1 downto 0) := "00"; + signal fifo_readout_end_int : std_logic_vector(1 downto 0) := "00"; --fee signal fee_data_int : std_logic_vector(31 downto 0) := (others => '0'); - signal fee_data_write_int : std_logic; + signal fee_data_write_int : std_logic := '0'; signal fee_data_finished_int : std_logic := '0'; signal fee_trg_release_int : std_logic := '0'; signal fee_trg_statusbit_int : std_logic_vector(31 downto 0) := (others => '0'); @@ -89,11 +93,11 @@ architecture behavioral of TriggerHandler is signal trigger_rate_acc : unsigned(31 downto 0) := (others => '0'); signal trigger_rate_tot : unsigned(31 downto 0) := (others => '0'); signal trigger_rate_time_counter : unsigned(31 downto 0) := (others => '0'); - signal invalid_trigger_counter : unsigned(31 downto 0); + signal invalid_trigger_counter : unsigned(31 downto 0) := (others => '0'); signal valid_trigger_counter : unsigned(31 downto 0) := (others => '0'); signal invalid_trigger_counter_t : unsigned(31 downto 0) := (others => '0'); signal valid_trigger_counter_t : unsigned(31 downto 0) := (others => '0'); - signal trigger_handler_state : std_logic_vector(7 downto 0); + signal trigger_handler_state : std_logic_vector(7 downto 0) := (others => '0'); --trigger types constant trigger_physics_type : std_logic_vector(3 downto 0) := x"1"; @@ -124,8 +128,10 @@ begin Signal_Edge_Detect: process (CLK_IN) is begin -- process Mupix_Readout_End_Detect if rising_edge(CLK_IN) then - mupix_readout_end_int <= mupix_readout_end_int(0) & TRIGGER_BUSY_MUPIX_DATA_IN; + mupix_readout_end_int <= mupix_readout_end_int(0) & TRIGGER_BUSY_MUPIX_READ_IN; + fifo_readout_end_int <= fifo_readout_end_int(0) & TRIGGER_BUSY_FIFO_READ_IN; timing_trigger_edge <= timing_trigger_edge(0) & TIMING_TRIGGER_IN; + reset_trigger_state_edge <= reset_trigger_state_edge(1) & reset_trigger_state; end if; end process Signal_Edge_Detect; @@ -147,7 +153,7 @@ begin trigger_busy_int <= '1'; fast_clear_int <= '0'; fee_trg_release_int <= '0'; - if LVL1_INVALID_TRG_IN = '1'then + if LVL1_INVALID_TRG_IN = '1' or reset_trigger_state_edge = "01" then fast_clear_int <= '1'; fee_trg_release_int <= '1'; trigger_handler_fsm <= idle; @@ -218,8 +224,8 @@ begin when write_data_to_ipu => trigger_handler_state <= x"0A"; - if mupix_readout_end_int = "10" then - fee_data_finished_int <= '1'; + if fifo_readout_end_int = "10" then + --fee_data_finished_int <= '1'; trigger_handler_fsm <= trigger_release; else fee_data_int <= FEE_DATA_0_IN; @@ -287,6 +293,7 @@ begin --0x103: valid triggers --0x104: trigger_handler_state --0x105: reset counters + --0x106: reset trigger state machine slv_bus_handler : process(CLK_IN) begin @@ -300,6 +307,10 @@ begin case SLV_ADDR_IN is when x"0105" => reset_trigger_counters <= SLV_DATA_IN(0); + slv_ack_out <= '1'; + when x"0106" => + reset_trigger_state <= SLV_DATA_IN(0); + slv_ack_out <= '1'; when others => slv_unknown_addr_out <= '1'; end case; @@ -312,13 +323,13 @@ begin slv_data_out <= std_logic_vector(trigger_rate_tot); slv_ack_out <= '1'; when x"0102" => - slv_data_out(10 downto 0) <= std_logic_vector(invalid_trigger_counter); + slv_data_out <= std_logic_vector(invalid_trigger_counter); slv_ack_out <= '1'; when x"0103" => - slv_data_out(10 downto 0) <= std_logic_vector(valid_trigger_counter); + slv_data_out <= std_logic_vector(valid_trigger_counter); slv_ack_out <= '1'; when x"0104" => - slv_data_out(10 downto 0) <= x"000000" & trigger_handler_state; + slv_data_out <= x"000000" & trigger_handler_state; slv_ack_out <= '1'; when others => slv_unknown_addr_out <= '1'; diff --git a/mupix/sources/mupix_components.vhd b/mupix/sources/mupix_components.vhd index 766b270..be8bfc9 100644 --- a/mupix/sources/mupix_components.vhd +++ b/mupix/sources/mupix_components.vhd @@ -80,6 +80,7 @@ package mupix_components is memwren : out std_logic; endofevent : out std_logic; ro_busy : out std_logic; + trigger_ext : in std_logic; SLV_READ_IN : in std_logic; SLV_WRITE_IN : in std_logic; SLV_DATA_OUT : out std_logic_vector(31 downto 0); @@ -236,7 +237,8 @@ package mupix_components is FEE_TRG_STATUSBITS_OUT : out std_logic_vector(31 downto 0); FEE_DATA_0_IN : in std_logic_vector(31 downto 0); FEE_DATA_WRITE_0_IN : in std_logic; - TRIGGER_BUSY_MUPIX_DATA_IN : in std_logic; + TRIGGER_BUSY_MUPIX_READ_IN : in std_logic; + TRIGGER_BUSY_FIFO_READ_IN : in std_logic; VALID_TRIGGER_OUT : out std_logic; TRIGGER_TIMING_OUT : out std_logic; TRIGGER_STATUS_OUT : out std_logic; diff --git a/mupix/trb3_periph.vhd b/mupix/trb3_periph.vhd index 3fd80d2..6fe40a2 100644 --- a/mupix/trb3_periph.vhd +++ b/mupix/trb3_periph.vhd @@ -674,9 +674,9 @@ begin REGIO_DATAREADY_OUT => mu_regio_dataready_out, REGIO_WRITE_ACK_OUT => mu_regio_write_ack_out, REGIO_NO_MORE_DATA_OUT => mu_regio_no_more_data_out, - REGIO_UNKNOWN_ADDR_OUT => mu_regio_unknown_addr_out, + REGIO_UNKNOWN_ADDR_OUT => mu_regio_unknown_addr_out - DEBUG_LINE_OUT => TEST_LINE + --DEBUG_LINE_OUT => TEST_LINE --DEBUG_LINE_OUT => open ); -- 2.43.0