From b717dcc19d29e61cd9b06edb645ccb7d6d8daf4c Mon Sep 17 00:00:00 2001 From: Benedikt Gutsche Date: Wed, 10 Jan 2024 11:44:58 +0100 Subject: [PATCH] removed cores from vldb dir --- vldb/cores/mimosis_inp.fdc | 2 - vldb/cores/mimosis_inp.lpc | 66 ---- vldb/cores/mimosis_inp.sbx | 322 ------------------ vldb/cores/mimosis_inp.vhd | 205 ------------ vldb/cores/pll_200_160/pll_200_160.fdc | 2 - vldb/cores/pll_200_160/pll_200_160.ipx | 8 - vldb/cores/pll_200_160/pll_200_160.lpc | 93 ------ vldb/cores/pll_200_160/pll_200_160.sbx | 430 ------------------------- vldb/cores/pll_200_160/pll_200_160.vhd | 81 ----- vldb/cores/testout.lpc | 66 ---- vldb/cores/testout.sbx | 322 ------------------ vldb/cores/testout.vhd | 219 ------------- 12 files changed, 1816 deletions(-) delete mode 100644 vldb/cores/mimosis_inp.fdc delete mode 100644 vldb/cores/mimosis_inp.lpc delete mode 100644 vldb/cores/mimosis_inp.sbx delete mode 100644 vldb/cores/mimosis_inp.vhd delete mode 100644 vldb/cores/pll_200_160/pll_200_160.fdc delete mode 100644 vldb/cores/pll_200_160/pll_200_160.ipx delete mode 100644 vldb/cores/pll_200_160/pll_200_160.lpc delete mode 100644 vldb/cores/pll_200_160/pll_200_160.sbx delete mode 100644 vldb/cores/pll_200_160/pll_200_160.vhd delete mode 100644 vldb/cores/testout.lpc delete mode 100644 vldb/cores/testout.sbx delete mode 100644 vldb/cores/testout.vhd diff --git a/vldb/cores/mimosis_inp.fdc b/vldb/cores/mimosis_inp.fdc deleted file mode 100644 index 6fbcac9..0000000 --- a/vldb/cores/mimosis_inp.fdc +++ /dev/null @@ -1,2 +0,0 @@ -###==== Start Configuration - diff --git a/vldb/cores/mimosis_inp.lpc b/vldb/cores/mimosis_inp.lpc deleted file mode 100644 index 30827bf..0000000 --- a/vldb/cores/mimosis_inp.lpc +++ /dev/null @@ -1,66 +0,0 @@ -[Device] -Family=ecp5um -PartType=LFE5UM-85F -PartName=LFE5UM-85F-8BG756C -SpeedGrade=8 -Package=CABGA756 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=DDR_GENERIC -CoreRevision=6.0 -ModuleName=mimosis_inp -SourceFormat=vhdl -ParameterFileVersion=1.0 -Date=06/03/2019 -Time=14:45:56 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -mode=Receive -trioddr=0 -io_type=LVDS -width=8 -freq_in=160 -bandwidth=2560 -aligned=Edge-to-Edge -pre-configuration=DISABLED -mode2=Receive -trioddr2=0 -io_type2=LVDS -freq_in2=160 -gear=2:1 -aligned2=Centered -width2=8 -DataLane=By Lane -EnECLK=0 -Interface=GDDRX1_RX.SCLK.Centered -Delay=Dynamic User Defined -DelVal=1 -EnInEdge= -NumEdge=BOTH -EnDynamic=0 -GenPll=0 -Freq= -AFreq= -Reference=0 -IOBUF= -ReceiverSync=0 -EnDynamicAlign= -DynamicAlign= -MIPIFilter=0 -enClkIBuf=0 -ClkIBuf=LVDS - -[Command] -cmd_line= -w -n mimosis_inp -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type iol -mode Receive -io_type LVDS -width 8 -freq_in 160 -gear 2 -del 1 -dynamic_delay -data_lane diff --git a/vldb/cores/mimosis_inp.sbx b/vldb/cores/mimosis_inp.sbx deleted file mode 100644 index e0c4c05..0000000 --- a/vldb/cores/mimosis_inp.sbx +++ /dev/null @@ -1,322 +0,0 @@ - - - - Lattice Semiconductor Corporation - LEGACY - DDR_GENERIC - 6.0 - - - Diamond_Simulation - simulation - - ./mimosis_inp.vhd - vhdlSource - - - - Diamond_Synthesis - synthesis - - ./mimosis_inp.vhd - vhdlSource - - - - - - Configuration - none - ${sbp_path}/generate_core.tcl - CONFIG - - - Generation - none - ${sbp_path}/${instance}/generate_core.tcl - GENERATE - - - - - - - - LFE5UM-85F-8BG756C - synplify - 2019-05-31.19:33:04 - 2019-06-03.14:45:58 - 3.10.3.144 - VHDL - - false - false - false - false - false - false - false - false - false - false - LPM - PRIMARY - PRIMARY - false - false - - - - - - Family - ecp5um - - - OperatingCondition - COM - - - Package - CABGA756 - - - PartName - LFE5UM-85F-8BG756C - - - PartType - LFE5UM-85F - - - SpeedGrade - 8 - - - Status - P - - - - CoreName - DDR_GENERIC - - - CoreRevision - 6.0 - - - CoreStatus - Demo - - - CoreType - LPM - - - Date - 06/03/2019 - - - ModuleName - mimosis_inp - - - ParameterFileVersion - 1.0 - - - SourceFormat - vhdl - - - Time - 14:45:56 - - - VendorName - Lattice Semiconductor Corporation - - - - AFreq - - - - ClkIBuf - LVDS - - - DataLane - By Lane - - - DelVal - 1 - - - Delay - Dynamic User Defined - - - Destination - Synplicity - - - DynamicAlign - - - - EDIF - 1 - - - EnDynamic - 0 - - - EnDynamicAlign - - - - EnECLK - 0 - - - EnInEdge - - - - Expression - BusA(0 to 7) - - - Freq - - - - GenPll - 0 - - - IO - 0 - - - IOBUF - - - - Interface - GDDRX1_RX.SCLK.Centered - - - MIPIFilter - 0 - - - NumEdge - BOTH - - - Order - Big Endian [MSB:LSB] - - - ReceiverSync - 0 - - - Reference - 0 - - - VHDL - 1 - - - Verilog - 0 - - - aligned - Edge-to-Edge - - - aligned2 - Centered - - - bandwidth - 2560 - - - enClkIBuf - 0 - - - freq_in - 160 - - - freq_in2 - 160 - - - gear - 2:1 - - - io_type - LVDS - - - io_type2 - LVDS - - - mode - Receive - - - mode2 - Receive - - - pre-configuration - DISABLED - - - trioddr - 0 - - - trioddr2 - 0 - - - width - 8 - - - width2 - 8 - - - - cmd_line - -w -n mimosis_inp -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type iol -mode Receive -io_type LVDS -width 8 -freq_in 160 -gear 2 -del 1 -dynamic_delay -data_lane - - - - - - - LATTICE - LOCAL - mimosis_inp - 1.0 - - - - diff --git a/vldb/cores/mimosis_inp.vhd b/vldb/cores/mimosis_inp.vhd deleted file mode 100644 index c6ce890..0000000 --- a/vldb/cores/mimosis_inp.vhd +++ /dev/null @@ -1,205 +0,0 @@ --- VHDL netlist generated by SCUBA Diamond (64-bit) 3.10.3.144 --- Module Version: 5.8 ---/d/jspc29/lattice/diamond/3.10_x64/ispfpga/bin/lin64/scuba -w -n mimosis_inp -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type iol -mode Receive -io_type LVDS -width 8 -freq_in 160 -gear 2 -del 1 -dynamic_delay -data_lane -fdc /d/jspc22/trb/lattice/sio/mimosis_inp/mimosis_inp.fdc - --- Mon Jun 3 14:45:58 2019 - -library IEEE; -use IEEE.std_logic_1164.all; -library ecp5um; -use ecp5um.components.all; - -entity mimosis_inp is - port ( - clkin: in std_logic; - reset: in std_logic; - sclk: out std_logic; - data_cflag: out std_logic_vector(7 downto 0); - data_direction: in std_logic_vector(7 downto 0); - data_loadn: in std_logic_vector(7 downto 0); - data_move: in std_logic_vector(7 downto 0); - datain: in std_logic_vector(7 downto 0); - q: out std_logic_vector(15 downto 0)); -end mimosis_inp; - -architecture Structure of mimosis_inp is - - -- internal signal declarations - signal buf_clkin: std_logic; - signal qb7: std_logic; - signal qa7: std_logic; - signal qb6: std_logic; - signal qa6: std_logic; - signal qb5: std_logic; - signal qa5: std_logic; - signal qb4: std_logic; - signal qa4: std_logic; - signal qb3: std_logic; - signal qa3: std_logic; - signal qb2: std_logic; - signal qa2: std_logic; - signal qb1: std_logic; - signal qa1: std_logic; - signal qb0: std_logic; - signal qa0: std_logic; - signal sclk_t: std_logic; - signal dataini_t7: std_logic; - signal dataini_t6: std_logic; - signal dataini_t5: std_logic; - signal dataini_t4: std_logic; - signal dataini_t3: std_logic; - signal dataini_t2: std_logic; - signal dataini_t1: std_logic; - signal dataini_t0: std_logic; - signal buf_dataini7: std_logic; - signal buf_dataini6: std_logic; - signal buf_dataini5: std_logic; - signal buf_dataini4: std_logic; - signal buf_dataini3: std_logic; - signal buf_dataini2: std_logic; - signal buf_dataini1: std_logic; - signal buf_dataini0: std_logic; - - attribute IO_TYPE : string; --- attribute IO_TYPE of Inst3_IB : label is "LVDS"; - attribute IO_TYPE of Inst1_IB7 : label is "LVDS"; - attribute IO_TYPE of Inst1_IB6 : label is "LVDS"; - attribute IO_TYPE of Inst1_IB5 : label is "LVDS"; - attribute IO_TYPE of Inst1_IB4 : label is "LVDS"; - attribute IO_TYPE of Inst1_IB3 : label is "LVDS"; - attribute IO_TYPE of Inst1_IB2 : label is "LVDS"; - attribute IO_TYPE of Inst1_IB1 : label is "LVDS"; - attribute IO_TYPE of Inst1_IB0 : label is "LVDS"; - attribute syn_keep : boolean; - attribute NGD_DRC_MASK : integer; - attribute NGD_DRC_MASK of Structure : architecture is 1; - -begin - -- component instantiation statements --- Inst3_IB: IB --- port map (I=>clkin, O=>buf_clkin); -buf_clkin <= clkin; - - Inst2_IDDRX1F7: IDDRX1F - port map (D=>dataini_t7, SCLK=>sclk_t, RST=>reset, Q0=>qa7, - Q1=>qb7); - - Inst2_IDDRX1F6: IDDRX1F - port map (D=>dataini_t6, SCLK=>sclk_t, RST=>reset, Q0=>qa6, - Q1=>qb6); - - Inst2_IDDRX1F5: IDDRX1F - port map (D=>dataini_t5, SCLK=>sclk_t, RST=>reset, Q0=>qa5, - Q1=>qb5); - - Inst2_IDDRX1F4: IDDRX1F - port map (D=>dataini_t4, SCLK=>sclk_t, RST=>reset, Q0=>qa4, - Q1=>qb4); - - Inst2_IDDRX1F3: IDDRX1F - port map (D=>dataini_t3, SCLK=>sclk_t, RST=>reset, Q0=>qa3, - Q1=>qb3); - - Inst2_IDDRX1F2: IDDRX1F - port map (D=>dataini_t2, SCLK=>sclk_t, RST=>reset, Q0=>qa2, - Q1=>qb2); - - Inst2_IDDRX1F1: IDDRX1F - port map (D=>dataini_t1, SCLK=>sclk_t, RST=>reset, Q0=>qa1, - Q1=>qb1); - - Inst2_IDDRX1F0: IDDRX1F - port map (D=>dataini_t0, SCLK=>sclk_t, RST=>reset, Q0=>qa0, - Q1=>qb0); - - udel_dataini7: DELAYF - generic map (DEL_VALUE=> 0, DEL_MODE=> "USER_DEFINED") - port map (A=>buf_dataini7, LOADN=>data_loadn(7), - MOVE=>data_move(7), DIRECTION=>data_direction(7), - Z=>dataini_t7, CFLAG=>data_cflag(7)); - - udel_dataini6: DELAYF - generic map (DEL_VALUE=> 0, DEL_MODE=> "USER_DEFINED") - port map (A=>buf_dataini6, LOADN=>data_loadn(6), - MOVE=>data_move(6), DIRECTION=>data_direction(6), - Z=>dataini_t6, CFLAG=>data_cflag(6)); - - udel_dataini5: DELAYF - generic map (DEL_VALUE=> 0, DEL_MODE=> "USER_DEFINED") - port map (A=>buf_dataini5, LOADN=>data_loadn(5), - MOVE=>data_move(5), DIRECTION=>data_direction(5), - Z=>dataini_t5, CFLAG=>data_cflag(5)); - - udel_dataini4: DELAYF - generic map (DEL_VALUE=> 0, DEL_MODE=> "USER_DEFINED") - port map (A=>buf_dataini4, LOADN=>data_loadn(4), - MOVE=>data_move(4), DIRECTION=>data_direction(4), - Z=>dataini_t4, CFLAG=>data_cflag(4)); - - udel_dataini3: DELAYF - generic map (DEL_VALUE=> 0, DEL_MODE=> "USER_DEFINED") - port map (A=>buf_dataini3, LOADN=>data_loadn(3), - MOVE=>data_move(3), DIRECTION=>data_direction(3), - Z=>dataini_t3, CFLAG=>data_cflag(3)); - - udel_dataini2: DELAYF - generic map (DEL_VALUE=> 0, DEL_MODE=> "USER_DEFINED") - port map (A=>buf_dataini2, LOADN=>data_loadn(2), - MOVE=>data_move(2), DIRECTION=>data_direction(2), - Z=>dataini_t2, CFLAG=>data_cflag(2)); - - udel_dataini1: DELAYF - generic map (DEL_VALUE=> 0, DEL_MODE=> "USER_DEFINED") - port map (A=>buf_dataini1, LOADN=>data_loadn(1), - MOVE=>data_move(1), DIRECTION=>data_direction(1), - Z=>dataini_t1, CFLAG=>data_cflag(1)); - - udel_dataini0: DELAYF - generic map (DEL_VALUE=> 0, DEL_MODE=> "USER_DEFINED") - port map (A=>buf_dataini0, LOADN=>data_loadn(0), - MOVE=>data_move(0), DIRECTION=>data_direction(0), - Z=>dataini_t0, CFLAG=>data_cflag(0)); - - Inst1_IB7: IB - port map (I=>datain(7), O=>buf_dataini7); - - Inst1_IB6: IB - port map (I=>datain(6), O=>buf_dataini6); - - Inst1_IB5: IB - port map (I=>datain(5), O=>buf_dataini5); - - Inst1_IB4: IB - port map (I=>datain(4), O=>buf_dataini4); - - Inst1_IB3: IB - port map (I=>datain(3), O=>buf_dataini3); - - Inst1_IB2: IB - port map (I=>datain(2), O=>buf_dataini2); - - Inst1_IB1: IB - port map (I=>datain(1), O=>buf_dataini1); - - Inst1_IB0: IB - port map (I=>datain(0), O=>buf_dataini0); - - sclk <= sclk_t; - q(15) <= qb7; - q(14) <= qa7; - q(13) <= qb6; - q(12) <= qa6; - q(11) <= qb5; - q(10) <= qa5; - q(9) <= qb4; - q(8) <= qa4; - q(7) <= qb3; - q(6) <= qa3; - q(5) <= qb2; - q(4) <= qa2; - q(3) <= qb1; - q(2) <= qa1; - q(1) <= qb0; - q(0) <= qa0; - sclk_t <= buf_clkin; -end Structure; diff --git a/vldb/cores/pll_200_160/pll_200_160.fdc b/vldb/cores/pll_200_160/pll_200_160.fdc deleted file mode 100644 index 6fbcac9..0000000 --- a/vldb/cores/pll_200_160/pll_200_160.fdc +++ /dev/null @@ -1,2 +0,0 @@ -###==== Start Configuration - diff --git a/vldb/cores/pll_200_160/pll_200_160.ipx b/vldb/cores/pll_200_160/pll_200_160.ipx deleted file mode 100644 index 43fe758..0000000 --- a/vldb/cores/pll_200_160/pll_200_160.ipx +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/vldb/cores/pll_200_160/pll_200_160.lpc b/vldb/cores/pll_200_160/pll_200_160.lpc deleted file mode 100644 index defee1c..0000000 --- a/vldb/cores/pll_200_160/pll_200_160.lpc +++ /dev/null @@ -1,93 +0,0 @@ -[Device] -Family=ecp5um -PartType=LFE5UM-85F -PartName=LFE5UM-85F-8BG756C -SpeedGrade=8 -Package=CABGA756 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=PLL -CoreRevision=5.8 -ModuleName=pll_200_160 -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=11/12/2021 -Time=15:18:43 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -CLKI_FREQ=200 -CLKI_DIV=5 -ENABLE_HBW=DISABLED -REFERENCE=0 -IOBUF=LVDS -CLKOP_FREQ=160 -CLKOP_TOL=0.0 -CLKOP_DIV=4 -CLKOP_ACTUAL_FREQ=160.000000 -CLKOP_MUXA=DISABLED -CLKOS_Enable=ENABLED -CLKOS_FREQ=320 -CLKOS_TOL=0.0 -CLKOS_DIV=2 -CLKOS_ACTUAL_FREQ=320.000000 -CLKOS_MUXB=DISABLED -CLKOS2_Enable=ENABLED -CLKOS2_FREQ=40.00 -CLKOS2_TOL=0.0 -CLKOS2_DIV=16 -CLKOS2_ACTUAL_FREQ=40.000000 -CLKOS2_MUXC=DISABLED -CLKOS3_Enable=DISABLED -CLKOS3_FREQ=100.00 -CLKOS3_TOL=0.0 -CLKOS3_DIV=1 -CLKOS3_ACTUAL_FREQ= -CLKOS3_MUXD=DISABLED -FEEDBK_PATH=CLKOP -CLKFB_DIV=4 -FRACN_ENABLE=DISABLED -FRACN_DIV= -VCO_RATE=640.000 -PLL_BW=4.655 -CLKOP_DPHASE=0 -CLKOP_APHASE=0.00 -CLKOP_TRIM_POL=Rising -CLKOP_TRIM_DELAY=0 -CLKOS_DPHASE=0 -CLKOS_APHASE=0.00 -CLKOS_TRIM_POL=Rising -CLKOS_TRIM_DELAY=0 -CLKOS2_DPHASE=0 -CLKOS2_APHASE=0.00 -CLKOS2_TRIM_POL=Rising -CLKOS2_TRIM_DELAY=0 -CLKOS3_DPHASE=0 -CLKOS3_APHASE=0.00 -CLKOS3_TRIM_POL=Rising -CLKOS3_TRIM_DELAY=0 -CLKSEL_ENA=DISABLED -DPHASE_SOURCE=STATIC -ENABLE_CLKOP=DISABLED -ENABLE_CLKOS=DISABLED -ENABLE_CLKOS2=DISABLED -ENABLE_CLKOS3=DISABLED -STDBY_ENABLE=DISABLED -PLLRST_ENA=DISABLED -PLL_LOCK_MODE=DISABLED -PLL_LOCK_STK=DISABLED -PLL_USE_SMI=DISABLED - -[Command] -cmd_line= -w -n pll_200_160 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 200 -fclkop 160 -fclkop_tol 0.0 -fclkos 320 -fclkos_tol 0.0 -phases 0 -fclkos2 40.00 -fclkos2_tol 0.0 -phases2 0 -phase_cntl STATIC -fb_mode 1 diff --git a/vldb/cores/pll_200_160/pll_200_160.sbx b/vldb/cores/pll_200_160/pll_200_160.sbx deleted file mode 100644 index 2c7f06c..0000000 --- a/vldb/cores/pll_200_160/pll_200_160.sbx +++ /dev/null @@ -1,430 +0,0 @@ - - - - Lattice Semiconductor Corporation - LEGACY - PLL - 5.8 - - - Diamond_Simulation - simulation - - ./pll_200_160.vhd - vhdlSource - - - - Diamond_Synthesis - synthesis - - ./pll_200_160.vhd - vhdlSource - - - - - - Configuration - none - ${sbp_path}/generate_core.tcl - CONFIG - - - Generation - none - ${sbp_path}/${instance}/generate_core.tcl - GENERATE - - - - - - - - LFE5UM-85F-8BG756C - synplify - 2019-06-04.11:21:55 - 2021-07-02.12:08:04 - 3.11.2.446 - VHDL - - false - false - false - false - false - false - false - false - false - false - LPM - PRIMARY - PRIMARY - false - false - - - - - - Family - ecp5um - - - OperatingCondition - COM - - - Package - CABGA756 - - - PartName - LFE5UM-85F-8BG756C - - - PartType - LFE5UM-85F - - - SpeedGrade - 8 - - - Status - P - - - - CoreName - PLL - - - CoreRevision - 5.8 - - - CoreStatus - Demo - - - CoreType - LPM - - - Date - 07/02/2021 - - - ModuleName - pll_200_160 - - - ParameterFileVersion - 1.0 - - - SourceFormat - vhdl - - - Time - 12:07:59 - - - VendorName - Lattice Semiconductor Corporation - - - - CLKFB_DIV - 4 - - - CLKI_DIV - 5 - - - CLKI_FREQ - 200 - - - CLKOP_ACTUAL_FREQ - 160.000000 - - - CLKOP_APHASE - 0.00 - - - CLKOP_DIV - 4 - - - CLKOP_DPHASE - 0 - - - CLKOP_FREQ - 160 - - - CLKOP_MUXA - DISABLED - - - CLKOP_TOL - 0.0 - - - CLKOP_TRIM_DELAY - 0 - - - CLKOP_TRIM_POL - Rising - - - CLKOS2_ACTUAL_FREQ - - - - CLKOS2_APHASE - 0.00 - - - CLKOS2_DIV - 1 - - - CLKOS2_DPHASE - 0 - - - CLKOS2_Enable - DISABLED - - - CLKOS2_FREQ - 100.00 - - - CLKOS2_MUXC - DISABLED - - - CLKOS2_TOL - 0.0 - - - CLKOS2_TRIM_DELAY - 0 - - - CLKOS2_TRIM_POL - Rising - - - CLKOS3_ACTUAL_FREQ - - - - CLKOS3_APHASE - 0.00 - - - CLKOS3_DIV - 1 - - - CLKOS3_DPHASE - 0 - - - CLKOS3_Enable - DISABLED - - - CLKOS3_FREQ - 100.00 - - - CLKOS3_MUXD - DISABLED - - - CLKOS3_TOL - 0.0 - - - CLKOS3_TRIM_DELAY - 0 - - - CLKOS3_TRIM_POL - Rising - - - CLKOS_ACTUAL_FREQ - 320.000000 - - - CLKOS_APHASE - 0.00 - - - CLKOS_DIV - 2 - - - CLKOS_DPHASE - 0 - - - CLKOS_Enable - ENABLED - - - CLKOS_FREQ - 320 - - - CLKOS_MUXB - DISABLED - - - CLKOS_TOL - 0.0 - - - CLKOS_TRIM_DELAY - 0 - - - CLKOS_TRIM_POL - Rising - - - CLKSEL_ENA - DISABLED - - - DPHASE_SOURCE - STATIC - - - Destination - Synplicity - - - EDIF - 1 - - - ENABLE_CLKOP - DISABLED - - - ENABLE_CLKOS - DISABLED - - - ENABLE_CLKOS2 - DISABLED - - - ENABLE_CLKOS3 - DISABLED - - - ENABLE_HBW - DISABLED - - - Expression - BusA(0 to 7) - - - FEEDBK_PATH - CLKOP - - - FRACN_DIV - - - - FRACN_ENABLE - DISABLED - - - IO - 0 - - - IOBUF - LVDS - - - Order - Big Endian [MSB:LSB] - - - PLLRST_ENA - DISABLED - - - PLL_BW - 4.655 - - - PLL_LOCK_MODE - DISABLED - - - PLL_LOCK_STK - DISABLED - - - PLL_USE_SMI - DISABLED - - - REFERENCE - 0 - - - STDBY_ENABLE - DISABLED - - - VCO_RATE - 640.000 - - - VHDL - 1 - - - Verilog - 0 - - - - cmd_line - -w -n pll_200_160 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 200 -fclkop 160 -fclkop_tol 0.0 -fclkos 320 -fclkos_tol 0.0 -phases 0 -phase_cntl STATIC -fb_mode 1 - - - - - - - LATTICE - LOCAL - pll_200_160 - 1.0 - - - - diff --git a/vldb/cores/pll_200_160/pll_200_160.vhd b/vldb/cores/pll_200_160/pll_200_160.vhd deleted file mode 100644 index 6759858..0000000 --- a/vldb/cores/pll_200_160/pll_200_160.vhd +++ /dev/null @@ -1,81 +0,0 @@ --- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 --- Module Version: 5.7 ---/d/jspc29/lattice/diamond/3.12/ispfpga/bin/lin64/scuba -w -n pll_200_160 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 200 -fclkop 160 -fclkop_tol 0.0 -fclkos 320 -fclkos_tol 0.0 -phases 0 -fclkos2 40.00 -fclkos2_tol 0.0 -phases2 0 -phase_cntl STATIC -fb_mode 1 - --- Fri Nov 12 15:18:43 2021 - -library IEEE; -use IEEE.std_logic_1164.all; -library ecp5um; -use ecp5um.components.all; - -entity pll_200_160 is - port ( - CLKI: in std_logic; - CLKOP: out std_logic; - CLKOS: out std_logic; - CLKOS2: out std_logic); -end pll_200_160; - -architecture Structure of pll_200_160 is - - -- internal signal declarations - signal REFCLK: std_logic; - signal LOCK: std_logic; - signal CLKOS2_t: std_logic; - signal CLKOS_t: std_logic; - signal CLKOP_t: std_logic; - signal scuba_vhi: std_logic; - signal scuba_vlo: std_logic; - - attribute FREQUENCY_PIN_CLKOS2 : string; - attribute FREQUENCY_PIN_CLKOS : string; - attribute FREQUENCY_PIN_CLKOP : string; - attribute FREQUENCY_PIN_CLKI : string; - attribute ICP_CURRENT : string; - attribute LPF_RESISTOR : string; - attribute FREQUENCY_PIN_CLKOS2 of PLLInst_0 : label is "40.000000"; - attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "320.000000"; - attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "160.000000"; - attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000"; - attribute ICP_CURRENT of PLLInst_0 : label is "12"; - attribute LPF_RESISTOR of PLLInst_0 : label is "8"; - attribute syn_keep : boolean; - attribute NGD_DRC_MASK : integer; - attribute NGD_DRC_MASK of Structure : architecture is 1; - -begin - -- component instantiation statements - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - PLLInst_0: EHXPLLL - generic map (PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED", - STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED", - CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 0, CLKOS2_FPHASE=> 0, - CLKOS2_CPHASE=> 15, CLKOS_FPHASE=> 0, CLKOS_CPHASE=> 1, - CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 3, PLL_LOCK_MODE=> 0, - CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "FALLING", - CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "FALLING", - OUTDIVIDER_MUXD=> "DIVD", CLKOS3_ENABLE=> "DISABLED", - OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "ENABLED", - OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "ENABLED", - OUTDIVIDER_MUXA=> "DIVA", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 1, - CLKOS2_DIV=> 16, CLKOS_DIV=> 2, CLKOP_DIV=> 4, CLKFB_DIV=> 4, - CLKI_DIV=> 5, FEEDBK_PATH=> "CLKOP") - port map (CLKI=>CLKI, CLKFB=>CLKOP_t, PHASESEL1=>scuba_vlo, - PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo, - PHASESTEP=>scuba_vlo, PHASELOADREG=>scuba_vlo, - STDBY=>scuba_vlo, PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo, - ENCLKOP=>scuba_vlo, ENCLKOS=>scuba_vlo, ENCLKOS2=>scuba_vlo, - ENCLKOS3=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t, - CLKOS2=>CLKOS2_t, CLKOS3=>open, LOCK=>LOCK, INTLOCK=>open, - REFCLK=>REFCLK, CLKINTFB=>open); - - CLKOS2 <= CLKOS2_t; - CLKOS <= CLKOS_t; - CLKOP <= CLKOP_t; -end Structure; diff --git a/vldb/cores/testout.lpc b/vldb/cores/testout.lpc deleted file mode 100644 index c705e50..0000000 --- a/vldb/cores/testout.lpc +++ /dev/null @@ -1,66 +0,0 @@ -[Device] -Family=ecp5um -PartType=LFE5UM-85F -PartName=LFE5UM-85F-8BG756C -SpeedGrade=8 -Package=CABGA756 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=DDR_GENERIC -CoreRevision=6.0 -ModuleName=testout -SourceFormat=vhdl -ParameterFileVersion=1.0 -Date=06/05/2019 -Time=14:55:39 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -mode=Transmit -trioddr=0 -io_type=LVDS -width=8 -freq_in=160 -bandwidth=2560 -aligned=Edge-to-Edge -pre-configuration=DISABLED -mode2=Transmit -trioddr2=0 -io_type2=LVDS -freq_in2=160 -gear=2:1 -aligned2=Edge-to-Edge -width2=8 -DataLane=By Lane -EnECLK=0 -Interface=GDDRX1_TX.SCLK.Aligned -Delay=Dynamic User Defined -DelVal=1 -EnInEdge= -NumEdge=BOTH -EnDynamic=0 -GenPll=0 -Freq= -AFreq= -Reference=0 -IOBUF= -ReceiverSync=0 -EnDynamicAlign= -DynamicAlign= -MIPIFilter=0 -enClkIBuf=0 -ClkIBuf=LVDS - -[Command] -cmd_line= -w -n testout -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type iol -mode Transmit -io_type LVDS -width 8 -freq_in 160 -gear 2 -aligned -del 1 -dynamic_delay -data_lane diff --git a/vldb/cores/testout.sbx b/vldb/cores/testout.sbx deleted file mode 100644 index 7b87c2e..0000000 --- a/vldb/cores/testout.sbx +++ /dev/null @@ -1,322 +0,0 @@ - - - - Lattice Semiconductor Corporation - LEGACY - DDR_GENERIC - 6.0 - - - Diamond_Simulation - simulation - - ./testout.vhd - vhdlSource - - - - Diamond_Synthesis - synthesis - - ./testout.vhd - vhdlSource - - - - - - Configuration - none - ${sbp_path}/generate_core.tcl - CONFIG - - - Generation - none - ${sbp_path}/${instance}/generate_core.tcl - GENERATE - - - - - - - - LFE5UM-85F-8BG756C - synplify - 2019-06-05.14:55:41 - 2019-06-05.14:55:41 - 3.10.3.144 - VHDL - - false - false - false - false - false - false - false - false - false - false - LPM - PRIMARY - PRIMARY - false - false - - - - - - Family - ecp5um - - - OperatingCondition - COM - - - Package - CABGA756 - - - PartName - LFE5UM-85F-8BG756C - - - PartType - LFE5UM-85F - - - SpeedGrade - 8 - - - Status - P - - - - CoreName - DDR_GENERIC - - - CoreRevision - 6.0 - - - CoreStatus - Demo - - - CoreType - LPM - - - Date - 06/05/2019 - - - ModuleName - testout - - - ParameterFileVersion - 1.0 - - - SourceFormat - vhdl - - - Time - 14:55:39 - - - VendorName - Lattice Semiconductor Corporation - - - - AFreq - - - - ClkIBuf - LVDS - - - DataLane - By Lane - - - DelVal - 1 - - - Delay - Dynamic User Defined - - - Destination - Synplicity - - - DynamicAlign - - - - EDIF - 1 - - - EnDynamic - 0 - - - EnDynamicAlign - - - - EnECLK - 0 - - - EnInEdge - - - - Expression - BusA(0 to 7) - - - Freq - - - - GenPll - 0 - - - IO - 0 - - - IOBUF - - - - Interface - GDDRX1_TX.SCLK.Aligned - - - MIPIFilter - 0 - - - NumEdge - BOTH - - - Order - Big Endian [MSB:LSB] - - - ReceiverSync - 0 - - - Reference - 0 - - - VHDL - 1 - - - Verilog - 0 - - - aligned - Edge-to-Edge - - - aligned2 - Edge-to-Edge - - - bandwidth - 2560 - - - enClkIBuf - 0 - - - freq_in - 160 - - - freq_in2 - 160 - - - gear - 2:1 - - - io_type - LVDS - - - io_type2 - LVDS - - - mode - Transmit - - - mode2 - Transmit - - - pre-configuration - DISABLED - - - trioddr - 0 - - - trioddr2 - 0 - - - width - 8 - - - width2 - 8 - - - - cmd_line - -w -n testout -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type iol -mode Transmit -io_type LVDS -width 8 -freq_in 160 -gear 2 -aligned -del 1 -dynamic_delay -data_lane - - - - - - - LATTICE - LOCAL - testout - 1.0 - - - - diff --git a/vldb/cores/testout.vhd b/vldb/cores/testout.vhd deleted file mode 100644 index 7c1451c..0000000 --- a/vldb/cores/testout.vhd +++ /dev/null @@ -1,219 +0,0 @@ --- VHDL netlist generated by SCUBA Diamond (64-bit) 3.10.3.144 --- Module Version: 5.8 ---/d/jspc29/lattice/diamond/3.10_x64/ispfpga/bin/lin64/scuba -w -n testout -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type iol -mode Transmit -io_type LVDS -width 8 -freq_in 160 -gear 2 -aligned -del 1 -dynamic_delay -data_lane -fdc /d/jspc22/trb/lattice/sio/testout/testout.fdc - --- Wed Jun 5 14:55:41 2019 - -library IEEE; -use IEEE.std_logic_1164.all; -library ecp5um; -use ecp5um.components.all; - -entity testout is - port ( - clkout: out std_logic; - refclk: in std_logic; - reset: in std_logic; - data: in std_logic_vector(15 downto 0); - data_cflag: out std_logic_vector(7 downto 0); - data_direction: in std_logic_vector(7 downto 0); - data_loadn: in std_logic_vector(7 downto 0); - data_move: in std_logic_vector(7 downto 0); - dout: out std_logic_vector(7 downto 0)); -end testout; - -architecture Structure of testout is - - -- internal signal declarations - signal db7: std_logic; - signal da7: std_logic; - signal db6: std_logic; - signal da6: std_logic; - signal db5: std_logic; - signal da5: std_logic; - signal db4: std_logic; - signal da4: std_logic; - signal db3: std_logic; - signal da3: std_logic; - signal db2: std_logic; - signal da2: std_logic; - signal db1: std_logic; - signal da1: std_logic; - signal db0: std_logic; - signal da0: std_logic; - signal scuba_vlo: std_logic; - signal scuba_vhi: std_logic; - signal sclk_t: std_logic; - signal clkos: std_logic; - signal clkop: std_logic; - signal buf_clkout: std_logic; - signal douto_t7: std_logic; - signal buf_douto7: std_logic; - signal douto_t6: std_logic; - signal buf_douto6: std_logic; - signal douto_t5: std_logic; - signal buf_douto5: std_logic; - signal douto_t4: std_logic; - signal buf_douto4: std_logic; - signal douto_t3: std_logic; - signal buf_douto3: std_logic; - signal douto_t2: std_logic; - signal buf_douto2: std_logic; - signal douto_t1: std_logic; - signal buf_douto1: std_logic; - signal douto_t0: std_logic; - signal buf_douto0: std_logic; - - attribute IO_TYPE : string; - attribute IO_TYPE of Inst2_OB : label is "LVDS"; - attribute IO_TYPE of Inst1_OB7 : label is "LVDS"; - attribute IO_TYPE of Inst1_OB6 : label is "LVDS"; - attribute IO_TYPE of Inst1_OB5 : label is "LVDS"; - attribute IO_TYPE of Inst1_OB4 : label is "LVDS"; - attribute IO_TYPE of Inst1_OB3 : label is "LVDS"; - attribute IO_TYPE of Inst1_OB2 : label is "LVDS"; - attribute IO_TYPE of Inst1_OB1 : label is "LVDS"; - attribute IO_TYPE of Inst1_OB0 : label is "LVDS"; - attribute syn_keep : boolean; - attribute NGD_DRC_MASK : integer; - attribute NGD_DRC_MASK of Structure : architecture is 1; - -begin - -- component instantiation statements - Inst4_ODDRX1F7: ODDRX1F - port map (SCLK=>sclk_t, RST=>reset, D0=>da7, D1=>db7, - Q=>buf_douto7); - - Inst4_ODDRX1F6: ODDRX1F - port map (SCLK=>sclk_t, RST=>reset, D0=>da6, D1=>db6, - Q=>buf_douto6); - - Inst4_ODDRX1F5: ODDRX1F - port map (SCLK=>sclk_t, RST=>reset, D0=>da5, D1=>db5, - Q=>buf_douto5); - - Inst4_ODDRX1F4: ODDRX1F - port map (SCLK=>sclk_t, RST=>reset, D0=>da4, D1=>db4, - Q=>buf_douto4); - - Inst4_ODDRX1F3: ODDRX1F - port map (SCLK=>sclk_t, RST=>reset, D0=>da3, D1=>db3, - Q=>buf_douto3); - - Inst4_ODDRX1F2: ODDRX1F - port map (SCLK=>sclk_t, RST=>reset, D0=>da2, D1=>db2, - Q=>buf_douto2); - - Inst4_ODDRX1F1: ODDRX1F - port map (SCLK=>sclk_t, RST=>reset, D0=>da1, D1=>db1, - Q=>buf_douto1); - - Inst4_ODDRX1F0: ODDRX1F - port map (SCLK=>sclk_t, RST=>reset, D0=>da0, D1=>db0, - Q=>buf_douto0); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - Inst3_ODDRX1F: ODDRX1F - port map (SCLK=>clkos, RST=>reset, D0=>scuba_vhi, D1=>scuba_vlo, - Q=>buf_clkout); - - Inst2_OB: OB - port map (I=>buf_clkout, O=>clkout); - - Inst1_OB7: OB - port map (I=>douto_t7, O=>dout(7)); - - Inst1_OB6: OB - port map (I=>douto_t6, O=>dout(6)); - - Inst1_OB5: OB - port map (I=>douto_t5, O=>dout(5)); - - Inst1_OB4: OB - port map (I=>douto_t4, O=>dout(4)); - - Inst1_OB3: OB - port map (I=>douto_t3, O=>dout(3)); - - Inst1_OB2: OB - port map (I=>douto_t2, O=>dout(2)); - - Inst1_OB1: OB - port map (I=>douto_t1, O=>dout(1)); - - Inst1_OB0: OB - port map (I=>douto_t0, O=>dout(0)); - - udel_douto7: DELAYF - generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED") - port map (A=>buf_douto7, LOADN=>data_loadn(7), - MOVE=>data_move(7), DIRECTION=>data_direction(7), - Z=>douto_t7, CFLAG=>data_cflag(7)); - - udel_douto6: DELAYF - generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED") - port map (A=>buf_douto6, LOADN=>data_loadn(6), - MOVE=>data_move(6), DIRECTION=>data_direction(6), - Z=>douto_t6, CFLAG=>data_cflag(6)); - - udel_douto5: DELAYF - generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED") - port map (A=>buf_douto5, LOADN=>data_loadn(5), - MOVE=>data_move(5), DIRECTION=>data_direction(5), - Z=>douto_t5, CFLAG=>data_cflag(5)); - - udel_douto4: DELAYF - generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED") - port map (A=>buf_douto4, LOADN=>data_loadn(4), - MOVE=>data_move(4), DIRECTION=>data_direction(4), - Z=>douto_t4, CFLAG=>data_cflag(4)); - - udel_douto3: DELAYF - generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED") - port map (A=>buf_douto3, LOADN=>data_loadn(3), - MOVE=>data_move(3), DIRECTION=>data_direction(3), - Z=>douto_t3, CFLAG=>data_cflag(3)); - - udel_douto2: DELAYF - generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED") - port map (A=>buf_douto2, LOADN=>data_loadn(2), - MOVE=>data_move(2), DIRECTION=>data_direction(2), - Z=>douto_t2, CFLAG=>data_cflag(2)); - - udel_douto1: DELAYF - generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED") - port map (A=>buf_douto1, LOADN=>data_loadn(1), - MOVE=>data_move(1), DIRECTION=>data_direction(1), - Z=>douto_t1, CFLAG=>data_cflag(1)); - - udel_douto0: DELAYF - generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED") - port map (A=>buf_douto0, LOADN=>data_loadn(0), - MOVE=>data_move(0), DIRECTION=>data_direction(0), - Z=>douto_t0, CFLAG=>data_cflag(0)); - - db7 <= data(15); - da7 <= data(14); - db6 <= data(13); - da6 <= data(12); - db5 <= data(11); - da5 <= data(10); - db4 <= data(9); - da4 <= data(8); - db3 <= data(7); - da3 <= data(6); - db2 <= data(5); - da2 <= data(4); - db1 <= data(3); - da1 <= data(2); - db0 <= data(1); - da0 <= data(0); - sclk_t <= clkop; - clkos <= refclk; - clkop <= refclk; -end Structure; -- 2.43.0