From b772ce84007e1f6147c7f4d20f707fa7e7ba69eb Mon Sep 17 00:00:00 2001 From: Andreas Neiser Date: Tue, 14 Apr 2015 17:46:16 +0200 Subject: [PATCH] Implement DebugMode --- ADC/source/adc_package.vhd | 7 +++-- ADC/source/adc_processor_cfd.vhd | 2 +- ADC/source/adc_processor_cfd_ch.vhd | 49 +++++++++++++++++++++++++++-- 3 files changed, 52 insertions(+), 6 deletions(-) diff --git a/ADC/source/adc_package.vhd b/ADC/source/adc_package.vhd index f79c499..f646feb 100644 --- a/ADC/source/adc_package.vhd +++ b/ADC/source/adc_package.vhd @@ -43,7 +43,7 @@ package adc_package is end record; type cfg_cfd_t is record - ProcessingMode : integer range 0 to 3; -- 0 CFD events, 1 raw, 2 subtracted, 3 cfd + DebugMode : integer range 0 to 3; -- 0 CFD events, debug: 1 raw, 2 subtracted, 3 cfd InputThreshold : unsigned(9 downto 0); PolarityInvert : std_logic; BaselineAverage : unsigned(3 downto 0); @@ -58,9 +58,11 @@ package adc_package is CheckWordEnable : std_logic; TriggerEnable : std_logic_vector(47 downto 0); ChannelDisable : std_logic_vector(47 downto 0); + DebugSamples : unsigned(7 downto 0); -- for ProcessingMode>0 end record; constant cfg_cfd_t_INIT : cfg_cfd_t := ( + DebugMode => 0 InputThreshold => (others => '0'), PolarityInvert => '0', BaselineAverage => (others => '0'), @@ -74,7 +76,8 @@ package adc_package is CheckWord2 => (others => '0'), CheckWordEnable => '0', TriggerEnable => (others => '0'), - ChannelDisable => (others => '0') + ChannelDisable => (others => '0'), + DebugSamples => (others => '0') ); type debug_cfd_t is record diff --git a/ADC/source/adc_processor_cfd.vhd b/ADC/source/adc_processor_cfd.vhd index 76a9eb4..bc87cc2 100644 --- a/ADC/source/adc_processor_cfd.vhd +++ b/ADC/source/adc_processor_cfd.vhd @@ -142,7 +142,7 @@ begin READOUT_TX.statusbits <= (23 => '1', others => '0'); --event not found state <= RELEASE_DIRECT; elsif READOUT_RX.valid_timing_trg = '1' then - if CONF_sys.ProcessingMode = 0 then + if CONF_sys.DebugMode = 0 then counter := to_integer(CONF_sys.TriggerDelay); state <= TRIG_DLY; else diff --git a/ADC/source/adc_processor_cfd_ch.vhd b/ADC/source/adc_processor_cfd_ch.vhd index 5af94eb..f05bc4b 100644 --- a/ADC/source/adc_processor_cfd_ch.vhd +++ b/ADC/source/adc_processor_cfd_ch.vhd @@ -92,10 +92,12 @@ architecture arch of adc_processor_cfd_ch is signal integral_sum : signed(RESOLUTION_CFD - 1 downto 0) := (others => '0'); signal epoch_counter, epoch_counter_save : unsigned(23 downto 0) := (others => '0'); - type state_t is (IDLE, INTEGRATE, WRITE1, WRITE2, WRITE3, WRITE4, FINISH, LOCKED); + type state_t is (IDLE, INTEGRATE, WRITE1, WRITE2, WRITE3, WRITE4, FINISH, LOCKED, DEBUG_DUMP); signal state : state_t := IDLE; signal ram_counter : unsigned(8 downto 0) := (others => '0'); + + signal debug_mux : std_logic_vector(15 downto 0); begin -- input ADC data interpreted as unsigned input <= unsigned(ADC_DATA); @@ -226,6 +228,8 @@ begin proc_zeroX_gate : process is variable zeroX : std_logic := '0'; variable integral_counter : integer range 0 to 2 ** CONF.IntegrateWindow'length - 1; + variable debug_counter : integer range 0 to 2 ** CONF.DebugSamples'length - 1; + begin wait until rising_edge(CLK); @@ -244,17 +248,41 @@ begin case state is when IDLE => - if zeroX = '1' then + if CONF.DebugMode = 0 and zeroX = '1' then state <= INTEGRATE; integral_counter := to_integer(CONF.IntegrateWindow); integral_sum <= resize(delay_integral_out, RESOLUTION_CFD); cfd_prev_save <= cfd_prev; cfd_save <= cfd.value; epoch_counter_save <= epoch_counter; - elsif RAM_BSY_IN = '1' then + elsif CONF.DebugMode = 0 and RAM_BSY_IN = '1' then state <= LOCKED; + elsif CONF.DebugMode /= 0 and RAM_BSY_IN = '1' then + -- at least one word is always dumped into the RAM + -- don't move the ram pointer yet, it's already at next position + RAM_DATA(31 downto 24) <= x"cd"; + RAM_DATA(23 downto 20) <= std_logic_vector(to_unsigned(DEVICE, 4)); + RAM_DATA(19 downto 16) <= std_logic_vector(to_unsigned(CHANNEL, 4)); + RAM_DATA(15 downto 0) <= debug_mux; + debug_counter := to_integer(CONF.DebugSamples); + state <= DEBUG_DUMP; end if; + when DEBUG_DUMP => + -- always move the ram pointer + ram_counter <= ram_counter + 1; + if debug_counter = 0 then + -- indicate we're done + state <= LOCKED; + else + debug_counter := debug_counter - 1; + RAM_DATA(31 downto 24) <= x"cd"; + RAM_DATA(23 downto 20) <= std_logic_vector(to_unsigned(DEVICE, 4)); + RAM_DATA(19 downto 16) <= std_logic_vector(to_unsigned(CHANNEL, 4)); + RAM_DATA(15 downto 0) <= debug_mux; + end if; + + when INTEGRATE => if integral_counter = 0 then state <= WRITE1; @@ -307,6 +335,21 @@ begin end process proc_zeroX_gate; + -- debug multiplexer of some signals + proc_mux_debug : process is + begin + wait until rising_edge(CLK); + case CONF.DebugMode is + when 0 => + debug_mux <= (others => '0'); + when 1 => + debug_mux <= std_logic_vector(resize(input,debug_mux'length)); + when 2 => + debug_mux <= std_logic_vector(resize(subtracted.value,debug_mux'length)); + when 3 => + debug_mux <= std_logic_vector(resize(cfd.value,debug_mux'length)); + end case; + end process proc_mux_debug; -- 2.43.0