From b8108d3e18907e9ee57bcb7f5f5a28fb28e40aac Mon Sep 17 00:00:00 2001
From: Hadaq in Frankfurt <hadaq@frankfurt>
Date: Tue, 19 Mar 2013 19:30:03 +0100
Subject: [PATCH] added information about addresses, JM

---
 trb3/Trb3GeneralRemarks.tex | 22 ++++++++++++++++++++++
 trb3/main.tex               | 10 +++++-----
 2 files changed, 27 insertions(+), 5 deletions(-)

diff --git a/trb3/Trb3GeneralRemarks.tex b/trb3/Trb3GeneralRemarks.tex
index 6aa4f07..e79b9db 100644
--- a/trb3/Trb3GeneralRemarks.tex
+++ b/trb3/Trb3GeneralRemarks.tex
@@ -82,6 +82,19 @@ The lower 16 Bit are used to identify the contents of the design and the AddOn b
 Software versions can be stored in the generic \signal{Regio\_Compile\_Version} (register 0x41).
 
 \subsection{Network Addresses}
+The network addresses in a TRB3 set-up (not in HADES) follow a simple scheme:
+
+All network addresses are of the form ABBC, where:
+\begin{itemize*}
+\item C is the FPGA number. 0 for the central FPGA, 1-4 for the peripheral FPGAs.
+\item A denotes the function of the FPGA:\\C: CTS, 8: Hub, 0: TDC
+\item BB is a number identifying the TRB in the full system. BB is equal on   
+all 5 FPGA of one board.
+\end{itemize*}
+
+The FPGA with the CTS has address C000 (in already existing systems also 8000). For data unpacking schemes see also \ref{Data_Unpacking}.
+
+
 All boards of a given type are accessible by a broadcast address at the same time. This is set by \signal{Broadcast\_Special\_Addr} in the TrbNet endpoint:
 \begin{itemize*}
  \item 0x40 for the central FPGA
@@ -135,4 +148,13 @@ The pin-out of the JTAG connector (1x8 pin-header near the power supply).
 Pin 1 is next to the 2x6 pin-header. Note that TDO and TDI are switched compared to the layout on all other boards. If you experience strange behavior of the programming procedure and think you might have destroyed the cable: It's most likely a software issue - reboot your PC!
 
 
+\subsection{Data Unpacker}
+\label{Data_Unpacking}
+The data stream contains SubEvent-IDs and SubSubEvent-IDs to identify the sender of each block of data. While SubSubEvent-IDs are equal to the network address of the corresponding board by design, the SubEvent-IDs can be choosen freely, but are defined to be equal to the network address of the board sending the SubEvent via Gigabit Ethernet. The first digit of each SubSubEvent-ID is sufficient to determine how the following data  has to be handled:
+\begin{description*}
+\item[0] Unpack as TDC data
+\item[8] Skip this SubSubEvent-Header. Note: Only the header, the next word should be another valid SubSubEvent-Header.
+\item[C] Unpack as CTS data
+\item[5] The only SubSubEvent-ID starting with 5 is 5555 at the end of each SubEvent, marking the beginning of the status information word for this SubEvent.
+\end{description*}
 
diff --git a/trb3/main.tex b/trb3/main.tex
index 9a49101..d427c6e 100644
--- a/trb3/main.tex
+++ b/trb3/main.tex
@@ -79,7 +79,7 @@
 \author{Grzegorz Korcyl, Ludwig Maier, Jan Michel, Marek Palka, \\Manuel Penschuck, Pawel Strzempek, Michael Traxler, Cahit Ugur}
 
 
-\newcommand{\filename}[1]{\textit{#1}}
+% \newcommand{\filename}[1]{\textit{#1}}
 \newcommand{\signal}[1]{\textsc{#1}}
 \newcommand{\genericname}[1]{\textsc{#1}}
 \newcommand{\constname}[1]{\textsc{#1}}
@@ -125,7 +125,10 @@
 \part{Resources}
   \section{Code Repository}
     \input{CodeRepository}
-
+    \clearpage
+\part{General Information}    
+  \section{General Remarks}
+    \input{Trb3GeneralRemarks}  
 \cleardoublepage
 \part{Hardware}
   \input{Trb3Hardware}
@@ -155,9 +158,6 @@
   \cleardoublepage
 
 \part{Design Components}
-  \section{General Remarks}
-    \input{Trb3GeneralRemarks}  
-  \clearpage
   \section{TDC}
     \subsection{Building Blocks}
       \input{TdcBuildingBlocks}
-- 
2.43.0