From b826278ed2fc845e962723dd8c9a6d473c78dcbc Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Thu, 24 Oct 2019 13:37:39 +0200 Subject: [PATCH] TRB3sc CTS updates --- code/trb3sc_tools.vhd | 2 +- cts/config.vhd | 32 +++---- cts/trb3sc_cts.lpf | 30 ++++++- cts/trb3sc_cts.vhd | 193 +++++++++++++++++++++++++++--------------- 4 files changed, 169 insertions(+), 88 deletions(-) diff --git a/code/trb3sc_tools.vhd b/code/trb3sc_tools.vhd index c1cce15..4c65c92 100644 --- a/code/trb3sc_tools.vhd +++ b/code/trb3sc_tools.vhd @@ -91,7 +91,7 @@ begin PORT_NUMBER => 9, PORT_ADDRESSES => (0 => x"0000", 1 => x"0400", 2 => x"0480", 3 => x"0500", 4 => x"0600", 5 => x"0180", 6 => x"0f00", 7 => x"0f80", 8 => x"0580", others => x"0000"), - PORT_ADDR_MASK => (0 => 9, 1 => 5, 2 => 5, 3 => 1, 4 => 2, + PORT_ADDR_MASK => (0 => 9, 1 => 5, 2 => 5, 3 => 2, 4 => 2, 5 => 4, 6 => 7, 7 => 7, 8 => 0, others => 0), PORT_MASK_ENABLE => 1 ) diff --git a/cts/config.vhd b/cts/config.vhd index 5aafa19..8e1d24a 100644 --- a/cts/config.vhd +++ b/cts/config.vhd @@ -12,8 +12,8 @@ package config is ------------------------------------------------------------------------------ --design options: backplane or front SFP, with or without GBE - constant USE_BACKPLANE : integer := c_NO; - constant USE_ADDON : integer := c_YES; + constant USE_BACKPLANE : integer := c_NO; --c_YES doesn't work + constant USE_ADDON : integer := c_NO; constant INCLUDE_GBE : integer := c_YES; --c_NO doesn't work --Runs with 120 MHz instead of 100 MHz @@ -36,7 +36,7 @@ package config is constant INCLUDE_DEBUG_INTERFACE: integer := c_YES; --input monitor and trigger generation logic - constant INCLUDE_TDC : integer := c_NO; + constant INCLUDE_TDC : integer := c_YES; constant INCLUDE_TRIGGER_LOGIC : integer := c_YES; constant INCLUDE_STATISTICS : integer := c_YES; constant TRIG_GEN_INPUT_NUM : integer := 40; @@ -49,7 +49,7 @@ package config is -- 0: KEL on board -- 1: Canadian constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement - constant NUM_TDC_CHANNELS : integer range 1 to 65 := 12; -- number of tdc channels per module + constant NUM_TDC_CHANNELS : integer range 1 to 65 := 33; -- number of tdc channels per module constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 4; --the nearest power of two, for convenience reasons constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3 -- 0: single edge only, @@ -109,31 +109,31 @@ package config is type hw_info_t is array(0 to 3) of std_logic_vector(31 downto 0); type intlist_t is array(0 to 7) of integer; -- 0 opt. link opt. link --- 1-8 SFP 1-4 --- 1(9) CTS read-out internal 0 1 - X X O --downlink only --- 2(10) CTS TRG Sctrl GbE 2 3 4 X X X --uplink only +-- 0-7 SFP 1-8 +-- 1(8) CTS read-out internal 0 1 - X X O --downlink only +-- 2(9) CTS TRG Sctrl GbE 2 3 4 X X X --uplink only --Order: -- no backplane, no AddOn, 1x SFP, 1x GBE - -- no backplane, 4x AddOn, 1x SFP, 1x GBE --- -- -- -- no backplane, 8x AddOn, 1x SFP, 1x GBE - -- backplane, 9x backplane, 1x GBE - constant SFP_NUM_ARR : hub_mii_t := (1,5,0,0); - constant INTERFACE_NUM_ARR : hub_mii_t := (1,5,9,10); +-- -- -- -- no backplane, 4x AddOn, 1x SFP, 1x GBE + -- no backplane, 8x AddOn, 0x SFP, 1x GBE +-- -- -- -- backplane, 9x backplane, 1x GBE + constant SFP_NUM_ARR : hub_mii_t := (1,0,8,0); + constant INTERFACE_NUM_ARR : hub_mii_t := (1,5,8,10); -- 0 1 2 3 4 5 6 7 8 9 a b c d e f constant IS_UPLINK_ARR : hub_cfg_t := ((0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0), (0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0), -- (0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0), - (0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0), + (0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0), (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0)); constant IS_DOWNLINK_ARR : hub_cfg_t := ((1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), (1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0), -- (1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0), - (1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0), + (1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0), (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0)); constant IS_UPLINK_ONLY_ARR : hub_cfg_t := ((0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0), (0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0), - (0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0), + (0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0), -- (0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0), (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0)); @@ -169,7 +169,7 @@ package body config is constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_120_MHZ); constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_120_MHZ); - constant CFG_MODE : integer := USE_ADDON;--*2 + USE_BACKPLANE; + constant CFG_MODE : integer := USE_ADDON*2;--*2 + USE_BACKPLANE; constant INTERFACE_NUM : integer := INTERFACE_NUM_ARR(CFG_MODE); constant IS_UPLINK : hub_ct := IS_UPLINK_ARR(CFG_MODE); diff --git a/cts/trb3sc_cts.lpf b/cts/trb3sc_cts.lpf index 4ec992e..1bb9d55 100644 --- a/cts/trb3sc_cts.lpf +++ b/cts/trb3sc_cts.lpf @@ -5,21 +5,32 @@ # LOCATE COMP "gen_PCSD.THE_MEDIA_4_PCSD/THE_SERDES/PCSD_INST" SITE "PCSD" ; LOCATE COMP "gen_PCSB.THE_MEDIA_PCSB/gen_pcs3.THE_SERDES/PCSD_INST" SITE "PCSB"; +LOCATE COMP "gen_PCSB_ADDON.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST" SITE "PCSB"; LOCATE COMP "gen_PCSC.THE_MEDIA_PCSC/THE_SERDES/PCSD_INST" SITE "PCSC"; LOCATE COMP "gen_GBE.GBE/physical_impl_gen.physical/impl_gen.gbe_serdes/PCSD_INST" SITE "PCSD"; BLOCK PATH FROM CELL THE_TDC/calibration_o*; BLOCK PATH FROM CELL THE_CTS/TIME_REFERENCE_OUT TO CELL THE_TDC/ReferenceChannel/Channel200/SimAdderNo.FC/FF*; +BLOCK PATH FROM CELL THE_CTS/TIME_REFERENCE_OUT TO CELL THE_TDC/TheTriggerHandler/trg_in_r[0]; -REGION "MEDIA_DOWN1" "R102C40D" 13 100; +# REGION "MEDIA_GBE" "R89C2" 25 53; +REGION "MEDIA_C" "R102C128" 13 40; +REGION "MEDIA_B" "R102C55" 13 40; +REGION "MEDIA_DOWN1" "R102C20D" 13 120; #LOCATE UGROUP "gen_PCSA.THE_MEDIA_PCSA/media_interface_group" REGION "MEDIA_DOWN1" ; #LOCATE UGROUP "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/media_interface_group" REGION "MEDIA_DOWN1" ; #LOCATE UGROUP "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/media_interface_group" REGION "MEDIA_DOWN1" ; #LOCATE UGROUP "THE_MEDIA_4_PCSC/media_interface_group" REGION "MEDIA_DOWN1" ; #LOCATE UGROUP "gen_PCSD.THE_MEDIA_4_PCSD/media_interface_group" REGION "MEDIA_DOWN1" ; -LOCATE UGROUP "gen_PCSB.THE_MEDIA_PCSB/media_interface_group" REGION "MEDIA_DOWN1" ; -LOCATE UGROUP "gen_PCSC.THE_MEDIA_PCSC/media_interface_group" REGION "MEDIA_DOWN1" ; +LOCATE UGROUP "gen_PCSB.THE_MEDIA_PCSB/media_interface_group" REGION "MEDIA_B" ; +LOCATE UGROUP "gen_PCSC.THE_MEDIA_PCSC/media_interface_group" REGION "MEDIA_C" ; +LOCATE UGROUP "gen_PCSB_ADDON.THE_MEDIA_PCSB/media_interface_group" REGION "MEDIA_B" ; +# UGROUP "GBE_GROUP" BBOX 44 60 +# # BLKNAME GBE; +# BLKNAME GBE/physical_impl_gen.physical +# ; +# LOCATE UGROUP "GBE_GROUP" SITE "R71C2D"; #114 54 FREQUENCY NET "GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/clk_int.SERDES_GBE/sd_rx_clk_1" 125.0 MHz; FREQUENCY NET "GBE/clk_125_rx_from_pcs[3]" 125 MHz; @@ -40,6 +51,14 @@ BLOCK PATH FROM CLKNET "gen_PCSB.THE_MEDIA_PCSB/sci_write_i"; BLOCK PATH TO CLKNET "gen_PCSB.THE_MEDIA_PCSB/sci_read_i"; BLOCK PATH FROM CLKNET "gen_PCSB.THE_MEDIA_PCSB/sci_read_i"; # +MULTICYCLE TO CELL "gen_PCSB_ADDON.THE_MEDIA_PCSB/sci*" 20 ns; +MULTICYCLE FROM CELL "gen_PCSB_ADDON.THE_MEDIA_PCSB/sci*" 20 ns; +MULTICYCLE TO CELL "gen_PCSB_ADDON.THE_MEDIA_PCSB/PROC_SCI_CTRL.wa*" 20 ns; +BLOCK PATH TO CLKNET "gen_PCSB_ADDON.THE_MEDIA_PCSB/sci_write_i"; +BLOCK PATH FROM CLKNET "gen_PCSB_ADDON.THE_MEDIA_PCSB/sci_write_i"; +BLOCK PATH TO CLKNET "gen_PCSB_ADDON.THE_MEDIA_PCSB/sci_read_i"; +BLOCK PATH FROM CLKNET "gen_PCSB_ADDON.THE_MEDIA_PCSB/sci_read_i"; +# MULTICYCLE TO CELL "gen_PCSC.THE_MEDIA_PCSC/sci*" 20 ns; MULTICYCLE FROM CELL "gen_PCSC.THE_MEDIA_PCSC/sci*" 20 ns; MULTICYCLE TO CELL "gen_PCSC.THE_MEDIA_PCSC/PROC_SCI_CTRL.wa*" 20 ns; @@ -78,6 +97,9 @@ BLOCK PATH FROM CLKNET "gen_PCSC.THE_MEDIA_PCSC/sci_read_i"; MULTICYCLE TO ASIC gen_PCSB.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; MAXDELAY TO ASIC gen_PCSB.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; # +MULTICYCLE TO ASIC gen_PCSB_ADDON.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; +MAXDELAY TO ASIC gen_PCSB_ADDON.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; +# MULTICYCLE TO ASIC gen_PCSC.THE_MEDIA_PCSC/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; MAXDELAY TO ASIC gen_PCSC.THE_MEDIA_PCSC/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; @@ -90,7 +112,7 @@ MAXDELAY TO ASIC gen_PCSC.THE_MEDIA_PCSC/THE_SERDES/PCSD_INST PIN SCIRD 15 ns #MULTICYCLE TO ASIC gen_PCSD.THE_MEDIA_4_PCSD/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; #MAXDELAY TO ASIC gen_PCSD.THE_MEDIA_4_PCSD/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; - +PROHIBIT SECONDARY NET "THE_TOOLS/gen_STATISTICS.THE_STAT_LOGIC/reset_cnt" ; # PROHIBIT PRIMARY NET "THE_MEDIA_INTERFACE/clk_rx_full" ; # PROHIBIT SECONDARY NET "THE_MEDIA_INTERFACE/clk_rx_full" ; diff --git a/cts/trb3sc_cts.vhd b/cts/trb3sc_cts.vhd index 5268205..c9930bc 100644 --- a/cts/trb3sc_cts.vhd +++ b/cts/trb3sc_cts.vhd @@ -69,10 +69,10 @@ entity trb3sc_cts is ADC_DOUT : in std_logic; --SPI - DAC_OUT_SDO : out std_logic_vector(6 downto 5); - DAC_OUT_SCK : out std_logic_vector(6 downto 5); - DAC_OUT_CS : out std_logic_vector(6 downto 5); - DAC_IN_SDI : in std_logic_vector(6 downto 5); +-- DAC_OUT_SDO : out std_logic_vector(6 downto 5); +-- DAC_OUT_SCK : out std_logic_vector(6 downto 5); +-- DAC_OUT_CS : out std_logic_vector(6 downto 5); +-- DAC_IN_SDI : in std_logic_vector(6 downto 5); --Flash, 1-wire, Reload @@ -140,16 +140,16 @@ architecture trb3sc_arch of trb3sc_cts is signal timer : TIMERS; signal reset_via_gbe : std_logic := '0'; - signal med_dataready_out : std_logic_vector (5-1 downto 0); - signal med_data_out : std_logic_vector (5*c_DATA_WIDTH-1 downto 0); - signal med_packet_num_out : std_logic_vector (5*c_NUM_WIDTH-1 downto 0); - signal med_read_in : std_logic_vector (5-1 downto 0); - signal med_dataready_in : std_logic_vector (5-1 downto 0); - signal med_data_in : std_logic_vector (5*c_DATA_WIDTH-1 downto 0); - signal med_packet_num_in : std_logic_vector (5*c_NUM_WIDTH-1 downto 0); - signal med_read_out : std_logic_vector (5-1 downto 0); - signal med_stat_op : std_logic_vector (5*16-1 downto 0); - signal med_ctrl_op : std_logic_vector (5*16-1 downto 0); + signal med_dataready_out : std_logic_vector ((1+USE_ADDON*7)-1 downto 0); + signal med_data_out : std_logic_vector ((1+USE_ADDON*7)*c_DATA_WIDTH-1 downto 0); + signal med_packet_num_out : std_logic_vector ((1+USE_ADDON*7)*c_NUM_WIDTH-1 downto 0); + signal med_read_in : std_logic_vector ((1+USE_ADDON*7)-1 downto 0); + signal med_dataready_in : std_logic_vector ((1+USE_ADDON*7)-1 downto 0); + signal med_data_in : std_logic_vector ((1+USE_ADDON*7)*c_DATA_WIDTH-1 downto 0); + signal med_packet_num_in : std_logic_vector ((1+USE_ADDON*7)*c_NUM_WIDTH-1 downto 0); + signal med_read_out : std_logic_vector ((1+USE_ADDON*7)-1 downto 0); + signal med_stat_op : std_logic_vector ((1+USE_ADDON*7)*16-1 downto 0); + signal med_ctrl_op : std_logic_vector ((1+USE_ADDON*7)*16-1 downto 0); signal rdack, wrack : std_logic; signal monitor_inputs_i : std_logic_vector(MONITOR_INPUT_NUM-1 downto 0); @@ -298,7 +298,7 @@ bussci1_tx.unknown <= '1'; --------------------------------------------------------------------------- -- PCSB Downlink without backplane is SFP --------------------------------------------------------------------------- -gen_PCSB : if USE_BACKPLANE = c_NO generate +gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate THE_MEDIA_PCSB : entity work.med_ecp3_sfp_sync generic map( SERDES_NUM => 3, @@ -331,6 +331,7 @@ gen_PCSB : if USE_BACKPLANE = c_NO generate STAT_DEBUG => open, CTRL_DEBUG => open ); + PCSSW <= "01001110"; --SFP2 on B3, AddOn on D1 end generate; --------------------------------------------------------------------------- @@ -354,14 +355,14 @@ gen_PCSC : if USE_BACKPLANE = c_NO and USE_ADDON = c_YES generate CLEAR => clear_i, --Internal Connection - MEDIA_MED2INT(0) => med2int(3), - MEDIA_MED2INT(1) => med2int(4), - MEDIA_MED2INT(2) => med2int(1), - MEDIA_MED2INT(3) => med2int(2), - MEDIA_INT2MED(0) => int2med(3), - MEDIA_INT2MED(1) => int2med(4), - MEDIA_INT2MED(2) => int2med(1), - MEDIA_INT2MED(3) => int2med(2), + MEDIA_MED2INT(0) => med2int(2), + MEDIA_MED2INT(1) => med2int(3), + MEDIA_MED2INT(2) => med2int(0), + MEDIA_MED2INT(3) => med2int(1), + MEDIA_INT2MED(0) => int2med(2), + MEDIA_INT2MED(1) => int2med(3), + MEDIA_INT2MED(2) => int2med(0), + MEDIA_INT2MED(3) => int2med(1), --Sync operation RX_DLM => open, @@ -395,6 +396,61 @@ gen_PCSC : if USE_BACKPLANE = c_NO and USE_ADDON = c_YES generate ); end generate; +gen_PCSB_ADDON : if USE_BACKPLANE = c_NO and USE_ADDON = c_YES generate + THE_MEDIA_PCSB : entity work.med_ecp3_sfp_sync_4 + generic map( + IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_NO), + IS_USED => (c_YES,c_YES ,c_YES ,c_YES) + ) + port map( + CLK_REF_FULL => clk_full_osc, + CLK_INTERNAL_FULL => clk_full_osc, + SYSCLK => clk_sys, + RESET => reset_i, + CLEAR => clear_i, + + --Internal Connection + MEDIA_MED2INT(0) => med2int(4), + MEDIA_MED2INT(1) => med2int(5), + MEDIA_MED2INT(2) => med2int(6), + MEDIA_MED2INT(3) => med2int(7), + MEDIA_INT2MED(0) => int2med(4), + MEDIA_INT2MED(1) => int2med(5), + MEDIA_INT2MED(2) => int2med(6), + MEDIA_INT2MED(3) => int2med(7), + + --Sync operation + RX_DLM => open, + RX_DLM_WORD => open, + TX_DLM => open, + TX_DLM_WORD => open, + + --SFP Connection + SD_PRSNT_N_IN(0) => HUB_MOD0(5), + SD_PRSNT_N_IN(1) => HUB_MOD0(6), + SD_PRSNT_N_IN(2) => HUB_MOD0(7), + SD_PRSNT_N_IN(3) => HUB_MOD0(8), + + SD_LOS_IN(0) => HUB_LOS(5), + SD_LOS_IN(1) => HUB_LOS(6), + SD_LOS_IN(2) => HUB_LOS(7), + SD_LOS_IN(3) => HUB_LOS(8), + + SD_TXDIS_OUT(0) => HUB_TXDIS(5), + SD_TXDIS_OUT(1) => HUB_TXDIS(6), + SD_TXDIS_OUT(2) => HUB_TXDIS(7), + SD_TXDIS_OUT(3) => HUB_TXDIS(8), + + --Control Interface + BUS_RX => bussci2_rx, + BUS_TX => bussci2_tx, + + -- Status and control port + STAT_DEBUG => open, --med_stat_debug(63 downto 0), + CTRL_DEBUG => open + ); + PCSSW <= "11100100"; --01001110"; --default 1:1 +end generate; --------------------------------------------------------------------------- -- GbE (PCSD) @@ -721,7 +777,7 @@ end generate; cts_addon_triggers_in(1 downto 0) <= SPARE_IN(1 downto 0); cts_addon_triggers_in(41 downto 2) <= KEL(40 downto 1); - cts_addon_triggers_in(43 downto 42) <= trigger_gen_outputs_i; + cts_addon_triggers_in(43 downto 42) <= trigger_gen_outputs_i when rising_edge(clk_sys); buscts_tx.nack <= '0'; buscts_tx.ack <= '0'; @@ -882,7 +938,7 @@ end generate; PCSSW_ENSMB <= '0'; PCSSW_EQ <= x"0"; PCSSW_PE <= x"F"; - PCSSW <= "01001110"; --SFP2 on B3, AddOn on D1 + --------------------------------------------------------------------------- -- I/O @@ -907,11 +963,13 @@ end generate; gen_leds_addon : if USE_ADDON = c_YES generate - gen_hub_leds : for i in 1 to 4 generate - LED_HUB_LINKOK(i) <= not med2int(i).stat_op(9); - LED_HUB_TX(i) <= not (med2int(i).stat_op(10) or not med2int(i).stat_op(9)); - LED_HUB_RX(i) <= not (med2int(i).stat_op(11)); + gen_hub_leds : for i in 1 to 8 generate + LED_HUB_LINKOK(i) <= not med2int(i-1).stat_op(9); + LED_HUB_TX(i) <= not (med2int(i-1).stat_op(10) or not med2int(i-1).stat_op(9)); + LED_HUB_RX(i) <= not (med2int(i-1).stat_op(11)); end generate; + LED_SFP_GREEN(1) <= '1'; + LED_SFP_RED(1) <= '1'; end generate; -- LED_HUB_LINKOK(8) <= not med2int(7).stat_op(9) when INCLUDE_GBE = 0 else @@ -924,12 +982,12 @@ end generate; '1'; LED_SFP_RED(0) <= --not (med2int(8).stat_op(10) or med2int(8).stat_op(11) or not med2int(8).stat_op(9)) when INCLUDE_GBE = 0 else '1'; - +gen_leds_addon : if USE_ADDON = c_NO generate LED_SFP_GREEN(1) <= not med2int(0).stat_op(9) when USE_BACKPLANE = 0 else '1'; LED_SFP_RED(1) <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11) or not med2int(0).stat_op(9)) when USE_BACKPLANE = 0 else '1'; - +end generate; -- LED_WHITE(0) <= not med2int(10).stat_op(9) when INCLUDE_GBE = 0 and USE_BACKPLANE = 1 else -- not med2int(8).stat_op(9) when INCLUDE_GBE = 1 and USE_BACKPLANE = 1 else -- '1'; @@ -940,42 +998,43 @@ end generate; ------------------------------------------------------------------------------- -- TDC ------------------------------------------------------------------------------- --- THE_TDC : entity work.TDC_record --- generic map ( --- CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels per module --- STATUS_REG_NR => 21, -- Number of status regs --- DEBUG => c_YES, --- SIMULATION => c_NO) --- port map ( --- RESET => reset_i, --- CLK_TDC => clk_full_osc, --- CLK_READOUT => clk_sys, -- Clock for the readout --- REFERENCE_TIME => cts_trigger_out, -- Reference time input --- HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals --- HIT_CAL_IN => clk_cal, -- Hits for calibrating the TDC --- -- Trigger signals from handler --- BUSRDO_RX => cts_rdo_rx, --- BUSRDO_TX => cts_rdo_additional(INCLUDE_TIMESTAMP_GENERATOR + INCLUDE_ETM), --- -- Slow control bus --- BUS_RX => bustdc_rx, --- BUS_TX => bustdc_tx, --- -- Dubug signals --- INFO_IN => timer, --- LOGIC_ANALYSER_OUT => open --- ); --- --- -- For single edge measurements --- gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate --- hit_in_i(NUM_TDC_CHANNELS-1 downto 1) <= INP(NUM_TDC_CHANNELS-2+64 downto 64); --- end generate; --- --- -- For ToT Measurements --- gen_double : if DOUBLE_EDGE_TYPE = 2 generate --- Gen_Hit_In_Signals : for i in 0 to NUM_TDC_CHANNELS-2 generate --- hit_in_i(i*2+1) <= INP(i+64); --- hit_in_i(i*2+2) <= not INP(i+64); --- end generate Gen_Hit_In_Signals; --- end generate; + THE_TDC : entity work.TDC_record + generic map ( + CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels per module + STATUS_REG_NR => 21, -- Number of status regs + DEBUG => c_YES, + SIMULATION => c_NO) + port map ( + RESET => reset_i, + CLK_TDC => clk_full_osc, + CLK_READOUT => clk_sys, -- Clock for the readout + REFERENCE_TIME => cts_trigger_out, -- Reference time input + HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals + HIT_CAL_IN => clk_cal, -- Hits for calibrating the TDC + -- Trigger signals from handler + BUSRDO_RX => cts_rdo_rx, + BUSRDO_TX => cts_rdo_additional(INCLUDE_TIMESTAMP_GENERATOR + INCLUDE_ETM), + -- Slow control bus + BUS_RX => bustdc_rx, + BUS_TX => bustdc_tx, + -- Dubug signals + INFO_IN => timer, + LOGIC_ANALYSER_OUT => open + ); + + -- For single edge measurements + gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate + hit_in_i(NUM_TDC_CHANNELS-1 downto 1) <= KEL(NUM_TDC_CHANNELS-1 downto 1); + end generate; + +-- -- +-- -- -- For ToT Measurements +-- -- gen_double : if DOUBLE_EDGE_TYPE = 2 generate +-- -- Gen_Hit_In_Signals : for i in 0 to NUM_TDC_CHANNELS-2 generate +-- -- hit_in_i(i*2+1) <= INP(i+64); +-- -- hit_in_i(i*2+2) <= not INP(i+64); +-- -- end generate Gen_Hit_In_Signals; +-- -- end generate; end architecture; -- 2.43.0