From b82c54ab0f88fe36fbddf7648f5b648b929062ec Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Wed, 9 Nov 2022 21:31:59 +0100 Subject: [PATCH] bug fixed finally, MAC data stream may be interupted now. SCTRL working again. --- gbe_trb/base/gbe_frame_receiver.vhd | 90 ++++----- .../gbe_response_constructor_SCTRL.vhd | 178 ++++++++++-------- 2 files changed, 139 insertions(+), 129 deletions(-) diff --git a/gbe_trb/base/gbe_frame_receiver.vhd b/gbe_trb/base/gbe_frame_receiver.vhd index 3b86ac8..c96d1fe 100644 --- a/gbe_trb/base/gbe_frame_receiver.vhd +++ b/gbe_trb/base/gbe_frame_receiver.vhd @@ -83,7 +83,6 @@ architecture gbe_frame_receiver_arch of gbe_frame_receiver is signal stored_src_port : std_logic_vector(15 downto 0); signal stored_dst_port : std_logic_vector(15 downto 0); --- signal fifo_pl_wr_x : std_logic; signal fifo_pl_wr : std_logic; signal fifo_hd_wr_x : std_logic; signal fifo_hd_wr : std_logic; @@ -127,18 +126,16 @@ begin -- generate a "emergency stop" signal mac_rx_eof_qq <= mac_rx_eof_q when rising_edge(CLK); - -- FSM to decode the incoming stream + -- FSM to decode the incoming stream PROC_DECODE_FSM: process( CLK, RESET ) begin if ( RESET = '1' ) then DECODE_CS <= IDLE; --- fifo_pl_wr <= '0'; fifo_hd_wr <= '0'; drop_frame <= '0'; rst_bytes <= '1'; elsif( rising_edge(CLK) ) then DECODE_CS <= DECODE_NS; --- fifo_pl_wr <= fifo_pl_wr_x; fifo_hd_wr <= fifo_hd_wr_x; drop_frame <= drop_frame_x; rst_bytes <= rst_bytes_x; @@ -149,7 +146,6 @@ begin is_my_mac_x, is_broadcast_x, is_arp_x, is_ipv4_x, is_udp_x, is_version_x, is_sctrl_x, is_icmp_x ) begin --- fifo_pl_wr_x <= '0'; fifo_hd_wr_x <= '0'; drop_frame_x <= '0'; rst_bytes_x <= '0'; @@ -181,7 +177,6 @@ begin if( (mac_rx_eof_q = '0') ) then -- payload available, store it DECODE_NS <= STORE_FRAME; --- fifo_pl_wr_x <= '1'; else -- empty payload, must never happen with ARP, so we drop it DECODE_NS <= LAST_BYTE; @@ -196,7 +191,6 @@ begin if( (mac_rx_eof_q = '0') ) then -- payload available DECODE_NS <= STORE_FRAME; --- fifo_pl_wr_x <= '1'; else -- empty payload, must never happen with ICMP, so we drop it DECODE_NS <= LAST_BYTE; @@ -214,7 +208,6 @@ begin if( (mac_rx_eof_q = '0') ) then -- payload available DECODE_NS <= STORE_FRAME; --- fifo_pl_wr_x <= '1'; else -- empty payload, store raw frame, check that later? DECODE_NS <= LAST_BYTE; @@ -255,7 +248,6 @@ begin when STORE_FRAME => decode_fsm <= x"3"; --- fifo_pl_wr_x <= '1'; if( MAC_RX_EOF_IN = '1' ) then DECODE_NS <= LAST_BYTE; fifo_hd_wr_x <= '1'; @@ -285,20 +277,6 @@ begin end case; end process PROC_DECODE_TRANSITIONS; --- -- counter for decoding the byte stream --- PROC_DECODE_CTR: process( CLK, RESET ) --- begin --- if ( RESET = '1' ) then --- decode_ctr <= (others => '0'); --- elsif( rising_edge(CLK) ) then --- if( (DECODE_CS = STORE_HEADER) or (DECODE_CS = STORE_FRAME) ) then --- decode_ctr <= decode_ctr + 1; --- else --- decode_ctr <= (others => '0'); --- end if; --- end if; --- end process PROC_DECODE_CTR; - -- counter for decoding the byte stream PROC_DECODE_CTR: process( CLK, RESET ) begin @@ -331,28 +309,44 @@ begin end if; end process PROC_RX_FIFO_SYNC; + PROC_STORE_FIRST_BYTE: process( CLK ) + begin + if( rising_edge(CLK) ) then + if ( (DECODE_CS = DELAY) ) then + stored_dst_mac(7 downto 0) <= (others => '0'); + elsif( (DECODE_CS = IDLE) and (MAC_RX_EN_IN = '1') and (decode_ctr = x"00") ) then + stored_dst_mac(7 downto 0) <= MAC_RXD_IN; + end if; + end if; + end process PROC_STORE_FIRST_BYTE; + + PROC_STORE_SECOND_BYTE: process( CLK ) + begin + if( rising_edge(CLK) ) then + if ( (DECODE_CS = DELAY) ) then + stored_dst_mac(15 downto 8) <= (others => '0'); + elsif( (DECODE_CS = STORE_HEADER) and (MAC_RX_EN_IN = '1') and (decode_ctr = x"00") ) then + stored_dst_mac(15 downto 8) <= MAC_RXD_IN; + end if; + end if; + end process PROC_STORE_SECOND_BYTE; + -- storing the relevant parts of headers for decision and further usage - PROC_STORE_INFO: process( CLK, RESET ) + PROC_STORE_INFO: process( CLK ) begin - if ( RESET = '1' ) then - stored_src_mac <= (others => '0'); - stored_dst_mac <= (others => '0'); - stored_ethertype <= (others => '0'); - stored_version <= (others => '0'); - stored_protocol <= (others => '0'); - stored_src_ip <= (others => '0'); - stored_dst_ip <= (others => '0'); - stored_src_port <= (others => '0'); - stored_dst_port <= (others => '0'); - elsif( rising_edge(CLK) ) then --- if( (MAC_RX_EN_IN = '1') and (mac_rx_en_q = '0') ) then --- -- early bird --- stored_dst_mac(7 downto 0) <= MAC_RXD_IN; -- FUCKING BUG!!!! --- end if; - if( (mac_rx_en_q = '1') and (DECODE_CS = STORE_HEADER) ) then + if( rising_edge(CLK) ) then + if( (DECODE_CS = DELAY) ) then + stored_dst_mac(47 downto 16) <= (others => '0'); + stored_src_mac <= (others => '0'); + stored_ethertype <= (others => '0'); + stored_version <= (others => '0'); + stored_protocol <= (others => '0'); + stored_src_ip <= (others => '0'); + stored_dst_ip <= (others => '0'); + stored_src_port <= (others => '0'); + stored_dst_port <= (others => '0'); + elsif( (DECODE_CS = STORE_HEADER) and (MAC_RX_EN_IN = '1') ) then case decode_ctr is - when x"00" => stored_dst_mac(15 downto 8) <= MAC_RXD_IN; - stored_dst_mac(7 downto 0) <= mac_rxd_q; when x"01" => stored_dst_mac(23 downto 16) <= MAC_RXD_IN; when x"02" => stored_dst_mac(31 downto 24) <= MAC_RXD_IN; when x"03" => stored_dst_mac(39 downto 32) <= MAC_RXD_IN; @@ -382,18 +376,6 @@ begin when others => null; end case; end if; --- if( (DECODE_CS = WRITE_HDR) ) then - if( (DECODE_CS = DELAY) ) then - stored_src_mac <= (others => '0'); - stored_dst_mac <= (others => '0'); - stored_ethertype <= (others => '0'); - stored_version <= (others => '0'); - stored_protocol <= (others => '0'); - stored_src_ip <= (others => '0'); - stored_dst_ip <= (others => '0'); - stored_src_port <= (others => '0'); - stored_dst_port <= (others => '0'); - end if; end if; end process PROC_STORE_INFO; diff --git a/gbe_trb/protocols/gbe_response_constructor_SCTRL.vhd b/gbe_trb/protocols/gbe_response_constructor_SCTRL.vhd index e3e605a..9ff54bf 100644 --- a/gbe_trb/protocols/gbe_response_constructor_SCTRL.vhd +++ b/gbe_trb/protocols/gbe_response_constructor_SCTRL.vhd @@ -52,7 +52,7 @@ entity gbe_response_constructor_SCTRL is GSC_INIT_READ_IN : in std_logic; GSC_REPLY_DATAREADY_IN : in std_logic; GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0); - GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0); + GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0); -- not used GSC_REPLY_READ_OUT : out std_logic; GSC_BUSY_IN : in std_logic; MAKE_RESET_OUT : out std_logic; @@ -69,9 +69,9 @@ architecture gbe_response_constructor_SCTRL_arch of gbe_response_constructor_SCT attribute syn_encoding : string; - type dissect_states is (IDLE, READ_FRAME, WAIT_FOR_HUB, LOAD_TO_HUB, WAIT_FOR_RESPONSE, SAVE_RESPONSE, DELAY, LOAD_FRAME, WAIT_FOR_LOAD, CLEANUP); - signal dissect_current_state, dissect_next_state : dissect_states; - attribute syn_encoding of dissect_current_state: signal is "onehot"; + type DISSECT_STATES is (IDLE, READ_FRAME, WAIT_FOR_HUB, LOAD_TO_HUB, WAIT_FOR_RESPONSE, SAVE_RESPONSE, DELAY, LOAD_FRAME, WAIT_FOR_LOAD, CLEANUP); + signal DISSECT_CS, DISSECT_NS : DISSECT_STATES; + attribute syn_encoding of DISSECT_CS: signal is "onehot"; signal rx_fifo_q : std_logic_vector(17 downto 0); signal rx_fifo_qq : std_logic_vector(17 downto 0); @@ -121,17 +121,23 @@ architecture gbe_response_constructor_SCTRL_arch of gbe_response_constructor_SCT signal mon_sent_frames : unsigned(31 downto 0); signal mon_sent_bytes : unsigned(31 downto 0); + signal rx_cnt : std_logic_vector(15 downto 0); + signal tx_cnt : std_logic_vector(15 downto 0); + + -- TO BE REMOVED LATER. + signal delay_ctr : unsigned(13 downto 0); + signal delay_done : std_logic; + + -- TEST + signal saved_dst_mac : std_logic_vector(47 downto 0); + signal store_mac_x : std_logic; + signal store_mac : std_logic; + attribute syn_preserve : boolean; attribute syn_keep : boolean; attribute syn_keep of rx_fifo_wr, rx_fifo_rd, gsc_init_dataready, tx_fifo_wr, tx_fifo_rd, gsc_reply_read, state : signal is true; attribute syn_preserve of rx_fifo_wr, rx_fifo_rd, gsc_init_dataready, tx_fifo_wr, tx_fifo_rd, gsc_reply_read, state : signal is true; - signal rx_cnt : std_logic_vector(15 downto 0); - signal tx_cnt : std_logic_vector(15 downto 0); - - signal delay_ctr : unsigned(13 downto 0); - signal delay_done : std_logic; - begin -- DEBUG lines @@ -152,6 +158,19 @@ begin MAKE_RESET_OUT <= make_reset; + -- TEST + PROC_STORE_MAC: process( CLK ) + begin + if( rising_edge(CLK) ) then + if ( DISSECT_CS = IDLE ) then + saved_dst_mac <= (others => '0'); + elsif( store_mac = '1' ) then + saved_dst_mac <= PS_SRC_MAC_ADDRESS_IN; + end if; + end if; + end process PROC_STORE_MAC; + + -- stores incoming TRBnet requests THE_RECEIVE_FIFO: entity work.fifo_2kx9x18_wcnt port map( Reset => RESET, @@ -168,9 +187,9 @@ begin ); --TODO: change to synchronous - rx_fifo_rd <= '1' when (gsc_init_dataready = '1' and dissect_current_state = LOAD_TO_HUB) or - (gsc_init_dataready = '1' and dissect_current_state = WAIT_FOR_HUB and GSC_INIT_READ_IN = '1') or - (dissect_current_state = READ_FRAME and PS_DATA_IN(8) = '1') + rx_fifo_rd <= '1' when ((DISSECT_CS = LOAD_TO_HUB) and (gsc_init_dataready = '1')) or + ((DISSECT_CS = WAIT_FOR_HUB) and (gsc_init_dataready = '1') and (GSC_INIT_READ_IN = '1')) or + ((DISSECT_CS = READ_FRAME) and (PS_DATA_IN(8) = '1')) else '0'; -- preload first word PROC_RX_FIFO_WR_SYNC: process( CLK ) @@ -187,10 +206,11 @@ begin end if; end process PROC_RX_FIFO_WR_SYNC; + -- one travelling bit PROC_SAVED_HDR_CTR: process( CLK ) begin if( rising_edge(CLK) ) then - if ( (PS_WR_EN_IN = '0') and (PS_ACTIVATE_IN = '0') and (dissect_current_state = IDLE) ) then + if ( (PS_WR_EN_IN = '0') and (PS_ACTIVATE_IN = '0') and (DISSECT_CS = IDLE) ) then saved_hdr_ctr <= "0001"; elsif( (PS_WR_EN_IN = '1') and (PS_ACTIVATE_IN = '1') and (saved_hdr_ctr /= "1000") ) then saved_hdr_ctr(3 downto 0) <= saved_hdr_ctr(2 downto 0) & '0'; @@ -204,10 +224,8 @@ begin if( PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1' ) then if ( saved_hdr_ctr = "0001" ) then saved_hdr_1 <= PS_DATA_IN(7 downto 0); - saved_hdr_2 <= saved_hdr_2; elsif( saved_hdr_ctr = "0010" ) then saved_hdr_2 <= PS_DATA_IN(7 downto 0); - saved_hdr_1 <= saved_hdr_1; end if; end if; end if; @@ -220,18 +238,20 @@ begin ------ TODO: change it to synchronous GSC_INIT_PACKET_NUM_OUT <= std_logic_vector(packet_num); GSC_INIT_DATAREADY_OUT <= gsc_init_dataready; - gsc_init_dataready <= '1' when (GSC_INIT_READ_IN = '1' and dissect_current_state = LOAD_TO_HUB) or -- JM: TODO Ob das so richtig ist, ohne auf fifo_rd zu schauen? - (dissect_current_state = WAIT_FOR_HUB) + -- JM: TODO Ob das so richtig ist, ohne auf fifo_rd zu schauen? + gsc_init_dataready <= '1' when ((DISSECT_CS = LOAD_TO_HUB) and (GSC_INIT_READ_IN = '1')) or + ((DISSECT_CS = WAIT_FOR_HUB)) else '0'; PROC_PACKET_NUM: process( CLK ) begin if( rising_edge(CLK) ) then - if( dissect_current_state = IDLE ) then + if( DISSECT_CS = IDLE ) then packet_num <= "100"; - elsif( GSC_INIT_READ_IN = '1' and rx_fifo_rd = '1' and packet_num = "100" and dissect_current_state /= READ_FRAME ) then -- JM: BUG zählt schon hoch beim fifo_rd weil read schon 1 ist. read geht aber nur auf 1 wenn dataready auf 1 ist + elsif( (GSC_INIT_READ_IN = '1') and (rx_fifo_rd = '1') and (packet_num = "100") and (DISSECT_CS /= READ_FRAME) ) then + -- JM: BUG zaehlt schon hoch beim fifo_rd weil read schon 1 ist. read geht aber nur auf 1 wenn dataready auf 1 ist packet_num <= "000"; - elsif( rx_fifo_rd = '1' and packet_num /= "100" ) then + elsif( (rx_fifo_rd = '1') and (packet_num /= "100") ) then packet_num <= packet_num + "1"; end if; end if; @@ -274,7 +294,7 @@ begin PROC_TX_FIFO_WR_SYNC: process( CLK ) begin if( rising_edge(CLK) ) then - if ( GSC_REPLY_DATAREADY_IN = '1' and gsc_reply_read = '1' ) then + if ( (GSC_REPLY_DATAREADY_IN = '1') and (gsc_reply_read = '1') ) then tx_fifo_wr <= '1'; elsif( saved_hdr_ctr = "0010" ) then tx_fifo_wr <= '1'; @@ -283,7 +303,7 @@ begin end if; if( saved_hdr_ctr(2 downto 0) = "010" ) then - tx_fifo_data <= '0' & PS_DATA_IN(7 downto 0) & '0' & x"02"; + tx_fifo_data <= '0' & PS_DATA_IN(7 downto 0) & '0' & x"02"; -- "reply" + random byte else tx_fifo_data(7 downto 0) <= GSC_REPLY_DATA_IN(15 downto 8); tx_fifo_data(8) <= '0'; @@ -293,14 +313,14 @@ begin end if; end process PROC_TX_FIFO_WR_SYNC; - tx_fifo_rd <= '1' when TC_RD_EN_IN = '1' and PS_SELECTED_IN = '1' else '0'; + tx_fifo_rd <= '1' when (TC_RD_EN_IN = '1') and (PS_SELECTED_IN = '1') else '0'; TX_FIFO_SYNC_PROC: process( CLK, RESET ) begin if ( RESET = '1' ) then tx_fifo_reset <= '1'; elsif( rising_edge(CLK) ) then - if( too_much_data = '1' and dissect_current_state = CLEANUP ) then + if( (too_much_data = '1') and (DISSECT_CS = CLEANUP) ) then tx_fifo_reset <= '1'; else tx_fifo_reset <= '0'; @@ -325,7 +345,7 @@ begin GSC_REPLY_READ_PROC: process( CLK ) begin if( rising_edge(CLK) ) then - if( dissect_current_state = WAIT_FOR_RESPONSE or dissect_current_state = SAVE_RESPONSE ) then + if( (DISSECT_CS = WAIT_FOR_RESPONSE) or (DISSECT_CS = SAVE_RESPONSE) ) then gsc_reply_read <= '1'; else gsc_reply_read <= '0'; @@ -338,7 +358,7 @@ begin TX_DATA_CTR_PROC: process( CLK ) begin if( rising_edge(CLK) ) then - if (dissect_current_state = IDLE) then + if (DISSECT_CS = IDLE) then tx_data_ctr <= (others => '0'); elsif( tx_fifo_wr = '1' ) then tx_data_ctr <= tx_data_ctr + 2; @@ -349,9 +369,9 @@ begin TOO_MUCH_DATA_PROC: process( CLK ) begin if( rising_edge(CLK) ) then - if ( dissect_current_state = IDLE ) then + if ( DISSECT_CS = IDLE ) then too_much_data <= '0'; - elsif( (dissect_current_state = SAVE_RESPONSE) and (tx_data_ctr = unsigned(CFG_MAX_REPLY_SIZE_IN(15 downto 0))) ) then + elsif( (DISSECT_CS = SAVE_RESPONSE) and (tx_data_ctr = unsigned(CFG_MAX_REPLY_SIZE_IN(15 downto 0))) ) then too_much_data <= '1'; end if; end if; @@ -361,10 +381,10 @@ begin TX_LOADED_CTR_PROC: process( CLK ) begin if( rising_edge(CLK) ) then - if( dissect_current_state = IDLE ) then + if( DISSECT_CS = IDLE ) then tx_loaded_ctr <= x"0000"; - elsif( dissect_current_state = LOAD_FRAME and PS_SELECTED_IN = '1' and TC_RD_EN_IN = '1' ) then - tx_loaded_ctr <= tx_loaded_ctr + x"1"; + elsif( (DISSECT_CS = LOAD_FRAME) and (PS_SELECTED_IN = '1') and (TC_RD_EN_IN = '1') ) then + tx_loaded_ctr <= tx_loaded_ctr + 1; end if; end if; end process TX_LOADED_CTR_PROC; @@ -373,14 +393,14 @@ begin begin if( rising_edge(CLK) ) then if( too_much_data = '0' ) then - if( dissect_current_state = WAIT_FOR_LOAD or dissect_current_state = LOAD_FRAME or dissect_current_state = CLEANUP ) then + if( (DISSECT_CS = WAIT_FOR_LOAD) or (DISSECT_CS = LOAD_FRAME) or (DISSECT_CS = CLEANUP) ) then PS_RESPONSE_READY_OUT <= '1'; else PS_RESPONSE_READY_OUT <= '0'; end if; end if; - if( dissect_current_state = IDLE or dissect_current_state = WAIT_FOR_RESPONSE ) then + if( (DISSECT_CS = IDLE) or (DISSECT_CS = WAIT_FOR_RESPONSE) ) then PS_BUSY_OUT <= '0'; else PS_BUSY_OUT <= '1'; @@ -389,13 +409,14 @@ begin end process PS_RESPONSE_SYNC; TC_FRAME_TYPE_OUT <= x"0008"; - TC_DEST_MAC_OUT <= PS_SRC_MAC_ADDRESS_IN; +-- TC_DEST_MAC_OUT <= PS_SRC_MAC_ADDRESS_IN; + TC_DEST_MAC_OUT <= saved_dst_mac; TC_DEST_IP_OUT <= PS_SRC_IP_ADDRESS_IN; TC_DEST_UDP_OUT(7 downto 0) <= PS_SRC_UDP_PORT_IN(15 downto 8); TC_DEST_UDP_OUT(15 downto 8) <= PS_SRC_UDP_PORT_IN(7 downto 0); TC_SRC_MAC_OUT <= MY_MAC_IN; TC_SRC_IP_OUT <= MY_IP_IN; - TC_SRC_UDP_OUT <= x"9065"; --x"a861"; + TC_SRC_UDP_OUT <= x"9065"; --x"a861"; -- BUG?!? shouldn't we use the SRC UDP port? TC_IP_PROTOCOL_OUT <= x"11"; TC_IDENT_OUT <= x"3" & std_logic_vector(reply_ctr(11 downto 0)); @@ -404,115 +425,121 @@ begin DISSECT_MACHINE_PROC: process( CLK, RESET ) begin if ( RESET = '1' ) then - dissect_current_state <= IDLE; + DISSECT_CS <= IDLE; + store_mac <= '0'; elsif( rising_edge(CLK) ) then - dissect_current_state <= dissect_next_state; + DISSECT_CS <= DISSECT_NS; + store_mac <= store_mac_x; end if; end process DISSECT_MACHINE_PROC; - DISSECT_MACHINE: process( dissect_current_state, reset_detected, too_much_data, PS_WR_EN_IN, PS_ACTIVATE_IN, + DISSECT_MACHINE: process( DISSECT_CS, reset_detected, too_much_data, PS_WR_EN_IN, PS_ACTIVATE_IN, PS_DATA_IN, PS_SELECTED_IN, GSC_INIT_READ_IN, GSC_REPLY_DATAREADY_IN, tx_loaded_ctr, tx_data_ctr, rx_fifo_q, GSC_BUSY_IN, delay_done ) begin state <= x"0"; + store_mac_x <= '0'; - case dissect_current_state is + case DISSECT_CS is when IDLE => state <= x"1"; if( (PS_WR_EN_IN = '1') and (PS_ACTIVATE_IN = '1') ) then - dissect_next_state <= READ_FRAME; + DISSECT_NS <= READ_FRAME; + store_mac_x <= '1'; else - dissect_next_state <= IDLE; + DISSECT_NS <= IDLE; end if; when READ_FRAME => state <= x"2"; if ( (PS_DATA_IN(8) = '1') and (GSC_INIT_READ_IN = '0') ) then - dissect_next_state <= WAIT_FOR_HUB; + DISSECT_NS <= WAIT_FOR_HUB; elsif( (PS_DATA_IN(8) = '1') and (GSC_INIT_READ_IN = '1') ) then - dissect_next_state <= LOAD_TO_HUB; + DISSECT_NS <= LOAD_TO_HUB; else - dissect_next_state <= READ_FRAME; + DISSECT_NS <= READ_FRAME; end if; when WAIT_FOR_HUB => state <= x"3"; if( GSC_INIT_READ_IN = '1' ) then - dissect_next_state <= LOAD_TO_HUB; + DISSECT_NS <= LOAD_TO_HUB; else - dissect_next_state <= WAIT_FOR_HUB; + DISSECT_NS <= WAIT_FOR_HUB; end if; when LOAD_TO_HUB => state <= x"4"; if( (rx_fifo_q(17) = '1') and (GSC_INIT_READ_IN = '1') ) then if( reset_detected = '1' ) then - dissect_next_state <= CLEANUP; + DISSECT_NS <= CLEANUP; else - dissect_next_state <= WAIT_FOR_RESPONSE; + DISSECT_NS <= WAIT_FOR_RESPONSE; end if; else - dissect_next_state <= LOAD_TO_HUB; + DISSECT_NS <= LOAD_TO_HUB; end if; when WAIT_FOR_RESPONSE => state <= x"5"; if( GSC_REPLY_DATAREADY_IN = '1' ) then - dissect_next_state <= SAVE_RESPONSE; + DISSECT_NS <= SAVE_RESPONSE; else - dissect_next_state <= WAIT_FOR_RESPONSE; + DISSECT_NS <= WAIT_FOR_RESPONSE; end if; when SAVE_RESPONSE => state <= x"6"; if( (GSC_REPLY_DATAREADY_IN = '0') and (GSC_BUSY_IN = '0') ) then if( too_much_data = '0' ) then --- dissect_next_state <= WAIT_FOR_LOAD; - dissect_next_state <= DELAY; +-- DISSECT_NS <= WAIT_FOR_LOAD; + DISSECT_NS <= DELAY; else - dissect_next_state <= CLEANUP; + DISSECT_NS <= CLEANUP; end if; else - dissect_next_state <= SAVE_RESPONSE; + DISSECT_NS <= SAVE_RESPONSE; end if; when DELAY => + state <= x"a"; if( delay_done = '1' ) then - dissect_next_state <= WAIT_FOR_LOAD; + DISSECT_NS <= WAIT_FOR_LOAD; else - dissect_next_state <= DELAY; + DISSECT_NS <= DELAY; end if; when WAIT_FOR_LOAD => state <= x"7"; - if (PS_SELECTED_IN = '1') then - dissect_next_state <= LOAD_FRAME; + if( PS_SELECTED_IN = '1' ) then + DISSECT_NS <= LOAD_FRAME; else - dissect_next_state <= WAIT_FOR_LOAD; + DISSECT_NS <= WAIT_FOR_LOAD; end if; when LOAD_FRAME => state <= x"8"; - if (tx_loaded_ctr = tx_data_ctr) then - dissect_next_state <= CLEANUP; + if( tx_loaded_ctr = tx_data_ctr ) then + DISSECT_NS <= CLEANUP; else - dissect_next_state <= LOAD_FRAME; + DISSECT_NS <= LOAD_FRAME; end if; when CLEANUP => state <= x"9"; - dissect_next_state <= IDLE; + DISSECT_NS <= IDLE; - when others => dissect_next_state <= IDLE; + when others => DISSECT_NS <= IDLE; end case; end process DISSECT_MACHINE; + -- JUST FOR TESTING. TO BE REMOVED. PROC_DELAY_CTR: process( CLK ) begin if( rising_edge(CLK) ) then - if( dissect_current_state /= DELAY ) then + if( DISSECT_CS /= DELAY ) then delay_ctr <= (others => '0'); else delay_ctr <= delay_ctr + 1; @@ -520,15 +547,16 @@ begin end if; end process PROC_DELAY_CTR; - delay_done <= std_logic(delay_ctr(13)); +-- delay_done <= std_logic(delay_ctr(13)); + delay_done <= std_logic(delay_ctr(4)); -- reset request packet detection RESET_DETECTED_PROC: process( CLK ) begin if( rising_edge(CLK) ) then - if ( dissect_current_state = IDLE ) then + if ( DISSECT_CS = IDLE ) then reset_detected <= '0'; - elsif( PS_DATA_IN(7 downto 0) = x"80" and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1' and saved_hdr_ctr = "0100" ) then + elsif( (PS_DATA_IN(7 downto 0) = x"80") and (PS_WR_EN_IN = '1') and (PS_ACTIVATE_IN = '1') and (saved_hdr_ctr = "0100") ) then reset_detected <= '1'; end if; end if; @@ -537,9 +565,9 @@ begin MAKE_RESET_PROC: process( CLK ) begin if( rising_edge(CLK) ) then - if ( dissect_current_state = IDLE ) then + if ( DISSECT_CS = IDLE ) then make_reset <= '0'; - elsif( dissect_current_state = CLEANUP and reset_detected = '1' ) then + elsif( (DISSECT_CS = CLEANUP) and (reset_detected = '1') ) then make_reset <= '1'; end if; end if; @@ -552,7 +580,7 @@ begin if ( RESET = '1' ) then mon_rec_frames <= (others => '0'); elsif( rising_edge(CLK) ) then - if( dissect_current_state = READ_FRAME and PS_DATA_IN(8) = '1' ) then + if( (DISSECT_CS = READ_FRAME) and (PS_DATA_IN(8) = '1') ) then mon_rec_frames <= mon_rec_frames + 1; end if; end if; @@ -576,7 +604,7 @@ begin if ( RESET = '1' ) then mon_sent_frames <= (others => '0'); elsif( rising_edge(CLK) ) then - if( dissect_current_state = LOAD_FRAME and tx_loaded_ctr = tx_data_ctr ) then + if( (DISSECT_CS = LOAD_FRAME) and (tx_loaded_ctr = tx_data_ctr) ) then mon_sent_frames <= mon_sent_frames + 1; end if; end if; @@ -601,7 +629,7 @@ begin if ( RESET = '1' ) then reply_ctr <= (others => '0'); elsif( rising_edge(CLK) ) then - if( dissect_current_state = LOAD_FRAME and tx_loaded_ctr = tx_data_ctr ) then + if( (DISSECT_CS = LOAD_FRAME) and (tx_loaded_ctr = tx_data_ctr) ) then reply_ctr <= reply_ctr + 1; end if; end if; -- 2.43.0