From b8f7354e03984a9dd55bab064f017107b9e14168 Mon Sep 17 00:00:00 2001 From: Thomas Gessler Date: Thu, 25 Feb 2021 10:33:03 +0100 Subject: [PATCH] hub_test: Replace TX buf bypass with phase aligner This achieves a deterministic phase of the downlink TX data with respect to the reference clock (and system/CBM clock). --- hub_test/constrs/debug.xdc | 26 ++ hub_test/constrs/debug_tx_phase_aligner.xdc | 9 + hub_test/constrs/hub_test.xdc | 14 + hub_test/hub_test.xpr | 124 +++++---- hub_test/src/hub_test.vhd | 270 +++++++------------- 5 files changed, 208 insertions(+), 235 deletions(-) create mode 100644 hub_test/constrs/debug_tx_phase_aligner.xdc diff --git a/hub_test/constrs/debug.xdc b/hub_test/constrs/debug.xdc index 8752f0c..c3e136b 100644 --- a/hub_test/constrs/debug.xdc +++ b/hub_test/constrs/debug.xdc @@ -128,6 +128,32 @@ create_debug_port u_ila_2 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe8] set_property port_width 1 [get_debug_ports u_ila_2/probe8] connect_debug_port u_ila_2/probe8 [get_nets [list {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/TXCHARISK}]] +create_debug_core u_ila_3 ila +set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_3] +set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_3] +set_property C_ADV_TRIGGER false [get_debug_cores u_ila_3] +set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_3] +set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_3] +set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_3] +set_property C_TRIGIN_EN false [get_debug_cores u_ila_3] +set_property C_TRIGOUT_EN false [get_debug_cores u_ila_3] +set_property port_width 1 [get_debug_ports u_ila_3/clk] +connect_debug_port u_ila_3/clk [get_nets [list baseclk_100]] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_3/probe0] +set_property port_width 7 [get_debug_ports u_ila_3/probe0] +connect_debug_port u_ila_3/probe0 [get_nets [list {generate_downlinks[0].tx_phase_aligner_i/tx_pi_phase_o[0]} {generate_downlinks[0].tx_phase_aligner_i/tx_pi_phase_o[1]} {generate_downlinks[0].tx_phase_aligner_i/tx_pi_phase_o[2]} {generate_downlinks[0].tx_phase_aligner_i/tx_pi_phase_o[3]} {generate_downlinks[0].tx_phase_aligner_i/tx_pi_phase_o[4]} {generate_downlinks[0].tx_phase_aligner_i/tx_pi_phase_o[5]} {generate_downlinks[0].tx_phase_aligner_i/tx_pi_phase_o[6]}]] +create_debug_port u_ila_3 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_3/probe1] +set_property port_width 32 [get_debug_ports u_ila_3/probe1] +connect_debug_port u_ila_3/probe1 [get_nets [list {generate_downlinks[0].tx_phase_aligner_i/tx_fifo_fill_pd_o[0]} {generate_downlinks[0].tx_phase_aligner_i/tx_fifo_fill_pd_o[1]} {generate_downlinks[0].tx_phase_aligner_i/tx_fifo_fill_pd_o[2]} {generate_downlinks[0].tx_phase_aligner_i/tx_fifo_fill_pd_o[3]} {generate_downlinks[0].tx_phase_aligner_i/tx_fifo_fill_pd_o[4]} {generate_downlinks[0].tx_phase_aligner_i/tx_fifo_fill_pd_o[5]} {generate_downlinks[0].tx_phase_aligner_i/tx_fifo_fill_pd_o[6]} {generate_downlinks[0].tx_phase_aligner_i/tx_fifo_fill_pd_o[7]} {generate_downlinks[0].tx_phase_aligner_i/tx_fifo_fill_pd_o[8]} {generate_downlinks[0].tx_phase_aligner_i/tx_fifo_fill_pd_o[9]} {generate_downlinks[0].tx_phase_aligner_i/tx_fifo_fill_pd_o[10]} {generate_downlinks[0].tx_phase_aligner_i/tx_fifo_fill_pd_o[11]} {generate_downlinks[0].tx_phase_aligner_i/tx_fifo_fill_pd_o[12]} {generate_downlinks[0].tx_phase_aligner_i/tx_fifo_fill_pd_o[13]} {generate_downlinks[0].tx_phase_aligner_i/tx_fifo_fill_pd_o[14]} {generate_downlinks[0].tx_phase_aligner_i/tx_fifo_fill_pd_o[15]} {generate_downlinks[0].tx_phase_aligner_i/tx_fifo_fill_pd_o[16]} {generate_downlinks[0].tx_phase_aligner_i/tx_fifo_fill_pd_o[17]} {generate_downlinks[0].tx_phase_aligner_i/tx_fifo_fill_pd_o[18]} {generate_downlinks[0].tx_phase_aligner_i/tx_fifo_fill_pd_o[19]} {generate_downlinks[0].tx_phase_aligner_i/tx_fifo_fill_pd_o[20]} {generate_downlinks[0].tx_phase_aligner_i/tx_fifo_fill_pd_o[21]} {generate_downlinks[0].tx_phase_aligner_i/tx_fifo_fill_pd_o[22]} {generate_downlinks[0].tx_phase_aligner_i/tx_fifo_fill_pd_o[23]} {generate_downlinks[0].tx_phase_aligner_i/tx_fifo_fill_pd_o[24]} {generate_downlinks[0].tx_phase_aligner_i/tx_fifo_fill_pd_o[25]} {generate_downlinks[0].tx_phase_aligner_i/tx_fifo_fill_pd_o[26]} {generate_downlinks[0].tx_phase_aligner_i/tx_fifo_fill_pd_o[27]} {generate_downlinks[0].tx_phase_aligner_i/tx_fifo_fill_pd_o[28]} {generate_downlinks[0].tx_phase_aligner_i/tx_fifo_fill_pd_o[29]} {generate_downlinks[0].tx_phase_aligner_i/tx_fifo_fill_pd_o[30]} {generate_downlinks[0].tx_phase_aligner_i/tx_fifo_fill_pd_o[31]}]] +create_debug_port u_ila_3 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_3/probe2] +set_property port_width 1 [get_debug_ports u_ila_3/probe2] +connect_debug_port u_ila_3/probe2 [get_nets [list {generate_downlinks[0].tx_phase_aligner_i/reset_i}]] +create_debug_port u_ila_3 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_3/probe3] +set_property port_width 1 [get_debug_ports u_ila_3/probe3] +connect_debug_port u_ila_3/probe3 [get_nets [list {generate_downlinks[0].tx_phase_aligner_i/tx_aligned_o}]] set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub] set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub] set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub] diff --git a/hub_test/constrs/debug_tx_phase_aligner.xdc b/hub_test/constrs/debug_tx_phase_aligner.xdc new file mode 100644 index 0000000..7b0b2a0 --- /dev/null +++ b/hub_test/constrs/debug_tx_phase_aligner.xdc @@ -0,0 +1,9 @@ +set_property KEEP true [get_nets {reset_i}] +set_property KEEP true [get_nets {tx_aligned_o}] +set_property KEEP true [get_nets {tx_pi_phase_o[*]}] +set_property KEEP true [get_nets {tx_fifo_fill_pd_o[*]}] + +set_property MARK_DEBUG true [get_nets {reset_i}] +set_property MARK_DEBUG true [get_nets {tx_aligned_o}] +set_property MARK_DEBUG true [get_nets {tx_pi_phase_o[*]}] +set_property MARK_DEBUG true [get_nets {tx_fifo_fill_pd_o[*]}] \ No newline at end of file diff --git a/hub_test/constrs/hub_test.xdc b/hub_test/constrs/hub_test.xdc index e08938a..6029b47 100644 --- a/hub_test/constrs/hub_test.xdc +++ b/hub_test/constrs/hub_test.xdc @@ -75,3 +75,17 @@ set_false_path -to [get_pins {THE_RESET_HANDLER/async_sampler_reg[0]/D}] set_false_path -to [get_pins {generate_downlinks[*].THE_DOWNLINK/THE_MED_CONTROL/THE_?X_FSM/rst_n_refclk_*reg/CLR}] set_false_path -to [get_pins THE_UPLINK/THE_MED_CONTROL/THE_?X_FSM/rst_n_refclk_*reg/CLR] set_false_path -to [get_pins THE_UPLINK/THE_MED_CONTROL/reset_txi_*reg/PRE] + +# TX phase aligner +# False path constraints +# ---------------------------------------------------------------------------------------------------------------------- +# Synchronizers internal to tx_phase_aligner +set_false_path -to [get_pins -hier -filter {NAME =~ *tx_phase_aligner_i/*meta*/D}] + +# Latched with a done signal +set_false_path -to [get_pins -hier -filter {NAME =~ *tx_phase_aligner_i/cmp_fifo_fill_level_acc/phase_detector_o*/D}] + +# Reset fifo fill pd after changing value of phase_detector_max from FSM +set_false_path -from [get_pins -hier -filter {NAME =~ *tx_phase_aligner_i/cmp_tx_phase_aligner_fsm/*/C}] -to [get_pins -hier -filter {NAME =~ *tx_phase_aligner_i/cmp_fifo_fill_level_acc/phase_detector_acc_reg*/CE}] +set_false_path -from [get_pins -hier -filter {NAME =~ *tx_phase_aligner_i/cmp_tx_phase_aligner_fsm/*/C}] -to [get_pins -hier -filter {NAME =~ *tx_phase_aligner_i/cmp_fifo_fill_level_acc/hits_acc_reg*/CE}] +set_false_path -from [get_pins -hier -filter {NAME =~ *tx_phase_aligner_i/cmp_tx_phase_aligner_fsm/*/C}] -to [get_pins -hier -filter {NAME =~ *tx_phase_aligner_i/cmp_fifo_fill_level_acc/done_reg/D}] \ No newline at end of file diff --git a/hub_test/hub_test.xpr b/hub_test/hub_test.xpr index afc3254..08a8b56 100644 --- a/hub_test/hub_test.xpr +++ b/hub_test/hub_test.xpr @@ -67,14 +67,21 @@ - + - + + + + + + + + @@ -88,21 +95,42 @@ - + - + - + + + + + + + + + + + + + + + + + + + + + + @@ -163,6 +191,12 @@ + + + + + + @@ -199,6 +233,12 @@ + + + + + + @@ -463,87 +503,36 @@ - + - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - - + - - + - - + + + @@ -600,6 +589,13 @@ + + + + + + + diff --git a/hub_test/src/hub_test.vhd b/hub_test/src/hub_test.vhd index e8224db..93c687a 100644 --- a/hub_test/src/hub_test.vhd +++ b/hub_test/src/hub_test.vhd @@ -5,6 +5,9 @@ use ieee.numeric_std.all; library unisim; use unisim.vcomponents.all; +library xpm; +use xpm.vcomponents.all; + library work; use work.config.all; use work.trb_net_std.all; @@ -12,9 +15,6 @@ use work.trb_net16_hub_func.all; use work.version.all; entity hub_test is - generic ( - BYPASS_TXBUF : integer range 0 to 1 := 1 - ); port ( CLK_200_P : in std_logic; CLK_200_N : in std_logic; @@ -87,43 +87,6 @@ architecture behavioral of hub_test is ); end component; - component gtwizard_ultrascale_v1_7_8_gtwiz_buffbypass_tx is - generic ( - P_BUFFER_BYPASS_MODE : integer; - P_TOTAL_NUMBER_OF_CHANNELS : integer; - P_MASTER_CHANNEL_POINTER : integer - ); - port ( - gtwiz_buffbypass_tx_clk_in : in std_logic; - gtwiz_buffbypass_tx_reset_in : in std_logic; - gtwiz_buffbypass_tx_start_user_in : in std_logic; - gtwiz_buffbypass_tx_resetdone_in : in std_logic; - gtwiz_buffbypass_tx_done_out : out std_logic; - gtwiz_buffbypass_tx_error_out : out std_logic; - txphaligndone_in : in std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0); - txphinitdone_in : in std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0); - txdlysresetdone_in : in std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0); - txsyncout_in : in std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0); - txsyncdone_in : in std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0); - txphdlyreset_out : out std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0); - txphalign_out : out std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0); - txphalignen_out : out std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0); - txphdlypd_out : out std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0); - txphinit_out : out std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0); - txphovrden_out : out std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0); - txdlysreset_out : out std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0); - txdlybypass_out : out std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0); - txdlyen_out : out std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0); - txdlyovrden_out : out std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0); - txphdlytstclk_out : out std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0); - txdlyhold_out : out std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0); - txdlyupdown_out : out std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0); - txsyncmode_out : out std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0); - txsyncallin_out : out std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0); - txsyncin_out : out std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0) - ); - end component gtwizard_ultrascale_v1_7_8_gtwiz_buffbypass_tx; - signal clk_200_ibuf : std_logic; signal baseclk_100 : std_logic; signal mb_ext_resets_n : std_logic_vector(7 downto 0); @@ -148,17 +111,18 @@ architecture behavioral of hub_test is signal mgtrefclk_uplink_bufg : std_logic; signal mgtrefclk_uplink_bufg_half : std_logic; - signal downlink_usrclk : std_logic; - signal downlink_usrclk_double : std_logic; - signal downlink_usrclk_active : std_logic; - signal not_downlink_usrclk_active : std_logic; - signal initial_clear_timer : unsigned(27 downto 0) := (others => '0'); signal initial_clear_n : std_logic := '0'; + signal tx_aligned : std_logic_vector(INTERFACE_NUM - 2 downto 0); + constant DOWNLINK_ONES : std_logic_vector(INTERFACE_NUM - 2 downto 0) + := (others => '1'); + signal reset_from_vio : std_logic; signal reset_from_net : std_logic; + signal clear_in : std_logic; + signal send_reset_in : std_logic; signal send_reset_detect : std_logic; @@ -170,36 +134,6 @@ architecture behavioral of hub_test is signal med2int_i : med2int_array_t(0 to 10); signal int2med_i : int2med_array_t(0 to 10); - signal txoutclk : std_logic_vector(0 to INTERFACE_NUM - 2); - signal txprgdivresetdone : std_logic_vector(0 to INTERFACE_NUM - 2); - - signal txresetdone : std_logic_vector(0 to INTERFACE_NUM - 2); - - signal txdlybypass : std_logic_vector(INTERFACE_NUM - 2 downto 0); - signal txdlyen : std_logic_vector(INTERFACE_NUM - 2 downto 0); - signal txdlyhold : std_logic_vector(INTERFACE_NUM - 2 downto 0); - signal txdlyovrden : std_logic_vector(INTERFACE_NUM - 2 downto 0); - signal txdlysreset : std_logic_vector(INTERFACE_NUM - 2 downto 0); - signal txdlyupdown : std_logic_vector(INTERFACE_NUM - 2 downto 0); - signal txphalign : std_logic_vector(INTERFACE_NUM - 2 downto 0); - signal txphalignen : std_logic_vector(INTERFACE_NUM - 2 downto 0); - signal txphdlypd : std_logic_vector(INTERFACE_NUM - 2 downto 0); - signal txphdlyreset : std_logic_vector(INTERFACE_NUM - 2 downto 0); - signal txphdlytstclk : std_logic_vector(INTERFACE_NUM - 2 downto 0); - signal txphinit : std_logic_vector(INTERFACE_NUM - 2 downto 0); - signal txphovrden : std_logic_vector(INTERFACE_NUM - 2 downto 0); - signal txsyncallin : std_logic_vector(INTERFACE_NUM - 2 downto 0); - signal txsyncin : std_logic_vector(INTERFACE_NUM - 2 downto 0); - signal txsyncmode : std_logic_vector(INTERFACE_NUM - 2 downto 0); - signal txdlysresetdone : std_logic_vector(INTERFACE_NUM - 2 downto 0); - signal txphaligndone : std_logic_vector(INTERFACE_NUM - 2 downto 0); - signal txphinitdone : std_logic_vector(INTERFACE_NUM - 2 downto 0); - signal txsyncdone : std_logic_vector(INTERFACE_NUM - 2 downto 0); - signal txsyncout : std_logic_vector(INTERFACE_NUM - 2 downto 0); - signal buffbypass_tx_start_user : std_logic := '0'; - signal buffbypass_tx_done : std_logic; - signal buffbypass_tx_error : std_logic; - signal ctrlbus_rx_i : CTRLBUS_RX; signal bussci1_rx : CTRLBUS_RX; signal bussci2_rx : CTRLBUS_RX; @@ -334,31 +268,6 @@ begin ); not_sysclk_locked <= not sysclk_locked; - downlink_usrclk_active <= txprgdivresetdone(0); - not_downlink_usrclk_active <= not downlink_usrclk_active; - - THE_DOWNLINK_USRCLK_DOUBLE : BUFG_GT - port map ( - O => downlink_usrclk_double, - CE => '1', - CEMASK => '0', - CLR => not_downlink_usrclk_active, - CLRMASK => '0', - DIV => "000", - I => txoutclk(0) - ); - - THE_DOWNLINK_USRCLK : BUFG_GT - port map ( - O => downlink_usrclk, - CE => '1', - CEMASK => '0', - CLR => not_downlink_usrclk_active, - CLRMASK => '0', - DIV => "001", - I => txoutclk(0) - ); - THE_MGTREFCLK0_232 : IBUFDS_GTE3 generic map ( REFCLK_EN_TX_PATH => '0', @@ -446,13 +355,15 @@ begin trb_reset <= reset_from_net or (send_reset_detect and not send_reset_in); + clear_in <= '1' when reset_from_vio = '1' or tx_aligned /= DOWNLINK_ONES + else '0'; THE_RESET_HANDLER : entity work.trb_net_reset_handler generic map ( RESET_DELAY => x"FEEE" ) port map ( - CLEAR_IN => reset_from_vio, + CLEAR_IN => clear_in, CLEAR_N_IN => initial_clear_n, CLK_IN => sysclk_120, SYSCLK_IN => sysclk_120, @@ -470,12 +381,12 @@ begin IS_SYNC_SLAVE => c_YES, LINE_RATE_KBPS => 2000000, REFCLK_FREQ_HZ => 200000000, - USE_TXPROGDIV => 0, - BYPASS_TXBUF => 0 + SOFT_RESET_TX => 1 ) port map ( SYSCLK => sysclk_120, CLK_100 => baseclk_100, + RESET_ALL => '0', GTREFCLK => mgtrefclk_uplink, GTREFCLK_BUFG => mgtrefclk_uplink_bufg, RXOUTCLK => open, @@ -511,32 +422,50 @@ begin generate_downlinks: for linknum in 0 to INTERFACE_NUM - 2 generate + signal drpaddr : std_logic_vector(8 downto 0); + signal drpdi : std_logic_vector(15 downto 0); + signal drpen : std_logic; + signal drpwe : std_logic; + signal drpdo : std_logic_vector(15 downto 0); + signal drprdy : std_logic; + + signal txpippmen : std_logic; + signal txpippmovrden : std_logic; + signal txpippmpd : std_logic; + signal txpippmsel : std_logic; + signal txpippmstepsize : std_logic_vector(4 downto 0); + + signal txbufstatus : std_logic_vector(1 downto 0); + + signal txresetdone : std_logic; + signal not_txresetdone : std_logic; + signal reset_tx_phase_aligner : std_logic; begin THE_DOWNLINK : entity work.med_xcku_sfp_sync generic map ( IS_SYNC_SLAVE => c_NO, LINE_RATE_KBPS => 2400000, REFCLK_FREQ_HZ => 120000000, - USE_TXPROGDIV => 1, - BYPASS_TXBUF => BYPASS_TXBUF + SOFT_RESET_TX => 0 ) port map ( SYSCLK => sysclk_120, CLK_100 => baseclk_100, + RESET_ALL => not_sysclk_locked, GTREFCLK => mgtrefclk_downlink, GTREFCLK_BUFG => mgtrefclk_downlink_bufg, RXOUTCLK => open, - TXOUTCLK => txoutclk(linknum), - RXUSRCLK => downlink_usrclk, - RXUSRCLK_DOUBLE => downlink_usrclk_double, - TXUSRCLK => downlink_usrclk, - TXUSRCLK_DOUBLE => downlink_usrclk_double, - RXUSRCLK_ACTIVE => downlink_usrclk_active, - TXUSRCLK_ACTIVE => downlink_usrclk_active, + TXOUTCLK => open, + RXUSRCLK => sysclk_120, + RXUSRCLK_DOUBLE => sysclk_240, + TXUSRCLK => sysclk_120, + TXUSRCLK_DOUBLE => sysclk_240, + RXUSRCLK_ACTIVE => sysclk_locked, + TXUSRCLK_ACTIVE => sysclk_locked, RXPMARESETDONE => open, TXPMARESETDONE => open, RXRESETDONE => open, - TXRESETDONE => txresetdone(linknum), + TXRESETDONE => txresetdone, RESET => reset, CLEAR => clear, RXN => RXN(linknum), @@ -553,70 +482,69 @@ begin SD_TXDIS_OUT => mpod_d_txdis(linknum + 3), STAT_DEBUG => open, CTRL_DEBUG => (others => '0'), - TXPRGDIVRESETDONE => txprgdivresetdone(linknum), - TXDLYBYPASS => txdlybypass(linknum), - TXDLYEN => txdlyen(linknum), - TXDLYHOLD => txdlyhold(linknum), - TXDLYOVRDEN => txdlyovrden(linknum), - TXDLYSRESET => txdlysreset(linknum), - TXDLYUPDOWN => txdlyupdown(linknum), - TXPHALIGN => txphalign(linknum), - TXPHALIGNEN => txphalignen(linknum), - TXPHDLYPD => txphdlypd(linknum), - TXPHDLYRESET => txphdlyreset(linknum), - TXPHDLYTSTCLK => txphdlytstclk(linknum), - TXPHINIT => txphinit(linknum), - TXPHOVRDEN => txphovrden(linknum), - TXSYNCALLIN => txsyncallin(linknum), - TXSYNCIN => txsyncin(linknum), - TXSYNCMODE => txsyncmode(linknum), - TXDLYSRESETDONE => txdlysresetdone(linknum), - TXPHALIGNDONE => txphaligndone(linknum), - TXPHINITDONE => txphinitdone(linknum), - TXSYNCDONE => txsyncdone(linknum), - TXSYNCOUT => txsyncout(linknum) + DRPADDR => drpaddr, + DRPCLK => baseclk_100, + DRPDI => drpdi, + DRPEN => drpen, + DRPWE => drpwe, + DRPDO => drpdo, + DRPRDY => drprdy, + TXPIPPMEN => txpippmen, + TXPIPPMOVRDEN => txpippmovrden, + TXPIPPMPD => txpippmpd, + TXPIPPMSEL => txpippmsel, + TXPIPPMSTEPSIZE => txpippmstepsize, + TXBUFSTATUS => txbufstatus ); - end generate generate_downlinks; - generate_bypass_txbuf: - if BYPASS_TXBUF = 1 generate - begin - buffbypass_tx_i : gtwizard_ultrascale_v1_7_8_gtwiz_buffbypass_tx + not_txresetdone <= not txresetdone; + + xpm_cdc_async_rst_tx_phase_aligner : xpm_cdc_async_rst + generic map ( + DEST_SYNC_FF => 4, + INIT_SYNC_FF => 0, + RST_ACTIVE_HIGH => 1 + ) + port map ( + dest_arst => reset_tx_phase_aligner, + dest_clk => baseclk_100, + src_arst => not_txresetdone + ); + + tx_phase_aligner_i : entity work.tx_phase_aligner generic map ( - P_BUFFER_BYPASS_MODE => 0, - P_TOTAL_NUMBER_OF_CHANNELS => INTERFACE_NUM - 1, - P_MASTER_CHANNEL_POINTER => 0 + g_DRP_NPORT_CTRL => true, + g_DRP_ADDR_TXPI_PPM_CFG => "010011010" ) port map ( - gtwiz_buffbypass_tx_clk_in => sysclk_120, - gtwiz_buffbypass_tx_reset_in => not_sysclk_locked, - gtwiz_buffbypass_tx_start_user_in => buffbypass_tx_start_user, - gtwiz_buffbypass_tx_resetdone_in => txresetdone(0), -- TODO: OR of all channels? - gtwiz_buffbypass_tx_done_out => buffbypass_tx_done, - gtwiz_buffbypass_tx_error_out => buffbypass_tx_error, - txphaligndone_in => txphaligndone, - txphinitdone_in => txphinitdone, - txdlysresetdone_in => txdlysresetdone, - txsyncout_in => txsyncout, - txsyncdone_in => txsyncdone, - txphdlyreset_out => txphdlyreset, - txphalign_out => txphalign, - txphalignen_out => txphalignen, - txphdlypd_out => txphdlypd, - txphinit_out => txphinit, - txphovrden_out => txphovrden, - txdlysreset_out => txdlysreset, - txdlybypass_out => txdlybypass, - txdlyen_out => txdlyen, - txdlyovrden_out => txdlyovrden, - txphdlytstclk_out => txphdlytstclk, - txdlyhold_out => txdlyhold, - txdlyupdown_out => txdlyupdown, - txsyncmode_out => txsyncmode, - txsyncallin_out => txsyncallin, - txsyncin_out => txsyncin + clk_sys_i => baseclk_100, + reset_i => reset_tx_phase_aligner, + tx_aligned_o => tx_aligned(linknum), + tx_pi_phase_calib_i => "0000000", -- (FINE_ALIGNMENT) + tx_ui_align_calib_i => '0', -- (FINE_ALIGNMENT) + tx_fifo_fill_pd_max_i => x"00040000", + tx_fine_realign_i => '0', + ps_strobe_i => '0', + ps_inc_ndec_i => '0', + ps_phase_step_i => "0000", + ps_done_o => open, + tx_pi_phase_o => open, + tx_fifo_fill_pd_o => open, + clk_txusr_i => sysclk_120, + tx_fifo_fill_level_i => txbufstatus(0), + txpippmen_o => txpippmen, + txpippmovrden_o => txpippmovrden, + txpippmsel_o => txpippmsel, + txpippmpd_o => txpippmpd, + txpippmstepsize_o => txpippmstepsize, + drpaddr_o => drpaddr, + drpen_o => drpen, + drpdi_o => drpdi, + drprdy_i => drprdy, + drpdo_i => drpdo, + drpwe_o => drpwe ); - end generate generate_bypass_txbuf; + end generate generate_downlinks; -- Create a 100 ns test pulse for debugging of microslice timing process (sysclk_240) is -- 2.43.0