From b912c0d894f4d8db57fa99c2ae0da8c657ffd341 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Thu, 17 Aug 2017 16:05:01 +0200 Subject: [PATCH] Fix IPU handler - remove Latch --- special/handler_data.vhd | 2 +- special/handler_ipu.vhd | 6 ++++-- special/tb_handler_lvl1.vhd | 34 ++++++++++++++++++++++++---------- 3 files changed, 29 insertions(+), 13 deletions(-) diff --git a/special/handler_data.vhd b/special/handler_data.vhd index 63b838b..13a9b21 100644 --- a/special/handler_data.vhd +++ b/special/handler_data.vhd @@ -379,7 +379,7 @@ begin <= not (or_all(data_buffer_almost_full) or or_all(length_buffer_almost_full) or header_buffer_almost_full); elsif or_all(got_busy_release(DATA_INTERFACE_NUMBER-1 downto 0)) = '1' and - (or_all(data_buffer_almost_full) or or_all(length_buffer_almost_full) or header_buffer_almost_full) = '0' then + (or_all(data_buffer_almost_full) or or_all(length_buffer_almost_full) or header_buffer_almost_full) = '0' and LVL1_TRG_DATA_VALID_IN = '1' then got_busy_release(DATA_INTERFACE_NUMBER) <= '1'; end if; end if; diff --git a/special/handler_ipu.vhd b/special/handler_ipu.vhd index b48697a..62ddf6e 100644 --- a/special/handler_ipu.vhd +++ b/special/handler_ipu.vhd @@ -130,6 +130,7 @@ begin next_first_fifo_read <= '0'; next_dat_fifo_number <= dat_fifo_number; next_suppress_output <= suppress_output; + next_hdr_data_waiting <= hdr_data_waiting; case current_state is when IDLE => @@ -427,8 +428,9 @@ assert ( STATUS_OUT(13) <= error_missing; STATUS_OUT(14) <= error_sync; STATUS_OUT(15) <= error_not_configured; - STATUS_OUT(23 downto 16) <= DAT_DATA_IN(7 downto 0); - STATUS_OUT(31 downto 24) <= (others => '0'); + STATUS_OUT(23 downto 16) <= DAT_HDR_DATA_IN(7 downto 0); + STATUS_OUT(24) <= hdr_data_waiting; + STATUS_OUT(31 downto 25) <= (others => '0'); end architecture; diff --git a/special/tb_handler_lvl1.vhd b/special/tb_handler_lvl1.vhd index 7060d1d..158affb 100755 --- a/special/tb_handler_lvl1.vhd +++ b/special/tb_handler_lvl1.vhd @@ -17,6 +17,8 @@ ARCHITECTURE behavior OF testbench IS ); PORT( RESET : IN std_logic; + RESET_FLAGS_IN : in std_logic; + RESET_STATS_IN : in std_logic; CLOCK : IN std_logic; LVL1_TIMING_TRG_IN : IN std_logic; LVL1_PSEUDO_TMG_TRG_IN : IN std_logic; @@ -25,7 +27,7 @@ ARCHITECTURE behavior OF testbench IS LVL1_TRG_NUMBER_IN : IN std_logic_vector(15 downto 0); LVL1_TRG_CODE_IN : IN std_logic_vector(7 downto 0); LVL1_TRG_INFORMATION_IN : IN std_logic_vector(23 downto 0); - LVL1_INT_TRG_RESET_IN : IN std_logic; +-- LVL1_INT_TRG_RESET_IN : IN std_logic; LVL1_INT_TRG_LOAD_IN : IN std_logic; LVL1_INT_TRG_COUNTER_IN : IN std_logic_vector(15 downto 0); LVL1_ERROR_PATTERN_IN : IN std_logic_vector(31 downto 0); @@ -39,7 +41,7 @@ ARCHITECTURE behavior OF testbench IS LVL1_VALID_TIMING_TRG_OUT : OUT std_logic; LVL1_VALID_NOTIMING_TRG_OUT : OUT std_logic; LVL1_INVALID_TRG_OUT : OUT std_logic; - STATUS_OUT : OUT std_logic_vector(31 downto 0); + STATUS_OUT : OUT std_logic_vector(63 downto 0); DEBUG_OUT : OUT std_logic_vector(15 downto 0) ); END COMPONENT; @@ -56,7 +58,7 @@ ARCHITECTURE behavior OF testbench IS SIGNAL LVL1_ERROR_PATTERN_OUT : std_logic_vector(31 downto 0); SIGNAL LVL1_TRG_RELEASE_OUT : std_logic; SIGNAL LVL1_INT_TRG_NUMBER_OUT : std_logic_vector(15 downto 0); - SIGNAL LVL1_INT_TRG_RESET_IN : std_logic; +-- SIGNAL LVL1_INT_TRG_RESET_IN : std_logic; SIGNAL LVL1_INT_TRG_LOAD_IN : std_logic; SIGNAL LVL1_INT_TRG_COUNTER_IN : std_logic_vector(15 downto 0); SIGNAL LVL1_TRG_DATA_VALID_OUT : std_logic; @@ -65,7 +67,7 @@ ARCHITECTURE behavior OF testbench IS SIGNAL LVL1_INVALID_TRG_OUT : std_logic; SIGNAL LVL1_ERROR_PATTERN_IN : std_logic_vector(31 downto 0); SIGNAL LVL1_TRG_RELEASE_IN : std_logic; - SIGNAL STATUS_OUT : std_logic_vector(31 downto 0); + SIGNAL STATUS_OUT : std_logic_vector(63 downto 0); SIGNAL TRG_ENABLE_IN : std_logic; SIGNAL TRG_INVERT_IN : std_logic; SIGNAL DEBUG_OUT : std_logic_vector(15 downto 0); @@ -74,11 +76,13 @@ BEGIN -- Please check and add your generic clause manually uut: handler_lvl1 - GENERIC MAP( + generic map( TIMING_TRIGGER_RAW => 1 ) - PORT MAP( + port map( RESET => RESET, + RESET_FLAGS_IN => '0', + RESET_STATS_IN => '0', CLOCK => CLOCK, LVL1_TIMING_TRG_IN => LVL1_TIMING_TRG_IN, LVL1_PSEUDO_TMG_TRG_IN => LVL1_PSEUDO_TMG_TRG_IN, @@ -90,7 +94,7 @@ BEGIN LVL1_ERROR_PATTERN_OUT => LVL1_ERROR_PATTERN_OUT, LVL1_TRG_RELEASE_OUT => LVL1_TRG_RELEASE_OUT, LVL1_INT_TRG_NUMBER_OUT => LVL1_INT_TRG_NUMBER_OUT, - LVL1_INT_TRG_RESET_IN => LVL1_INT_TRG_RESET_IN, +-- LVL1_INT_TRG_RESET_IN => LVL1_INT_TRG_RESET_IN, LVL1_INT_TRG_LOAD_IN => LVL1_INT_TRG_LOAD_IN, LVL1_INT_TRG_COUNTER_IN => LVL1_INT_TRG_COUNTER_IN, LVL1_TRG_DATA_VALID_OUT => LVL1_TRG_DATA_VALID_OUT, @@ -124,7 +128,7 @@ begin lvl1_trg_number_in <= x"0000"; lvl1_trg_code_in <= x"00"; lvl1_trg_information_in <= x"000000"; - lvl1_int_trg_reset_in <= '0'; +-- lvl1_int_trg_reset_in <= '0'; lvl1_int_trg_load_in <= '0'; lvl1_int_trg_counter_in <= x"0000"; lvl1_error_pattern_in <= x"0000_0000"; @@ -158,8 +162,13 @@ begin -- receive one normal timing trigger wait for 3 ns; lvl1_timing_trg_in <= '1'; - wait for 111 ns; + wait for 100 ns; lvl1_timing_trg_in <= '0'; + wait for 10 ns; + lvl1_timing_trg_in <= '1'; + wait for 200 ns; + lvl1_timing_trg_in <= '0'; + wait for 1000 ns; -- LVL1 packet is there @@ -194,8 +203,13 @@ begin -- receive one normal timing trigger wait for 3 ns; lvl1_timing_trg_in <= '1'; - wait for 111 ns; + wait for 100 ns; lvl1_timing_trg_in <= '0'; + wait for 10 ns; + lvl1_timing_trg_in <= '1'; + wait for 200 ns; + lvl1_timing_trg_in <= '0'; + wait for 1000 ns; -- LVL1 packet is there -- 2.43.0