From b97ee104223fe90b7e9fbc3924a6fe05071425df Mon Sep 17 00:00:00 2001 From: palka Date: Thu, 21 Feb 2008 15:07:41 +0000 Subject: [PATCH] iversion, new connection between tdc_int and etrax_int sss: ---------------------------------------------------------------------- --- trb_v2b_fpga.vhd | 28 +++++++++++++++++++++++----- 1 file changed, 23 insertions(+), 5 deletions(-) diff --git a/trb_v2b_fpga.vhd b/trb_v2b_fpga.vhd index a581d1a..d8ca781 100644 --- a/trb_v2b_fpga.vhd +++ b/trb_v2b_fpga.vhd @@ -382,6 +382,7 @@ architecture trb_v2b_fpga of trb_v2b_fpga is TDC_REGISTER_02 : out std_logic_vector(31 downto 0); TDC_REGISTER_03 : out std_logic_vector(31 downto 0); TDC_REGISTER_04 : out std_logic_vector(31 downto 0); + TDC_REGISTER_05 : in std_logic_vector(31 downto 0); BUNCH_RESET : out std_logic; EVENT_RESET : out std_logic; READ_ADRESS_END_UP : out std_logic; --here @@ -428,6 +429,7 @@ architecture trb_v2b_fpga of trb_v2b_fpga is FPGA_REGISTER_0B : in std_logic_vector(31 downto 0); FPGA_REGISTER_0C : in std_logic_vector(31 downto 0); FPGA_REGISTER_0D : in std_logic_vector(31 downto 0); + FPGA_REGISTER_0E : in std_logic_vector(31 downto 0); EXTERNAL_RESET : out std_logic; LVL2_VALID : in std_logic ); @@ -642,7 +644,8 @@ architecture trb_v2b_fpga of trb_v2b_fpga is signal fpga_register_0b_i : std_logic_vector(31 downto 0); signal fpga_register_0c_i : std_logic_vector(31 downto 0); signal fpga_register_0d_i : std_logic_vector(31 downto 0); - + signal fpga_register_0e_i : std_logic_vector(31 downto 0); + signal fpga_register_19_i : std_logic_vector(31 downto 0); signal fpga_register_20_i : std_logic_vector(31 downto 0); @@ -666,6 +669,9 @@ architecture trb_v2b_fpga of trb_v2b_fpga is signal tdc_register_02_i : std_logic_vector(31 downto 0); signal tdc_register_03_i : std_logic_vector(31 downto 0); signal tdc_register_04_i : std_logic_vector(31 downto 0); + signal tdc_register_05_i : std_logic_vector(31 downto 0); + + signal tdc_control_register_e : std_logic_vector(31 downto 0); signal simulation_00 : std_logic_vector(3 downto 0); signal bunch_reset_i : std_logic; @@ -728,7 +734,9 @@ architecture trb_v2b_fpga of trb_v2b_fpga is signal self_token :std_logic; signal self_data_valid : std_logic; signal external_reset : std_logic; - signal generator_trigger : std_logic; + signal generator_trigger_1 : std_logic; + signal generator_trigger_2 : std_logic; + signal generator_trigger : std_logic; signal check_pulse : std_logic; signal check_counter : std_logic_vector(16 downto 0); --api @@ -1740,6 +1748,7 @@ begin TDC_REGISTER_02 => tdc_register_02_i, TDC_REGISTER_03 => tdc_register_03_i, TDC_REGISTER_04 => tdc_register_04_i, + TDC_REGISTER_05 => fpga_register_0e_i, BUNCH_RESET => bunch_reset_i, EVENT_RESET => event_reset_i, READ_ADRESS_END_UP => trb_ack_lvl2_i, @@ -1750,7 +1759,7 @@ begin TRIGGER_WITH_GEN => not_hades_trigger--trigger_for_test_signal or generator_trigger ); ADO_TTL(42 downto 35) <= tdc_register_01_i(26 downto 19); - not_hades_trigger <= trigger_for_test_signal or generator_trigger; + not_hades_trigger <= trigger_for_test_signal or generator_trigger_1 or generator_trigger_2; end_of_transfer <= not tdc_data_valid_i; LVL2_BUSY_END_PULSER : edge_to_pulse port map ( @@ -1927,6 +1936,7 @@ begin FPGA_REGISTER_0B => fpga_register_0b_i, FPGA_REGISTER_0C => fpga_register_0c_i, FPGA_REGISTER_0D => fpga_register_0d_i, + FPGA_REGISTER_0E => fpga_register_0e_i, EXTERNAL_RESET => external_reset, LVL2_VALID => '0'--lvl2_trigger_code_i(3) ); @@ -2232,12 +2242,20 @@ begin UP => scaler_pulse(7), CLK => CLK, CLR => external_reset_i); - TRIGG_WITHOUT_HAD: edge_to_pulse + TRIGG_WITHOUT_HAD_1: edge_to_pulse port map ( clock => CLK, en_clk => '1', signal_in => ADO_TTL(0), - pulse => generator_trigger); + pulse => generator_trigger_1); + ADO_TTL(16) <= 'Z'; +-- TRIGG_WITHOUT_HAD_2: edge_to_pulse +-- port map ( +-- clock => CLK, +-- en_clk => '1', +-- signal_in => ADO_TTL(16), +-- pulse => generator_trigger_2); + generator_trigger_2 <= '0'; MAKE_LONG_LVL2_ACK: process (CLK, external_reset_i) begin -- process MAKE_LONG_ACK if rising_edge(CLK) then -- rising clock edge -- 2.43.0