From ba860bdf8523f83b5b08abd062842081772232ad Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Mon, 3 Jun 2024 15:31:49 +0200 Subject: [PATCH] add first ADC files --- adc/config.vhd | 16 +- adc/config_compile_frankfurt.pl | 6 +- adc/cores/adc_pll/adc_pll.fdc | 2 + adc/cores/adc_pll/adc_pll.lpc | 93 ++ adc/cores/adc_pll/adc_pll.sbx | 430 ++++++ adc/cores/adc_pll/adc_pll.vhd | 81 ++ adc/cores/fifo_cdt_70x16/fifo_cdt_70x16.cst | 3 + adc/cores/fifo_cdt_70x16/fifo_cdt_70x16.fdc | 2 + adc/cores/fifo_cdt_70x16/fifo_cdt_70x16.lpc | 53 + adc/cores/fifo_cdt_70x16/fifo_cdt_70x16.sbx | 264 ++++ adc/cores/fifo_cdt_70x16/fifo_cdt_70x16.vhd | 713 ++++++++++ adc/cores/input_4ch/input_4ch.fdc | 2 + adc/cores/input_4ch/input_4ch.lpc | 66 + adc/cores/input_4ch/input_4ch.sbx | 322 +++++ adc/cores/input_4ch/input_4ch.vhd | 1332 +++++++++++++++++++ adc/cores/input_4ch/input_4ch_edited.vhd | 1327 ++++++++++++++++++ adc/cores/mulaccsub3/mulaccsub3.cst | 3 + adc/cores/mulaccsub3/mulaccsub3.fdc | 2 + adc/cores/mulaccsub3/mulaccsub3.lpc | 67 + adc/cores/mulaccsub3/mulaccsub3.sbx | 304 +++++ adc/cores/mulaccsub3/mulaccsub3.vhd | 942 +++++++++++++ adc/par.p2t | 2 +- adc/source/adc_addon.vhd | 287 ++++ adc/source/adc_input.vhd | 172 +++ adc/source/adc_package.vhd | 45 + adc/source/adc_processor.vhd | 706 ++++++++++ adc/trb5sc_adc.lpf | 7 + adc/trb5sc_adc.prj | 20 +- adc/trb5sc_adc.vhd | 120 +- pinout/trb5sc_adc.lpf | 86 +- 30 files changed, 7375 insertions(+), 100 deletions(-) create mode 100644 adc/cores/adc_pll/adc_pll.fdc create mode 100644 adc/cores/adc_pll/adc_pll.lpc create mode 100644 adc/cores/adc_pll/adc_pll.sbx create mode 100644 adc/cores/adc_pll/adc_pll.vhd create mode 100644 adc/cores/fifo_cdt_70x16/fifo_cdt_70x16.cst create mode 100644 adc/cores/fifo_cdt_70x16/fifo_cdt_70x16.fdc create mode 100644 adc/cores/fifo_cdt_70x16/fifo_cdt_70x16.lpc create mode 100644 adc/cores/fifo_cdt_70x16/fifo_cdt_70x16.sbx create mode 100644 adc/cores/fifo_cdt_70x16/fifo_cdt_70x16.vhd create mode 100644 adc/cores/input_4ch/input_4ch.fdc create mode 100644 adc/cores/input_4ch/input_4ch.lpc create mode 100644 adc/cores/input_4ch/input_4ch.sbx create mode 100644 adc/cores/input_4ch/input_4ch.vhd create mode 100644 adc/cores/input_4ch/input_4ch_edited.vhd create mode 100644 adc/cores/mulaccsub3/mulaccsub3.cst create mode 100644 adc/cores/mulaccsub3/mulaccsub3.fdc create mode 100644 adc/cores/mulaccsub3/mulaccsub3.lpc create mode 100644 adc/cores/mulaccsub3/mulaccsub3.sbx create mode 100644 adc/cores/mulaccsub3/mulaccsub3.vhd create mode 100644 adc/source/adc_addon.vhd create mode 100644 adc/source/adc_input.vhd create mode 100644 adc/source/adc_package.vhd create mode 100644 adc/source/adc_processor.vhd diff --git a/adc/config.vhd b/adc/config.vhd index 4f233b9..d5183f8 100644 --- a/adc/config.vhd +++ b/adc/config.vhd @@ -35,8 +35,8 @@ package config is -- -- 14: Debug - single fine time and the ROM addresses for the two transitions -- -- 15: Debug - complete carry chain dump - constant EVENT_BUFFER_SIZE : integer range 9 to 15 := 13; -- size of the event buffer, 2**N - constant EVENT_MAX_SIZE : integer := 2000; --maximum event size. Must not exceed EVENT_BUFFER_SIZE/2 + constant EVENT_BUFFER_SIZE : integer range 9 to 15 := 9; -- size of the event buffer, 2**N + constant EVENT_MAX_SIZE : integer := 200; --maximum event size. Must not exceed EVENT_BUFFER_SIZE/2 constant USE_GBE : integer := c_NO; --Runs with 120 MHz instead of 100 MHz @@ -50,17 +50,17 @@ package config is constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"86"; constant INCLUDE_UART : integer := c_NO; - constant INCLUDE_SPI : integer := c_NO; + constant INCLUDE_SPI : integer := c_YES; constant INCLUDE_ADC : integer := c_YES; - constant INCLUDE_I2C : integer := c_YES; + constant INCLUDE_I2C : integer := c_NO; constant INCLUDE_DEBUG_INTERFACE: integer := c_NO; --input monitor and trigger generation logic - constant INCLUDE_TRIGGER_LOGIC : integer := c_NO; - constant INCLUDE_STATISTICS : integer := c_NO; - constant TRIG_GEN_INPUT_NUM : integer := 32; + constant INCLUDE_TRIGGER_LOGIC : integer := c_YES; + constant INCLUDE_STATISTICS : integer := c_YES; + constant TRIG_GEN_INPUT_NUM : integer := 16; constant TRIG_GEN_OUTPUT_NUM : integer := 4; - constant MONITOR_INPUT_NUM : integer := 32; + constant MONITOR_INPUT_NUM : integer := 16; ------------------------------------------------------------------------------ --End of design configuration diff --git a/adc/config_compile_frankfurt.pl b/adc/config_compile_frankfurt.pl index 1c3992f..35b89c8 100644 --- a/adc/config_compile_frankfurt.pl +++ b/adc/config_compile_frankfurt.pl @@ -4,14 +4,14 @@ Package => 'CABGA756', Speedgrade => '8', -TOPNAME => "trb5sc_mimosis", +TOPNAME => "trb5sc_adc", lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; lm_license_file_for_par => "1702\@jspc29", lattice_path => '/d/jspc29/lattice/diamond/3.12', -synplify_path => '/d/jspc29/lattice/synplify/S-2021.09-SP2/', +synplify_path => '/d/jspc29/lattice/synplify/T-2022.09-SP2/', nodelist_file => '../nodelist_frankfurt.txt', -pinout_file => 'trb5sc_hdmi', +pinout_file => 'trb5sc_adc', par_options => '../par.p2t', diff --git a/adc/cores/adc_pll/adc_pll.fdc b/adc/cores/adc_pll/adc_pll.fdc new file mode 100644 index 0000000..6fbcac9 --- /dev/null +++ b/adc/cores/adc_pll/adc_pll.fdc @@ -0,0 +1,2 @@ +###==== Start Configuration + diff --git a/adc/cores/adc_pll/adc_pll.lpc b/adc/cores/adc_pll/adc_pll.lpc new file mode 100644 index 0000000..2d7a1b8 --- /dev/null +++ b/adc/cores/adc_pll/adc_pll.lpc @@ -0,0 +1,93 @@ +[Device] +Family=ecp5um +PartType=LFE5UM-85F +PartName=LFE5UM-85F-8BG756C +SpeedGrade=8 +Package=CABGA756 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PLL +CoreRevision=5.8 +ModuleName=adc_pll +SourceFormat=vhdl +ParameterFileVersion=1.0 +Date=04/30/2024 +Time=13:48:45 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +CLKI_FREQ=200 +CLKI_DIV=4 +ENABLE_HBW=DISABLED +REFERENCE=0 +IOBUF=LVDS +CLKOP_FREQ=350 +CLKOP_TOL=0.0 +CLKOP_DIV=2 +CLKOP_ACTUAL_FREQ=350.000000 +CLKOP_MUXA=DISABLED +CLKOS_Enable=ENABLED +CLKOS_FREQ=50 +CLKOS_TOL=0.0 +CLKOS_DIV=14 +CLKOS_ACTUAL_FREQ=50.000000 +CLKOS_MUXB=DISABLED +CLKOS2_Enable=ENABLED +CLKOS2_FREQ=100.00 +CLKOS2_TOL=0.0 +CLKOS2_DIV=1 +CLKOS2_ACTUAL_FREQ=200.000000 +CLKOS2_MUXC=ENABLED +CLKOS3_Enable=DISABLED +CLKOS3_FREQ=100.00 +CLKOS3_TOL=0.0 +CLKOS3_DIV=1 +CLKOS3_ACTUAL_FREQ= +CLKOS3_MUXD=DISABLED +FEEDBK_PATH=CLKOP +CLKFB_DIV=7 +FRACN_ENABLE=DISABLED +FRACN_DIV= +VCO_RATE=700.000 +PLL_BW=6.139 +CLKOP_DPHASE=0 +CLKOP_APHASE=0.00 +CLKOP_TRIM_POL=Rising +CLKOP_TRIM_DELAY=0 +CLKOS_DPHASE=0 +CLKOS_APHASE=0.00 +CLKOS_TRIM_POL=Rising +CLKOS_TRIM_DELAY=0 +CLKOS2_DPHASE=0 +CLKOS2_APHASE=0.00 +CLKOS2_TRIM_POL=Rising +CLKOS2_TRIM_DELAY=0 +CLKOS3_DPHASE=0 +CLKOS3_APHASE=0.00 +CLKOS3_TRIM_POL=Rising +CLKOS3_TRIM_DELAY=0 +CLKSEL_ENA=DISABLED +DPHASE_SOURCE=STATIC +ENABLE_CLKOP=DISABLED +ENABLE_CLKOS=DISABLED +ENABLE_CLKOS2=DISABLED +ENABLE_CLKOS3=DISABLED +STDBY_ENABLE=DISABLED +PLLRST_ENA=DISABLED +PLL_LOCK_MODE=DISABLED +PLL_LOCK_STK=DISABLED +PLL_USE_SMI=DISABLED + +[Command] +cmd_line= -w -n adc_pll -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 200 -fclkop 350 -fclkop_tol 0.0 -fclkos 50 -fclkos_tol 0.0 -phases 0 -bypass_divs2 -phase_cntl STATIC -fb_mode 1 diff --git a/adc/cores/adc_pll/adc_pll.sbx b/adc/cores/adc_pll/adc_pll.sbx new file mode 100644 index 0000000..0a9a887 --- /dev/null +++ b/adc/cores/adc_pll/adc_pll.sbx @@ -0,0 +1,430 @@ + + + + Lattice Semiconductor Corporation + LEGACY + PLL + 5.8 + + + Diamond_Simulation + simulation + + ./adc_pll.vhd + vhdlSource + + + + Diamond_Synthesis + synthesis + + ./adc_pll.vhd + vhdlSource + + + + + + Configuration + none + ${sbp_path}/generate_core.tcl + CONFIG + + + Generation + none + ${sbp_path}/${instance}/generate_core.tcl + GENERATE + + + + + + + + LFE5UM-85F-8BG756C + synplify + 2024-04-30.10:51:46 AM + 2024-04-30.01:48:49 PM + 3.12.1.454 + VHDL + + false + false + false + false + false + false + false + false + false + false + LPM + PRIMARY + PRIMARY + false + false + + + + + + Family + ecp5um + + + OperatingCondition + COM + + + Package + CABGA756 + + + PartName + LFE5UM-85F-8BG756C + + + PartType + LFE5UM-85F + + + SpeedGrade + 8 + + + Status + P + + + + CoreName + PLL + + + CoreRevision + 5.8 + + + CoreStatus + Demo + + + CoreType + LPM + + + Date + 04/30/2024 + + + ModuleName + adc_pll + + + ParameterFileVersion + 1.0 + + + SourceFormat + vhdl + + + Time + 13:48:45 + + + VendorName + Lattice Semiconductor Corporation + + + + CLKFB_DIV + 7 + + + CLKI_DIV + 4 + + + CLKI_FREQ + 200 + + + CLKOP_ACTUAL_FREQ + 350.000000 + + + CLKOP_APHASE + 0.00 + + + CLKOP_DIV + 2 + + + CLKOP_DPHASE + 0 + + + CLKOP_FREQ + 350 + + + CLKOP_MUXA + DISABLED + + + CLKOP_TOL + 0.0 + + + CLKOP_TRIM_DELAY + 0 + + + CLKOP_TRIM_POL + Rising + + + CLKOS2_ACTUAL_FREQ + 200.000000 + + + CLKOS2_APHASE + 0.00 + + + CLKOS2_DIV + 1 + + + CLKOS2_DPHASE + 0 + + + CLKOS2_Enable + ENABLED + + + CLKOS2_FREQ + 100.00 + + + CLKOS2_MUXC + ENABLED + + + CLKOS2_TOL + 0.0 + + + CLKOS2_TRIM_DELAY + 0 + + + CLKOS2_TRIM_POL + Rising + + + CLKOS3_ACTUAL_FREQ + + + + CLKOS3_APHASE + 0.00 + + + CLKOS3_DIV + 1 + + + CLKOS3_DPHASE + 0 + + + CLKOS3_Enable + DISABLED + + + CLKOS3_FREQ + 100.00 + + + CLKOS3_MUXD + DISABLED + + + CLKOS3_TOL + 0.0 + + + CLKOS3_TRIM_DELAY + 0 + + + CLKOS3_TRIM_POL + Rising + + + CLKOS_ACTUAL_FREQ + 50.000000 + + + CLKOS_APHASE + 0.00 + + + CLKOS_DIV + 14 + + + CLKOS_DPHASE + 0 + + + CLKOS_Enable + ENABLED + + + CLKOS_FREQ + 50 + + + CLKOS_MUXB + DISABLED + + + CLKOS_TOL + 0.0 + + + CLKOS_TRIM_DELAY + 0 + + + CLKOS_TRIM_POL + Rising + + + CLKSEL_ENA + DISABLED + + + DPHASE_SOURCE + STATIC + + + Destination + Synplicity + + + EDIF + 1 + + + ENABLE_CLKOP + DISABLED + + + ENABLE_CLKOS + DISABLED + + + ENABLE_CLKOS2 + DISABLED + + + ENABLE_CLKOS3 + DISABLED + + + ENABLE_HBW + DISABLED + + + Expression + BusA(0 to 7) + + + FEEDBK_PATH + CLKOP + + + FRACN_DIV + + + + FRACN_ENABLE + DISABLED + + + IO + 0 + + + IOBUF + LVDS + + + Order + Big Endian [MSB:LSB] + + + PLLRST_ENA + DISABLED + + + PLL_BW + 6.139 + + + PLL_LOCK_MODE + DISABLED + + + PLL_LOCK_STK + DISABLED + + + PLL_USE_SMI + DISABLED + + + REFERENCE + 0 + + + STDBY_ENABLE + DISABLED + + + VCO_RATE + 700.000 + + + VHDL + 1 + + + Verilog + 0 + + + + cmd_line + -w -n adc_pll -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 200 -fclkop 350 -fclkop_tol 0.0 -fclkos 50 -fclkos_tol 0.0 -phases 0 -bypass_divs2 -phase_cntl STATIC -fb_mode 1 + + + + + + + LATTICE + LOCAL + adc_pll + 1.0 + + + + diff --git a/adc/cores/adc_pll/adc_pll.vhd b/adc/cores/adc_pll/adc_pll.vhd new file mode 100644 index 0000000..0ffcaa4 --- /dev/null +++ b/adc/cores/adc_pll/adc_pll.vhd @@ -0,0 +1,81 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 +-- Module Version: 5.7 +--/d/jspc29/lattice/diamond/3.12/ispfpga/bin/lin64/scuba -w -n adc_pll -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 200 -fclkop 350 -fclkop_tol 0.0 -fclkos 50 -fclkos_tol 0.0 -phases 0 -bypass_divs2 -phase_cntl STATIC -fb_mode 1 -fdc /local/trb/git/trb5sc/adc/cores/adc_pll/adc_pll.fdc + +-- Tue Apr 30 13:48:49 2024 + +library IEEE; +use IEEE.std_logic_1164.all; +library ecp5um; +use ecp5um.components.all; + +entity adc_pll is + port ( + CLKI: in std_logic; + CLKOP: out std_logic; + CLKOS: out std_logic; + CLKOS2: out std_logic); +end adc_pll; + +architecture Structure of adc_pll is + + -- internal signal declarations + signal REFCLK: std_logic; + signal LOCK: std_logic; + signal CLKOS2_t: std_logic; + signal CLKOS_t: std_logic; + signal CLKOP_t: std_logic; + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + + attribute FREQUENCY_PIN_CLKOS2 : string; + attribute FREQUENCY_PIN_CLKOS : string; + attribute FREQUENCY_PIN_CLKOP : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute ICP_CURRENT : string; + attribute LPF_RESISTOR : string; + attribute FREQUENCY_PIN_CLKOS2 of PLLInst_0 : label is "200.000000"; + attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "50.000000"; + attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "350.000000"; + attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000"; + attribute ICP_CURRENT of PLLInst_0 : label is "14"; + attribute LPF_RESISTOR of PLLInst_0 : label is "8"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + PLLInst_0: EHXPLLL + generic map (PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED", + STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED", + CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 0, CLKOS2_FPHASE=> 0, + CLKOS2_CPHASE=> 0, CLKOS_FPHASE=> 0, CLKOS_CPHASE=> 13, + CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 1, PLL_LOCK_MODE=> 0, + CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "FALLING", + CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "FALLING", + OUTDIVIDER_MUXD=> "DIVD", CLKOS3_ENABLE=> "DISABLED", + OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "ENABLED", + OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "ENABLED", + OUTDIVIDER_MUXA=> "DIVA", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 1, + CLKOS2_DIV=> 1, CLKOS_DIV=> 14, CLKOP_DIV=> 2, CLKFB_DIV=> 7, + CLKI_DIV=> 4, FEEDBK_PATH=> "CLKOP") + port map (CLKI=>CLKI, CLKFB=>CLKOP_t, PHASESEL1=>scuba_vlo, + PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo, + PHASESTEP=>scuba_vlo, PHASELOADREG=>scuba_vlo, + STDBY=>scuba_vlo, PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo, + ENCLKOP=>scuba_vlo, ENCLKOS=>scuba_vlo, ENCLKOS2=>scuba_vlo, + ENCLKOS3=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t, + CLKOS2=>CLKOS2_t, CLKOS3=>open, LOCK=>LOCK, INTLOCK=>open, + REFCLK=>REFCLK, CLKINTFB=>open); + + CLKOS2 <= CLKOS2_t; + CLKOS <= CLKOS_t; + CLKOP <= CLKOP_t; +end Structure; diff --git a/adc/cores/fifo_cdt_70x16/fifo_cdt_70x16.cst b/adc/cores/fifo_cdt_70x16/fifo_cdt_70x16.cst new file mode 100644 index 0000000..a3a1d4d --- /dev/null +++ b/adc/cores/fifo_cdt_70x16/fifo_cdt_70x16.cst @@ -0,0 +1,3 @@ +Date=05/10/2024 +Time=14:38:34 + diff --git a/adc/cores/fifo_cdt_70x16/fifo_cdt_70x16.fdc b/adc/cores/fifo_cdt_70x16/fifo_cdt_70x16.fdc new file mode 100644 index 0000000..6fbcac9 --- /dev/null +++ b/adc/cores/fifo_cdt_70x16/fifo_cdt_70x16.fdc @@ -0,0 +1,2 @@ +###==== Start Configuration + diff --git a/adc/cores/fifo_cdt_70x16/fifo_cdt_70x16.lpc b/adc/cores/fifo_cdt_70x16/fifo_cdt_70x16.lpc new file mode 100644 index 0000000..f1769b6 --- /dev/null +++ b/adc/cores/fifo_cdt_70x16/fifo_cdt_70x16.lpc @@ -0,0 +1,53 @@ +[Device] +Family=ecp5um +PartType=LFE5UM-85F +PartName=LFE5UM-85F-8BG756C +SpeedGrade=8 +Package=CABGA756 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.8 +ModuleName=fifo_cdt_70x16 +SourceFormat=vhdl +ParameterFileVersion=1.0 +Date=05/10/2024 +Time=14:38:34 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=16 +Width=70 +RDepth=16 +RWidth=70 +regout=1 +ClockEn=0 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=0 +PfMode=Static - Dual Threshold +PfAssert=508 +PfDeassert=506 +Reset=Async +Reset1=Sync +RDataCount=0 +WDataCount=0 +EnECC=0 + +[Command] +cmd_line= -w -n fifo_cdt_70x16 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -depth 16 -width 70 -rwidth 70 -regout -no_enable -reset_rel SYNC -pe -1 -pf -1 diff --git a/adc/cores/fifo_cdt_70x16/fifo_cdt_70x16.sbx b/adc/cores/fifo_cdt_70x16/fifo_cdt_70x16.sbx new file mode 100644 index 0000000..a933f9b --- /dev/null +++ b/adc/cores/fifo_cdt_70x16/fifo_cdt_70x16.sbx @@ -0,0 +1,264 @@ + + + + Lattice Semiconductor Corporation + LEGACY + FIFO_DC + 5.8 + + + Diamond_Simulation + simulation + + ./fifo_cdt_70x16.vhd + vhdlSource + + + + Diamond_Synthesis + synthesis + + ./fifo_cdt_70x16.vhd + vhdlSource + + + + + + Configuration + none + ${sbp_path}/generate_core.tcl + CONFIG + + + + + + + + LFE5UM-85F-8BG756C + synplify + 2024-05-10.02:38:36 PM + 2024-05-10.02:38:36 PM + 3.12.1.454 + VHDL + + false + false + false + false + false + false + false + false + false + false + LPM + PRIMARY + PRIMARY + false + false + + + + + + Family + ecp5um + + + OperatingCondition + COM + + + Package + CABGA756 + + + PartName + LFE5UM-85F-8BG756C + + + PartType + LFE5UM-85F + + + SpeedGrade + 8 + + + Status + P + + + + CoreName + FIFO_DC + + + CoreRevision + 5.8 + + + CoreStatus + Demo + + + CoreType + LPM + + + Date + 05/10/2024 + + + ModuleName + fifo_cdt_70x16 + + + ParameterFileVersion + 1.0 + + + SourceFormat + vhdl + + + Time + 14:38:34 + + + VendorName + Lattice Semiconductor Corporation + + + + ClockEn + 0 + + + CtrlByRdEn + 0 + + + Depth + 16 + + + Destination + Synplicity + + + EDIF + 1 + + + EmpFlg + 0 + + + EnECC + 0 + + + Expression + BusA(0 to 7) + + + FIFOImp + EBR Based + + + FullFlg + 0 + + + IO + 0 + + + Order + Big Endian [MSB:LSB] + + + PeAssert + 10 + + + PeDeassert + 12 + + + PeMode + Static - Dual Threshold + + + PfAssert + 508 + + + PfDeassert + 506 + + + PfMode + Static - Dual Threshold + + + RDataCount + 0 + + + RDepth + 16 + + + RWidth + 70 + + + Reset + Async + + + Reset1 + Sync + + + VHDL + 1 + + + Verilog + 0 + + + WDataCount + 0 + + + Width + 70 + + + regout + 1 + + + + cmd_line + -w -n fifo_cdt_70x16 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -depth 16 -width 70 -rwidth 70 -regout -no_enable -reset_rel SYNC -pe -1 -pf -1 + + + + + + + LATTICE + LOCAL + fifo_cdt_70x16 + 1.0 + + + + diff --git a/adc/cores/fifo_cdt_70x16/fifo_cdt_70x16.vhd b/adc/cores/fifo_cdt_70x16/fifo_cdt_70x16.vhd new file mode 100644 index 0000000..9ab5243 --- /dev/null +++ b/adc/cores/fifo_cdt_70x16/fifo_cdt_70x16.vhd @@ -0,0 +1,713 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 +-- Module Version: 5.8 +--/d/jspc29/lattice/diamond/3.12/ispfpga/bin/lin64/scuba -w -n fifo_cdt_70x16 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -depth 16 -width 70 -rwidth 70 -regout -no_enable -reset_rel SYNC -pe -1 -pf -1 -fdc /local/trb/git/trb5sc/adc/cores/fifo_cdt_70x16/fifo_cdt_70x16.fdc + +-- Fri May 10 14:38:36 2024 + +library IEEE; +use IEEE.std_logic_1164.all; +library ecp5um; +use ecp5um.components.all; + +entity fifo_cdt_70x16 is + port ( + Data: in std_logic_vector(69 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(69 downto 0); + Empty: out std_logic; + Full: out std_logic); +end fifo_cdt_70x16; + +architecture Structure of fifo_cdt_70x16 is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal co2: std_logic; + signal co1: std_logic; + signal wcount_4: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal co2_1: std_logic; + signal co1_1: std_logic; + signal rcount_4: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_2: std_logic; + signal wcount_r2: std_logic; + signal wcount_r3: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_2: std_logic; + signal empty_cmp_clr: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal wren_i: std_logic; + signal cmp_ci_1: std_logic; + signal rcount_w0: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_3: std_logic; + signal rcount_w2: std_logic; + signal rcount_w3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_3: std_logic; + signal full_cmp_clr: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + signal full_d_c: std_logic; + + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_cdt_70x16.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "fifo_cdt_70x16.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is ""; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t10: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_1: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t9: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_0: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t8: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t7: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t6: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t5: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t4: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t3: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t2: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t1: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t0: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + LUT4_11: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, + AD1=>w_gcount_r23, AD0=>w_gcount_r24, + DO0=>w_g2b_xor_cluster_0); + + LUT4_10: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r3); + + LUT4_9: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, + AD1=>w_gcount_r24, AD0=>scuba_vlo, DO0=>wcount_r2); + + LUT4_8: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, + AD1=>w_gcount_r22, AD0=>wcount_r3, DO0=>wcount_r0); + + LUT4_7: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, + AD1=>r_gcount_w23, AD0=>r_gcount_w24, + DO0=>r_g2b_xor_cluster_0); + + LUT4_6: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w3); + + LUT4_5: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, + AD1=>r_gcount_w24, AD0=>scuba_vlo, DO0=>rcount_w2); + + LUT4_4: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, + AD1=>r_gcount_w22, AD0=>rcount_w3, DO0=>rcount_w0); + + LUT4_3: ROM16X1A + generic map (initval=> X"0410") + port map (AD3=>rptr_4, AD2=>rcount_4, AD1=>w_gcount_r24, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_2: ROM16X1A + generic map (initval=> X"1004") + port map (AD3=>rptr_4, AD2=>rcount_4, AD1=>w_gcount_r24, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_1: ROM16X1A + generic map (initval=> X"0140") + port map (AD3=>wptr_4, AD2=>wcount_4, AD1=>r_gcount_w24, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_0: ROM16X1A + generic map (initval=> X"4001") + port map (AD3=>wptr_4, AD2=>wcount_4, AD1=>r_gcount_w24, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + pdp_ram_0_0_1: PDPW16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_R=> "0b001", CSDECODE_W=> "0b001", GSR=> "ENABLED", + RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, + DATA_WIDTH_W=> 36) + port map (DI35=>Data(35), DI34=>Data(34), DI33=>Data(33), + DI32=>Data(32), DI31=>Data(31), DI30=>Data(30), + DI29=>Data(29), DI28=>Data(28), DI27=>Data(27), + DI26=>Data(26), DI25=>Data(25), DI24=>Data(24), + DI23=>Data(23), DI22=>Data(22), DI21=>Data(21), + DI20=>Data(20), DI19=>Data(19), DI18=>Data(18), + DI17=>Data(17), DI16=>Data(16), DI15=>Data(15), + DI14=>Data(14), DI13=>Data(13), DI12=>Data(12), + DI11=>Data(11), DI10=>Data(10), DI9=>Data(9), DI8=>Data(8), + DI7=>Data(7), DI6=>Data(6), DI5=>Data(5), DI4=>Data(4), + DI3=>Data(3), DI2=>Data(2), DI1=>Data(1), DI0=>Data(0), + ADW8=>scuba_vlo, ADW7=>scuba_vlo, ADW6=>scuba_vlo, + ADW5=>scuba_vlo, ADW4=>scuba_vlo, ADW3=>wptr_3, ADW2=>wptr_2, + ADW1=>wptr_1, ADW0=>wptr_0, BE3=>scuba_vhi, BE2=>scuba_vhi, + BE1=>scuba_vhi, BE0=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, + CSW2=>scuba_vlo, CSW1=>scuba_vlo, CSW0=>scuba_vhi, + ADR13=>scuba_vlo, ADR12=>scuba_vlo, ADR11=>scuba_vlo, + ADR10=>scuba_vlo, ADR9=>scuba_vlo, ADR8=>rptr_3, + ADR7=>rptr_2, ADR6=>rptr_1, ADR5=>rptr_0, ADR4=>scuba_vlo, + ADR3=>scuba_vlo, ADR2=>scuba_vlo, ADR1=>scuba_vlo, + ADR0=>scuba_vlo, CER=>scuba_vhi, OCER=>scuba_vhi, + CLKR=>RdClock, CSR2=>scuba_vlo, CSR1=>scuba_vlo, + CSR0=>rden_i, RST=>Reset, DO35=>Q(17), DO34=>Q(16), + DO33=>Q(15), DO32=>Q(14), DO31=>Q(13), DO30=>Q(12), + DO29=>Q(11), DO28=>Q(10), DO27=>Q(9), DO26=>Q(8), DO25=>Q(7), + DO24=>Q(6), DO23=>Q(5), DO22=>Q(4), DO21=>Q(3), DO20=>Q(2), + DO19=>Q(1), DO18=>Q(0), DO17=>Q(35), DO16=>Q(34), + DO15=>Q(33), DO14=>Q(32), DO13=>Q(31), DO12=>Q(30), + DO11=>Q(29), DO10=>Q(28), DO9=>Q(27), DO8=>Q(26), DO7=>Q(25), + DO6=>Q(24), DO5=>Q(23), DO4=>Q(22), DO3=>Q(21), DO2=>Q(20), + DO1=>Q(19), DO0=>Q(18)); + + pdp_ram_0_1_0: PDPW16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_R=> "0b001", CSDECODE_W=> "0b001", GSR=> "ENABLED", + RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, + DATA_WIDTH_W=> 36) + port map (DI35=>scuba_vlo, DI34=>scuba_vlo, DI33=>Data(69), + DI32=>Data(68), DI31=>Data(67), DI30=>Data(66), + DI29=>Data(65), DI28=>Data(64), DI27=>Data(63), + DI26=>Data(62), DI25=>Data(61), DI24=>Data(60), + DI23=>Data(59), DI22=>Data(58), DI21=>Data(57), + DI20=>Data(56), DI19=>Data(55), DI18=>Data(54), + DI17=>Data(53), DI16=>Data(52), DI15=>Data(51), + DI14=>Data(50), DI13=>Data(49), DI12=>Data(48), + DI11=>Data(47), DI10=>Data(46), DI9=>Data(45), DI8=>Data(44), + DI7=>Data(43), DI6=>Data(42), DI5=>Data(41), DI4=>Data(40), + DI3=>Data(39), DI2=>Data(38), DI1=>Data(37), DI0=>Data(36), + ADW8=>scuba_vlo, ADW7=>scuba_vlo, ADW6=>scuba_vlo, + ADW5=>scuba_vlo, ADW4=>scuba_vlo, ADW3=>wptr_3, ADW2=>wptr_2, + ADW1=>wptr_1, ADW0=>wptr_0, BE3=>scuba_vhi, BE2=>scuba_vhi, + BE1=>scuba_vhi, BE0=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, + CSW2=>scuba_vlo, CSW1=>scuba_vlo, CSW0=>scuba_vhi, + ADR13=>scuba_vlo, ADR12=>scuba_vlo, ADR11=>scuba_vlo, + ADR10=>scuba_vlo, ADR9=>scuba_vlo, ADR8=>rptr_3, + ADR7=>rptr_2, ADR6=>rptr_1, ADR5=>rptr_0, ADR4=>scuba_vlo, + ADR3=>scuba_vlo, ADR2=>scuba_vlo, ADR1=>scuba_vlo, + ADR0=>scuba_vlo, CER=>scuba_vhi, OCER=>scuba_vhi, + CLKR=>RdClock, CSR2=>scuba_vlo, CSR1=>scuba_vlo, + CSR0=>rden_i, RST=>Reset, DO35=>Q(53), DO34=>Q(52), + DO33=>Q(51), DO32=>Q(50), DO31=>Q(49), DO30=>Q(48), + DO29=>Q(47), DO28=>Q(46), DO27=>Q(45), DO26=>Q(44), + DO25=>Q(43), DO24=>Q(42), DO23=>Q(41), DO22=>Q(40), + DO21=>Q(39), DO20=>Q(38), DO19=>Q(37), DO18=>Q(36), + DO17=>open, DO16=>open, DO15=>Q(69), DO14=>Q(68), + DO13=>Q(67), DO12=>Q(66), DO11=>Q(65), DO10=>Q(64), + DO9=>Q(63), DO8=>Q(62), DO7=>Q(61), DO6=>Q(60), DO5=>Q(59), + DO4=>Q(58), DO3=>Q(57), DO2=>Q(56), DO1=>Q(55), DO0=>Q(54)); + + FF_51: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_50: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_49: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_48: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_47: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_46: FD1P3DX + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_45: FD1P3DX + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_44: FD1P3DX + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_43: FD1P3DX + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_42: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_41: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_40: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_39: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_38: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_37: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_36: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_35: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_34: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_33: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_32: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_31: FD1P3DX + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_30: FD1P3DX + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_29: FD1P3DX + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_28: FD1P3DX + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_27: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_26: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_25: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_24: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_23: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_22: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_21: FD1S3DX + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_20: FD1S3DX + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_19: FD1S3DX + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_18: FD1S3DX + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_17: FD1S3DX + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_16: FD1S3DX + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_15: FD1S3DX + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_14: FD1S3DX + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_13: FD1S3DX + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_12: FD1S3DX + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_11: FD1S3DX + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_10: FD1S3DX + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_9: FD1S3DX + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_8: FD1S3DX + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_7: FD1S3DX + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_6: FD1S3DX + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_5: FD1S3DX + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_4: FD1S3DX + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_3: FD1S3DX + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_2: FD1S3DX + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_1: FD1S3BX + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_0: FD1S3DX + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + w_gctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>w_gctr_ci); + + w_gctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>w_gctr_ci, S0=>iwcount_0, S1=>iwcount_1, + COUT=>co0); + + w_gctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_2, A1=>wcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0, S0=>iwcount_2, S1=>iwcount_3, + COUT=>co1); + + w_gctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_4, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1, S0=>iwcount_4, S1=>open, COUT=>co2); + + r_gctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>r_gctr_ci); + + r_gctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>r_gctr_ci, S0=>ircount_0, S1=>ircount_1, + COUT=>co0_1); + + r_gctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_2, A1=>rcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_1, S0=>ircount_2, S1=>ircount_3, + COUT=>co1_1); + + r_gctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_4, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_1, S0=>ircount_4, S1=>open, + COUT=>co2_1); + + empty_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci); + + empty_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, + B1=>w_g2b_xor_cluster_0, C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>cmp_ci, S0=>open, + S1=>open, COUT=>co0_2); + + empty_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, + B1=>wcount_r3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_2, S0=>open, S1=>open, COUT=>co1_2); + + empty_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_2, S0=>open, S1=>open, + COUT=>empty_d_c); + + a0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>empty_d_c, S0=>empty_d, S1=>open, + COUT=>open); + + full_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_1); + + full_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, + B1=>r_g2b_xor_cluster_0, C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>cmp_ci_1, S0=>open, + S1=>open, COUT=>co0_3); + + full_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, + B1=>rcount_w3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_3, S0=>open, S1=>open, COUT=>co1_3); + + full_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_3, S0=>open, S1=>open, + COUT=>full_d_c); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>full_d_c, S0=>full_d, S1=>open, + COUT=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; diff --git a/adc/cores/input_4ch/input_4ch.fdc b/adc/cores/input_4ch/input_4ch.fdc new file mode 100644 index 0000000..6fbcac9 --- /dev/null +++ b/adc/cores/input_4ch/input_4ch.fdc @@ -0,0 +1,2 @@ +###==== Start Configuration + diff --git a/adc/cores/input_4ch/input_4ch.lpc b/adc/cores/input_4ch/input_4ch.lpc new file mode 100644 index 0000000..68f5b98 --- /dev/null +++ b/adc/cores/input_4ch/input_4ch.lpc @@ -0,0 +1,66 @@ +[Device] +Family=ecp5um +PartType=LFE5UM-85F +PartName=LFE5UM-85F-8BG756C +SpeedGrade=8 +Package=CABGA756 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=DDR_GENERIC +CoreRevision=6.0 +ModuleName=input_4ch +SourceFormat=vhdl +ParameterFileVersion=1.0 +Date=04/30/2024 +Time=11:23:01 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +mode=Receive +trioddr=0 +io_type=LVDS +width=5 +freq_in=350 +bandwidth=3500 +aligned=Centered +pre-configuration=DISABLED +mode2=Receive +trioddr2=0 +io_type2=LVDS +freq_in2=350 +gear=4:1 +aligned2=Edge-to-Edge +width2=5 +DataLane=By Lane +EnECLK=0 +Interface=GDDRX2_RX.ECLK.Aligned +Delay=Static User Defined +DelVal=59 +EnInEdge= +NumEdge=BOTH +EnDynamic=0 +GenPll=0 +Freq= +AFreq= +Reference=0 +IOBUF= +ReceiverSync=0 +EnDynamicAlign= +DynamicAlign= +MIPIFilter=0 +enClkIBuf=0 +ClkIBuf=LVDS + +[Command] +cmd_line= -w -n input_4ch -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type iol -mode Receive -io_type LVDS -width 5 -freq_in 350 -gear 4 -aligned -del 59 -data_lane diff --git a/adc/cores/input_4ch/input_4ch.sbx b/adc/cores/input_4ch/input_4ch.sbx new file mode 100644 index 0000000..49e7d6a --- /dev/null +++ b/adc/cores/input_4ch/input_4ch.sbx @@ -0,0 +1,322 @@ + + + + Lattice Semiconductor Corporation + LEGACY + DDR_GENERIC + 6.0 + + + Diamond_Simulation + simulation + + ./input_4ch.vhd + vhdlSource + + + + Diamond_Synthesis + synthesis + + ./input_4ch.vhd + vhdlSource + + + + + + Configuration + none + ${sbp_path}/generate_core.tcl + CONFIG + + + Generation + none + ${sbp_path}/${instance}/generate_core.tcl + GENERATE + + + + + + + + LFE5UM-85F-8BG756C + synplify + 2024-04-30.10:34:12 AM + 2024-04-30.01:43:04 PM + 3.12.1.454 + VHDL + + false + false + false + false + false + false + false + false + false + false + LPM + PRIMARY + PRIMARY + false + false + + + + + + Family + ecp5um + + + OperatingCondition + COM + + + Package + CABGA756 + + + PartName + LFE5UM-85F-8BG756C + + + PartType + LFE5UM-85F + + + SpeedGrade + 8 + + + Status + P + + + + CoreName + DDR_GENERIC + + + CoreRevision + 6.0 + + + CoreStatus + Demo + + + CoreType + LPM + + + Date + 04/30/2024 + + + ModuleName + input_4ch + + + ParameterFileVersion + 1.0 + + + SourceFormat + vhdl + + + Time + 11:23:01 + + + VendorName + Lattice Semiconductor Corporation + + + + AFreq + + + + ClkIBuf + LVDS + + + DataLane + By Lane + + + DelVal + 59 + + + Delay + Static User Defined + + + Destination + Synplicity + + + DynamicAlign + + + + EDIF + 1 + + + EnDynamic + 0 + + + EnDynamicAlign + + + + EnECLK + 0 + + + EnInEdge + + + + Expression + BusA(0 to 7) + + + Freq + + + + GenPll + 0 + + + IO + 0 + + + IOBUF + + + + Interface + GDDRX2_RX.ECLK.Aligned + + + MIPIFilter + 0 + + + NumEdge + BOTH + + + Order + Big Endian [MSB:LSB] + + + ReceiverSync + 0 + + + Reference + 0 + + + VHDL + 1 + + + Verilog + 0 + + + aligned + Centered + + + aligned2 + Edge-to-Edge + + + bandwidth + 3500 + + + enClkIBuf + 0 + + + freq_in + 350 + + + freq_in2 + 350 + + + gear + 4:1 + + + io_type + LVDS + + + io_type2 + LVDS + + + mode + Receive + + + mode2 + Receive + + + pre-configuration + DISABLED + + + trioddr + 0 + + + trioddr2 + 0 + + + width + 5 + + + width2 + 5 + + + + cmd_line + -w -n input_4ch -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type iol -mode Receive -io_type LVDS -width 5 -freq_in 350 -gear 4 -aligned -del 59 -data_lane + + + + + + + LATTICE + LOCAL + input_4ch + 1.0 + + + + diff --git a/adc/cores/input_4ch/input_4ch.vhd b/adc/cores/input_4ch/input_4ch.vhd new file mode 100644 index 0000000..56ab7b4 --- /dev/null +++ b/adc/cores/input_4ch/input_4ch.vhd @@ -0,0 +1,1332 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 +-- Module Version: 5.8 +--/d/jspc29/lattice/diamond/3.12/ispfpga/bin/lin64/scuba -w -n input_4ch -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type iol -mode Receive -io_type LVDS -width 5 -freq_in 350 -gear 4 -aligned -del 59 -data_lane + +-- Tue Apr 30 11:23:01 2024 + + + +-- +-- Verific VHDL Description of OPERATOR equal_32 +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +entity equal_32 is + port (a: in std_logic_vector(31 downto 0); + b: in std_logic_vector(31 downto 0); + o: out std_logic + ); + +end entity equal_32; + +architecture INTERFACE of equal_32 is + signal n1,n2,n3,n4,n5,n6,n7,n8,n9,n10,n11,n12,n13,n14,n15, + n16,n17,n18,n19,n20,n21,n22,n23,n24,n25,n26,n27,n28,n29, + n30,n31,n32,n33,n34,n35,n36,n37,n38,n39,n40,n41,n42,n43, + n44,n45,n46,n47,n48,n49,n50,n51,n52,n53,n54,n55,n56,n57, + n58,n59,n60,n61,n62,n63 : std_logic; +begin + n1 <= a(0) xor b(0); + n2 <= a(1) xor b(1); + n3 <= a(2) xor b(2); + n4 <= a(3) xor b(3); + n5 <= a(4) xor b(4); + n6 <= a(5) xor b(5); + n7 <= a(6) xor b(6); + n8 <= a(7) xor b(7); + n9 <= a(8) xor b(8); + n10 <= a(9) xor b(9); + n11 <= a(10) xor b(10); + n12 <= a(11) xor b(11); + n13 <= a(12) xor b(12); + n14 <= a(13) xor b(13); + n15 <= a(14) xor b(14); + n16 <= a(15) xor b(15); + n17 <= a(16) xor b(16); + n18 <= a(17) xor b(17); + n19 <= a(18) xor b(18); + n20 <= a(19) xor b(19); + n21 <= a(20) xor b(20); + n22 <= a(21) xor b(21); + n23 <= a(22) xor b(22); + n24 <= a(23) xor b(23); + n25 <= a(24) xor b(24); + n26 <= a(25) xor b(25); + n27 <= a(26) xor b(26); + n28 <= a(27) xor b(27); + n29 <= a(28) xor b(28); + n30 <= a(29) xor b(29); + n31 <= a(30) xor b(30); + n32 <= a(31) xor b(31); + n33 <= n1 or n2; + n34 <= n3 or n4; + n35 <= n33 or n34; + n36 <= n5 or n6; + n37 <= n7 or n8; + n38 <= n36 or n37; + n39 <= n35 or n38; + n40 <= n9 or n10; + n41 <= n11 or n12; + n42 <= n40 or n41; + n43 <= n13 or n14; + n44 <= n15 or n16; + n45 <= n43 or n44; + n46 <= n42 or n45; + n47 <= n39 or n46; + n48 <= n17 or n18; + n49 <= n19 or n20; + n50 <= n48 or n49; + n51 <= n21 or n22; + n52 <= n23 or n24; + n53 <= n51 or n52; + n54 <= n50 or n53; + n55 <= n25 or n26; + n56 <= n27 or n28; + n57 <= n55 or n56; + n58 <= n29 or n30; + n59 <= n31 or n32; + n60 <= n58 or n59; + n61 <= n57 or n60; + n62 <= n54 or n61; + n63 <= n47 or n62; + o <= not n63; + +end architecture INTERFACE; + + +-- +-- Verific VHDL Description of OPERATOR mux_5 +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +entity mux_5 is + port (d0: in std_logic_vector(4 downto 0); + d1: in std_logic_vector(4 downto 0); + cond: in std_logic; + o: out std_logic_vector(4 downto 0) + ); + +end entity mux_5; + +architecture INTERFACE of mux_5 is + +begin + o(0) <= d1(0) when cond='1' else d0(0); + o(1) <= d1(1) when cond='1' else d0(1); + o(2) <= d1(2) when cond='1' else d0(2); + o(3) <= d1(3) when cond='1' else d0(3); + o(4) <= d1(4) when cond='1' else d0(4); + +end architecture INTERFACE; + + +-- +-- Verific VHDL Description of OPERATOR equal_5 +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +entity equal_5 is + port (a: in std_logic_vector(4 downto 0); + b: in std_logic_vector(4 downto 0); + o: out std_logic + ); + +end entity equal_5; + +architecture INTERFACE of equal_5 is + signal n1,n2,n3,n4,n5,n6,n7,n8,n9 : std_logic; +begin + n1 <= a(0) xor b(0); + n2 <= a(1) xor b(1); + n3 <= a(2) xor b(2); + n4 <= a(3) xor b(3); + n5 <= a(4) xor b(4); + n6 <= n1 or n2; + n7 <= n4 or n5; + n8 <= n3 or n7; + n9 <= n6 or n8; + o <= not n9; + +end architecture INTERFACE; + + +-- +-- Verific VHDL Description of OPERATOR reduce_nor_6 +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +entity reduce_nor_6 is + port (a: in std_logic_vector(5 downto 0); + o: out std_logic + ); + +end entity reduce_nor_6; + +architecture INTERFACE of reduce_nor_6 is + signal n1,n2,n3,n4,n5 : std_logic; +begin + n1 <= a(1) or a(2); + n2 <= a(0) or n1; + n3 <= a(4) or a(5); + n4 <= a(3) or n3; + n5 <= n2 or n4; + o <= not n5; + +end architecture INTERFACE; + + +-- +-- Verific VHDL Description of OPERATOR Select_7 +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +entity Select_7 is + port (sel: in std_logic_vector(6 downto 0); + data: in std_logic_vector(6 downto 0); + o: out std_logic + ); + +end entity Select_7; + +architecture INTERFACE of Select_7 is + signal n1,n2,n3,n4,n5,n6,n7,n8,n9,n10,n11,n12 : std_logic; +begin + n1 <= data(0) and sel(0); + n2 <= data(1) and sel(1); + n3 <= data(2) and sel(2); + n4 <= data(3) and sel(3); + n5 <= data(4) and sel(4); + n6 <= data(5) and sel(5); + n7 <= data(6) and sel(6); + n8 <= n2 or n3; + n9 <= n1 or n8; + n10 <= n4 or n5; + n11 <= n6 or n7; + n12 <= n10 or n11; + o <= n9 or n12; + +end architecture INTERFACE; + + +-- +-- Verific VHDL Description of OPERATOR wide_select_7_35 +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +entity wide_select_7_35 is + port (sel: in std_logic_vector(6 downto 0); + data: in std_logic_vector(34 downto 0); + o: out std_logic_vector(4 downto 0) + ); + +end entity wide_select_7_35; + +architecture INTERFACE of wide_select_7_35 is + +begin + Select_0: entity work.Select_7(INTERFACE) port map (sel(6)=>sel(6),sel(5)=>sel(5), + sel(4)=>sel(4),sel(3)=>sel(3),sel(2)=>sel(2),sel(1)=>sel(1), + sel(0)=>sel(0),data(6)=>data(30),data(5)=>data(25),data(4)=>data(20), + data(3)=>data(15),data(2)=>data(10),data(1)=>data(5),data(0)=>data(0), + o=>o(0)); + Select_1: entity work.Select_7(INTERFACE) port map (sel(6)=>sel(6),sel(5)=>sel(5), + sel(4)=>sel(4),sel(3)=>sel(3),sel(2)=>sel(2),sel(1)=>sel(1), + sel(0)=>sel(0),data(6)=>data(31),data(5)=>data(26),data(4)=>data(21), + data(3)=>data(16),data(2)=>data(11),data(1)=>data(6),data(0)=>data(1), + o=>o(1)); + Select_2: entity work.Select_7(INTERFACE) port map (sel(6)=>sel(6),sel(5)=>sel(5), + sel(4)=>sel(4),sel(3)=>sel(3),sel(2)=>sel(2),sel(1)=>sel(1), + sel(0)=>sel(0),data(6)=>data(32),data(5)=>data(27),data(4)=>data(22), + data(3)=>data(17),data(2)=>data(12),data(1)=>data(7),data(0)=>data(2), + o=>o(2)); + Select_3: entity work.Select_7(INTERFACE) port map (sel(6)=>sel(6),sel(5)=>sel(5), + sel(4)=>sel(4),sel(3)=>sel(3),sel(2)=>sel(2),sel(1)=>sel(1), + sel(0)=>sel(0),data(6)=>data(33),data(5)=>data(28),data(4)=>data(23), + data(3)=>data(18),data(2)=>data(13),data(1)=>data(8),data(0)=>data(3), + o=>o(3)); + Select_4: entity work.Select_7(INTERFACE) port map (sel(6)=>sel(6),sel(5)=>sel(5), + sel(4)=>sel(4),sel(3)=>sel(3),sel(2)=>sel(2),sel(1)=>sel(1), + sel(0)=>sel(0),data(6)=>data(34),data(5)=>data(29),data(4)=>data(24), + data(3)=>data(19),data(2)=>data(14),data(1)=>data(9),data(0)=>data(4), + o=>o(4)); + +end architecture INTERFACE; + + +-- +-- Verific VHDL Description of OPERATOR LessThan_3u_3u +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +entity LessThan_3u_3u is + port (cin: in std_logic; + a: in std_logic_vector(2 downto 0); + b: in std_logic_vector(2 downto 0); + o: out std_logic + ); + +end entity LessThan_3u_3u; + +architecture INTERFACE of LessThan_3u_3u is + signal n1,n2,n3,n4,n5 : std_logic; +begin + n1 <= a(0) xor b(0); + n2 <= b(0) when n1='1' else cin; + n3 <= a(1) xor b(1); + n4 <= b(1) when n3='1' else n2; + n5 <= a(2) xor b(2); + o <= b(2) when n5='1' else n4; + +end architecture INTERFACE; + + +-- +-- Verific VHDL Description of OPERATOR add_32u_32u +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +entity add_32u_32u is + port (cin: in std_logic; + a: in std_logic_vector(31 downto 0); + b: in std_logic_vector(31 downto 0); + o: out std_logic_vector(31 downto 0); + cout: out std_logic + ); + +end entity add_32u_32u; + +architecture INTERFACE of add_32u_32u is + signal n2,n4,n6,n8,n10,n12,n14,n16,n18,n20,n22,n24,n26,n28, + n30,n32,n34,n36,n38,n40,n42,n44,n46,n48,n50,n52,n54,n56, + n58,n60,n62 : std_logic; +begin + n2 <= a(0) or b(0) when cin='1' else a(0) and b(0); + o(0) <= a(0) xor b(0) xor cin; + n4 <= a(1) or b(1) when n2='1' else a(1) and b(1); + o(1) <= a(1) xor b(1) xor n2; + n6 <= a(2) or b(2) when n4='1' else a(2) and b(2); + o(2) <= a(2) xor b(2) xor n4; + n8 <= a(3) or b(3) when n6='1' else a(3) and b(3); + o(3) <= a(3) xor b(3) xor n6; + n10 <= a(4) or b(4) when n8='1' else a(4) and b(4); + o(4) <= a(4) xor b(4) xor n8; + n12 <= a(5) or b(5) when n10='1' else a(5) and b(5); + o(5) <= a(5) xor b(5) xor n10; + n14 <= a(6) or b(6) when n12='1' else a(6) and b(6); + o(6) <= a(6) xor b(6) xor n12; + n16 <= a(7) or b(7) when n14='1' else a(7) and b(7); + o(7) <= a(7) xor b(7) xor n14; + n18 <= a(8) or b(8) when n16='1' else a(8) and b(8); + o(8) <= a(8) xor b(8) xor n16; + n20 <= a(9) or b(9) when n18='1' else a(9) and b(9); + o(9) <= a(9) xor b(9) xor n18; + n22 <= a(10) or b(10) when n20='1' else a(10) and b(10); + o(10) <= a(10) xor b(10) xor n20; + n24 <= a(11) or b(11) when n22='1' else a(11) and b(11); + o(11) <= a(11) xor b(11) xor n22; + n26 <= a(12) or b(12) when n24='1' else a(12) and b(12); + o(12) <= a(12) xor b(12) xor n24; + n28 <= a(13) or b(13) when n26='1' else a(13) and b(13); + o(13) <= a(13) xor b(13) xor n26; + n30 <= a(14) or b(14) when n28='1' else a(14) and b(14); + o(14) <= a(14) xor b(14) xor n28; + n32 <= a(15) or b(15) when n30='1' else a(15) and b(15); + o(15) <= a(15) xor b(15) xor n30; + n34 <= a(16) or b(16) when n32='1' else a(16) and b(16); + o(16) <= a(16) xor b(16) xor n32; + n36 <= a(17) or b(17) when n34='1' else a(17) and b(17); + o(17) <= a(17) xor b(17) xor n34; + n38 <= a(18) or b(18) when n36='1' else a(18) and b(18); + o(18) <= a(18) xor b(18) xor n36; + n40 <= a(19) or b(19) when n38='1' else a(19) and b(19); + o(19) <= a(19) xor b(19) xor n38; + n42 <= a(20) or b(20) when n40='1' else a(20) and b(20); + o(20) <= a(20) xor b(20) xor n40; + n44 <= a(21) or b(21) when n42='1' else a(21) and b(21); + o(21) <= a(21) xor b(21) xor n42; + n46 <= a(22) or b(22) when n44='1' else a(22) and b(22); + o(22) <= a(22) xor b(22) xor n44; + n48 <= a(23) or b(23) when n46='1' else a(23) and b(23); + o(23) <= a(23) xor b(23) xor n46; + n50 <= a(24) or b(24) when n48='1' else a(24) and b(24); + o(24) <= a(24) xor b(24) xor n48; + n52 <= a(25) or b(25) when n50='1' else a(25) and b(25); + o(25) <= a(25) xor b(25) xor n50; + n54 <= a(26) or b(26) when n52='1' else a(26) and b(26); + o(26) <= a(26) xor b(26) xor n52; + n56 <= a(27) or b(27) when n54='1' else a(27) and b(27); + o(27) <= a(27) xor b(27) xor n54; + n58 <= a(28) or b(28) when n56='1' else a(28) and b(28); + o(28) <= a(28) xor b(28) xor n56; + n60 <= a(29) or b(29) when n58='1' else a(29) and b(29); + o(29) <= a(29) xor b(29) xor n58; + n62 <= a(30) or b(30) when n60='1' else a(30) and b(30); + o(30) <= a(30) xor b(30) xor n60; + cout <= a(31) or b(31) when n62='1' else a(31) and b(31); + o(31) <= a(31) xor b(31) xor n62; + +end architecture INTERFACE; + + +-- +-- Verific VHDL Description of OPERATOR mux_3 +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +entity mux_3 is + port (d0: in std_logic_vector(2 downto 0); + d1: in std_logic_vector(2 downto 0); + cond: in std_logic; + o: out std_logic_vector(2 downto 0) + ); + +end entity mux_3; + +architecture INTERFACE of mux_3 is + +begin + o(0) <= d1(0) when cond='1' else d0(0); + o(1) <= d1(1) when cond='1' else d0(1); + o(2) <= d1(2) when cond='1' else d0(2); + +end architecture INTERFACE; + + +-- +-- Verific VHDL Description of OPERATOR not_equal_32 +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +entity not_equal_32 is + port (a: in std_logic_vector(31 downto 0); + b: in std_logic_vector(31 downto 0); + o: out std_logic + ); + +end entity not_equal_32; + +architecture INTERFACE of not_equal_32 is + signal n1,n2,n3,n4,n5,n6,n7,n8,n9,n10,n11,n12,n13,n14,n15, + n16,n17,n18,n19,n20,n21,n22,n23,n24,n25,n26,n27,n28,n29, + n30,n31,n32,n33,n34,n35,n36,n37,n38,n39,n40,n41,n42,n43, + n44,n45,n46,n47,n48,n49,n50,n51,n52,n53,n54,n55,n56,n57, + n58,n59,n60,n61,n62,n63,n64 : std_logic; +begin + n1 <= a(0) xor b(0); + n2 <= a(1) xor b(1); + n3 <= a(2) xor b(2); + n4 <= a(3) xor b(3); + n5 <= a(4) xor b(4); + n6 <= a(5) xor b(5); + n7 <= a(6) xor b(6); + n8 <= a(7) xor b(7); + n9 <= a(8) xor b(8); + n10 <= a(9) xor b(9); + n11 <= a(10) xor b(10); + n12 <= a(11) xor b(11); + n13 <= a(12) xor b(12); + n14 <= a(13) xor b(13); + n15 <= a(14) xor b(14); + n16 <= a(15) xor b(15); + n17 <= a(16) xor b(16); + n18 <= a(17) xor b(17); + n19 <= a(18) xor b(18); + n20 <= a(19) xor b(19); + n21 <= a(20) xor b(20); + n22 <= a(21) xor b(21); + n23 <= a(22) xor b(22); + n24 <= a(23) xor b(23); + n25 <= a(24) xor b(24); + n26 <= a(25) xor b(25); + n27 <= a(26) xor b(26); + n28 <= a(27) xor b(27); + n29 <= a(28) xor b(28); + n30 <= a(29) xor b(29); + n31 <= a(30) xor b(30); + n32 <= a(31) xor b(31); + n33 <= n1 or n2; + n34 <= n3 or n4; + n35 <= n33 or n34; + n36 <= n5 or n6; + n37 <= n7 or n8; + n38 <= n36 or n37; + n39 <= n35 or n38; + n40 <= n9 or n10; + n41 <= n11 or n12; + n42 <= n40 or n41; + n43 <= n13 or n14; + n44 <= n15 or n16; + n45 <= n43 or n44; + n46 <= n42 or n45; + n47 <= n39 or n46; + n48 <= n17 or n18; + n49 <= n19 or n20; + n50 <= n48 or n49; + n51 <= n21 or n22; + n52 <= n23 or n24; + n53 <= n51 or n52; + n54 <= n50 or n53; + n55 <= n25 or n26; + n56 <= n27 or n28; + n57 <= n55 or n56; + n58 <= n29 or n30; + n59 <= n31 or n32; + n60 <= n58 or n59; + n61 <= n57 or n60; + n62 <= n54 or n61; + n63 <= n47 or n62; + n64 <= not n63; + o <= not n64; + +end architecture INTERFACE; + + +-- +-- Verific VHDL Description of OPERATOR not_equal_5 +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +entity not_equal_5 is + port (a: in std_logic_vector(4 downto 0); + b: in std_logic_vector(4 downto 0); + o: out std_logic + ); + +end entity not_equal_5; + +architecture INTERFACE of not_equal_5 is + signal n1,n2,n3,n4,n5,n6,n7,n8,n9,n10 : std_logic; +begin + n1 <= a(0) xor b(0); + n2 <= a(1) xor b(1); + n3 <= a(2) xor b(2); + n4 <= a(3) xor b(3); + n5 <= a(4) xor b(4); + n6 <= n1 or n2; + n7 <= n4 or n5; + n8 <= n3 or n7; + n9 <= n6 or n8; + n10 <= not n9; + o <= not n10; + +end architecture INTERFACE; + + +-- +-- Verific VHDL Description of OPERATOR wide_dffrs_3 +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +entity wide_dffrs_3 is + port (d: in std_logic_vector(2 downto 0); + set: in std_logic_vector(2 downto 0); + reset: in std_logic_vector(2 downto 0); + clock: in std_logic; + q: out std_logic_vector(2 downto 0) + ); + +end entity wide_dffrs_3; + +architecture INTERFACE of wide_dffrs_3 is + procedure VERIFIC_DFFRS (d: in std_logic; + signal clk: in std_logic; + s: in std_logic; + r: in std_logic; + signal q: inout std_logic + ) is begin + if (s='1') then + q <= '1' ; + elsif (r='1') then + q <= '0' ; + elsif (clk'event and clk='1') then + q <= d ; + end if ; + end procedure VERIFIC_DFFRS; + signal \q[0]_c\,\q[1]_c\,\q[2]_c\ : std_logic; +begin + q(2) <= \q[2]_c\; + q(1) <= \q[1]_c\; + q(0) <= \q[0]_c\; + i1: VERIFIC_DFFRS (d=>d(0),clk=>clock,s=>set(0),r=>reset(0),q=>\q[0]_c\); + i2: VERIFIC_DFFRS (d=>d(1),clk=>clock,s=>set(1),r=>reset(1),q=>\q[1]_c\); + i3: VERIFIC_DFFRS (d=>d(2),clk=>clock,s=>set(2),r=>reset(2),q=>\q[2]_c\); + +end architecture INTERFACE; + + +-- +-- Verific VHDL Description of OPERATOR wide_dffrs_5 +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +entity wide_dffrs_5 is + port (d: in std_logic_vector(4 downto 0); + set: in std_logic_vector(4 downto 0); + reset: in std_logic_vector(4 downto 0); + clock: in std_logic; + q: out std_logic_vector(4 downto 0) + ); + +end entity wide_dffrs_5; + +architecture INTERFACE of wide_dffrs_5 is + procedure VERIFIC_DFFRS (d: in std_logic; + signal clk: in std_logic; + s: in std_logic; + r: in std_logic; + signal q: inout std_logic + ) is begin + if (s='1') then + q <= '1' ; + elsif (r='1') then + q <= '0' ; + elsif (clk'event and clk='1') then + q <= d ; + end if ; + end procedure VERIFIC_DFFRS; + signal \q[0]_c\,\q[1]_c\,\q[2]_c\,\q[3]_c\,\q[4]_c\ : std_logic; +begin + q(4) <= \q[4]_c\; + q(3) <= \q[3]_c\; + q(2) <= \q[2]_c\; + q(1) <= \q[1]_c\; + q(0) <= \q[0]_c\; + i1: VERIFIC_DFFRS (d=>d(0),clk=>clock,s=>set(0),r=>reset(0),q=>\q[0]_c\); + i2: VERIFIC_DFFRS (d=>d(1),clk=>clock,s=>set(1),r=>reset(1),q=>\q[1]_c\); + i3: VERIFIC_DFFRS (d=>d(2),clk=>clock,s=>set(2),r=>reset(2),q=>\q[2]_c\); + i4: VERIFIC_DFFRS (d=>d(3),clk=>clock,s=>set(3),r=>reset(3),q=>\q[3]_c\); + i5: VERIFIC_DFFRS (d=>d(4),clk=>clock,s=>set(4),r=>reset(4),q=>\q[4]_c\); + +end architecture INTERFACE; + + +-- +-- Verific VHDL Description of module input_4chrxdll_sync +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +library ecp5um ; +use ecp5um.components.all ; + +entity input_4chrxdll_sync is + port (rst: in std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(47) + sync_clk: in std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(48) + update: in std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(49) + dll_lock: in std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(50) + dll_reset: out std_logic; -- syn_preserve=1 -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(58) + uddcntln: out std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(53) + freeze: out std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(54) + stop: out std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(55) + ddr_reset: out std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(56) + ready: out std_logic -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(57) + ); + +end entity input_4chrxdll_sync; -- syn_module_defined=1 -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(25) + +architecture input_4chrxdll_sync of input_4chrxdll_sync is + procedure VERIFIC_DFFRS (d: in std_logic; + signal clk: in std_logic; + s: in std_logic; + r: in std_logic; + signal q: inout std_logic + ) is begin + if (s='1') then + q <= '1' ; + elsif (r='1') then + q <= '0' ; + elsif (clk'event and clk='1') then + q <= d ; + end if ; + end procedure VERIFIC_DFFRS; + signal uddcntln_c : std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(53) + signal freeze_c : std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(54) + signal stop_c : std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(55) + signal ready_c : std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(57) + signal dll_reset_c : std_logic; -- syn_preserve=1 -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(58) + signal ddr_reset_d : std_logic; -- syn_preserve=1 -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(75) + signal ctrl_cnt : std_logic_vector(2 downto 0); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(77) + signal dll_lock_cnt : std_logic_vector(2 downto 0); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(78) + signal ready_cnt : std_logic_vector(2 downto 0); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(79) + signal cs_rx_sync : std_logic_vector(4 downto 0); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(81) + signal ns_rx_sync : std_logic_vector(4 downto 0); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(82) + signal dll_lock_q1 : std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(84) + signal dll_lock_q2 : std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(85) + signal not_uddcntln : std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(87) + signal assert_stop : std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(88) + signal not_reset : std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(89) + signal not_stop : std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(90) + signal not_freeze : std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(91) + signal get_ready : std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(92) + signal n303,pwr,n3,n4,n5,n6,n8 : std_logic; + signal n9 : std_logic_vector(4 downto 0); + signal n15 : std_logic_vector(4 downto 0); + signal n21 : std_logic; + signal n24 : std_logic_vector(4 downto 0); + signal n30 : std_logic_vector(4 downto 0); + signal n36 : std_logic_vector(4 downto 0); + signal n42,n44 : std_logic; + signal n45 : std_logic_vector(4 downto 0); + signal n51 : std_logic; + signal n53 : std_logic_vector(4 downto 0); + signal n59 : std_logic_vector(4 downto 0); + signal n65,n67 : std_logic; + signal n68 : std_logic_vector(4 downto 0); + signal n74,n75 : std_logic; + signal n76 : std_logic_vector(4 downto 0); + signal n82,n83,n84,n85,n86,n87,n88,n97,n98,n99 : std_logic; + signal n101 : std_logic_vector(31 downto 0); + signal n134 : std_logic_vector(2 downto 0); + signal n138,n139,n140,n141,n142 : std_logic; + signal n144 : std_logic_vector(31 downto 0); + signal n177 : std_logic_vector(2 downto 0); + signal n181 : std_logic_vector(2 downto 0); + signal n185 : std_logic_vector(2 downto 0); + signal n189,n190 : std_logic; + signal n192 : std_logic_vector(31 downto 0); + signal n225 : std_logic_vector(2 downto 0); + signal n229,n230,n231,n232,n233,n234,n235,n236,n237,n238,n239, + n240,n241,n242,n243,n244,n245,n246,n247,n248,n249,n250,n251, + n252,n253,n254,n255,n256,n257,n258,n259,n260,n261,n262 : std_logic; + signal n263 : std_logic_vector(2 downto 0); + signal n267 : std_logic_vector(2 downto 0); + signal n271 : std_logic_vector(2 downto 0); + signal gnd : std_logic; signal OPEN_net : std_logic_vector(0 to 87); + +begin + dll_reset <= dll_reset_c; -- syn_preserve=1 -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(58) + uddcntln <= uddcntln_c; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(53) + freeze <= freeze_c; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(54) + stop <= stop_c; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(55) + ready <= ready_c; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(57) + n303 <= '0' ; + pwr <= '1' ; + ddr_reset <= cs_rx_sync(2) or ddr_reset_d; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(114) + equal_4: entity work.equal_32(INTERFACE) port map (a(31)=>n303,a(30)=>n303, + a(29)=>n303,a(28)=>n303,a(27)=>n303,a(26)=>n303,a(25)=>n303, + a(24)=>n303,a(23)=>n303,a(22)=>n303,a(21)=>n303,a(20)=>n303, + a(19)=>n303,a(18)=>n303,a(17)=>n303,a(16)=>n303,a(15)=>n303, + a(14)=>n303,a(13)=>n303,a(12)=>n303,a(11)=>n303,a(10)=>n303, + a(9)=>n303,a(8)=>n303,a(7)=>n303,a(6)=>n303,a(5)=>n303,a(4)=>n303, + a(3)=>n303,a(2)=>dll_lock_cnt(2),a(1)=>dll_lock_cnt(1),a(0)=>dll_lock_cnt(0), + b(31)=>n303,b(30)=>n303,b(29)=>n303,b(28)=>n303,b(27)=>n303, + b(26)=>n303,b(25)=>n303,b(24)=>n303,b(23)=>n303,b(22)=>n303, + b(21)=>n303,b(20)=>n303,b(19)=>n303,b(18)=>n303,b(17)=>n303, + b(16)=>n303,b(15)=>n303,b(14)=>n303,b(13)=>n303,b(12)=>n303, + b(11)=>n303,b(10)=>n303,b(9)=>n303,b(8)=>n303,b(7)=>n303,b(6)=>n303, + b(5)=>n303,b(4)=>n303,b(3)=>n303,b(2)=>pwr,b(1)=>n303,b(0)=>pwr, + o=>n3); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(124) + n4 <= not not_uddcntln; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(124) + n5 <= n3 and n4; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(124) + equal_7: entity work.equal_32(INTERFACE) port map (a(31)=>n303,a(30)=>n303, + a(29)=>n303,a(28)=>n303,a(27)=>n303,a(26)=>n303,a(25)=>n303, + a(24)=>n303,a(23)=>n303,a(22)=>n303,a(21)=>n303,a(20)=>n303, + a(19)=>n303,a(18)=>n303,a(17)=>n303,a(16)=>n303,a(15)=>n303, + a(14)=>n303,a(13)=>n303,a(12)=>n303,a(11)=>n303,a(10)=>n303, + a(9)=>n303,a(8)=>n303,a(7)=>n303,a(6)=>n303,a(5)=>n303,a(4)=>n303, + a(3)=>n303,a(2)=>ready_cnt(2),a(1)=>ready_cnt(1),a(0)=>ready_cnt(0), + b(31)=>n303,b(30)=>n303,b(29)=>n303,b(28)=>n303,b(27)=>n303, + b(26)=>n303,b(25)=>n303,b(24)=>n303,b(23)=>n303,b(22)=>n303, + b(21)=>n303,b(20)=>n303,b(19)=>n303,b(18)=>n303,b(17)=>n303, + b(16)=>n303,b(15)=>n303,b(14)=>n303,b(13)=>n303,b(12)=>n303, + b(11)=>n303,b(10)=>n303,b(9)=>n303,b(8)=>n303,b(7)=>n303,b(6)=>n303, + b(5)=>n303,b(4)=>n303,b(3)=>n303,b(2)=>pwr,b(1)=>pwr,b(0)=>pwr, + o=>n6); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(128) + n8 <= n6 and get_ready; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(128) + mux_10: entity work.mux_5(INTERFACE) port map (d0(4)=>n303,d0(3)=>n303, + d0(2)=>n303,d0(1)=>pwr,d0(0)=>n303,d1(4)=>n303,d1(3)=>n303, + d1(2)=>n303,d1(1)=>pwr,d1(0)=>pwr,cond=>n8,o(4)=>n9(4),o(3)=>n9(3), + o(2)=>n9(2),o(1)=>n9(1),o(0)=>n9(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(135) + mux_11: entity work.mux_5(INTERFACE) port map (d0(4)=>n9(4),d0(3)=>n9(3), + d0(2)=>n9(2),d0(1)=>n9(1),d0(0)=>n9(0),d1(4)=>pwr,d1(3)=>n303, + d1(2)=>n303,d1(1)=>pwr,d1(0)=>n303,cond=>n5,o(4)=>n15(4),o(3)=>n15(3), + o(2)=>n15(2),o(1)=>n15(1),o(0)=>n15(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(135) + equal_12: entity work.equal_32(INTERFACE) port map (a(31)=>n303,a(30)=>n303, + a(29)=>n303,a(28)=>n303,a(27)=>n303,a(26)=>n303,a(25)=>n303, + a(24)=>n303,a(23)=>n303,a(22)=>n303,a(21)=>n303,a(20)=>n303, + a(19)=>n303,a(18)=>n303,a(17)=>n303,a(16)=>n303,a(15)=>n303, + a(14)=>n303,a(13)=>n303,a(12)=>n303,a(11)=>n303,a(10)=>n303, + a(9)=>n303,a(8)=>n303,a(7)=>n303,a(6)=>n303,a(5)=>n303,a(4)=>n303, + a(3)=>n303,a(2)=>ctrl_cnt(2),a(1)=>ctrl_cnt(1),a(0)=>ctrl_cnt(0), + b(31)=>n303,b(30)=>n303,b(29)=>n303,b(28)=>n303,b(27)=>n303, + b(26)=>n303,b(25)=>n303,b(24)=>n303,b(23)=>n303,b(22)=>n303, + b(21)=>n303,b(20)=>n303,b(19)=>n303,b(18)=>n303,b(17)=>n303, + b(16)=>n303,b(15)=>n303,b(14)=>n303,b(13)=>n303,b(12)=>n303, + b(11)=>n303,b(10)=>n303,b(9)=>n303,b(8)=>n303,b(7)=>n303,b(6)=>n303, + b(5)=>n303,b(4)=>n303,b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>pwr, + o=>n21); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(140) + mux_15: entity work.mux_5(INTERFACE) port map (d0(4)=>pwr,d0(3)=>n303, + d0(2)=>n303,d0(1)=>n303,d0(0)=>n303,d1(4)=>n303,d1(3)=>n303, + d1(2)=>n303,d1(1)=>pwr,d1(0)=>n303,cond=>not_freeze,o(4)=>n24(4), + o(3)=>n24(3),o(2)=>n24(2),o(1)=>n24(1),o(0)=>n24(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(153) + mux_16: entity work.mux_5(INTERFACE) port map (d0(4)=>n24(4),d0(3)=>n24(3), + d0(2)=>n24(2),d0(1)=>n24(1),d0(0)=>n24(0),d1(4)=>pwr,d1(3)=>pwr, + d1(2)=>n303,d1(1)=>pwr,d1(0)=>n303,cond=>assert_stop,o(4)=>n30(4), + o(3)=>n30(3),o(2)=>n30(2),o(1)=>n30(1),o(0)=>n30(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(153) + mux_17: entity work.mux_5(INTERFACE) port map (d0(4)=>pwr,d0(3)=>n303, + d0(2)=>n303,d0(1)=>pwr,d0(0)=>n303,d1(4)=>n30(4),d1(3)=>n30(3), + d1(2)=>n30(2),d1(1)=>n30(1),d1(0)=>n30(0),cond=>n21,o(4)=>n36(4), + o(3)=>n36(3),o(2)=>n36(2),o(1)=>n36(1),o(0)=>n36(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(158) + equal_18: entity work.equal_32(INTERFACE) port map (a(31)=>n303,a(30)=>n303, + a(29)=>n303,a(28)=>n303,a(27)=>n303,a(26)=>n303,a(25)=>n303, + a(24)=>n303,a(23)=>n303,a(22)=>n303,a(21)=>n303,a(20)=>n303, + a(19)=>n303,a(18)=>n303,a(17)=>n303,a(16)=>n303,a(15)=>n303, + a(14)=>n303,a(13)=>n303,a(12)=>n303,a(11)=>n303,a(10)=>n303, + a(9)=>n303,a(8)=>n303,a(7)=>n303,a(6)=>n303,a(5)=>n303,a(4)=>n303, + a(3)=>n303,a(2)=>ctrl_cnt(2),a(1)=>ctrl_cnt(1),a(0)=>ctrl_cnt(0), + b(31)=>n303,b(30)=>n303,b(29)=>n303,b(28)=>n303,b(27)=>n303, + b(26)=>n303,b(25)=>n303,b(24)=>n303,b(23)=>n303,b(22)=>n303, + b(21)=>n303,b(20)=>n303,b(19)=>n303,b(18)=>n303,b(17)=>n303, + b(16)=>n303,b(15)=>n303,b(14)=>n303,b(13)=>n303,b(12)=>n303, + b(11)=>n303,b(10)=>n303,b(9)=>n303,b(8)=>n303,b(7)=>n303,b(6)=>n303, + b(5)=>n303,b(4)=>n303,b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>pwr, + o=>n42); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(163) + n44 <= n42 and not_uddcntln; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(163) + mux_21: entity work.mux_5(INTERFACE) port map (d0(4)=>pwr,d0(3)=>n303, + d0(2)=>n303,d0(1)=>n303,d0(0)=>n303,d1(4)=>pwr,d1(3)=>n303, + d1(2)=>n303,d1(1)=>pwr,d1(0)=>n303,cond=>n44,o(4)=>n45(4),o(3)=>n45(3), + o(2)=>n45(2),o(1)=>n45(1),o(0)=>n45(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(170) + equal_22: entity work.equal_32(INTERFACE) port map (a(31)=>n303,a(30)=>n303, + a(29)=>n303,a(28)=>n303,a(27)=>n303,a(26)=>n303,a(25)=>n303, + a(24)=>n303,a(23)=>n303,a(22)=>n303,a(21)=>n303,a(20)=>n303, + a(19)=>n303,a(18)=>n303,a(17)=>n303,a(16)=>n303,a(15)=>n303, + a(14)=>n303,a(13)=>n303,a(12)=>n303,a(11)=>n303,a(10)=>n303, + a(9)=>n303,a(8)=>n303,a(7)=>n303,a(6)=>n303,a(5)=>n303,a(4)=>n303, + a(3)=>n303,a(2)=>ctrl_cnt(2),a(1)=>ctrl_cnt(1),a(0)=>ctrl_cnt(0), + b(31)=>n303,b(30)=>n303,b(29)=>n303,b(28)=>n303,b(27)=>n303, + b(26)=>n303,b(25)=>n303,b(24)=>n303,b(23)=>n303,b(22)=>n303, + b(21)=>n303,b(20)=>n303,b(19)=>n303,b(18)=>n303,b(17)=>n303, + b(16)=>n303,b(15)=>n303,b(14)=>n303,b(13)=>n303,b(12)=>n303, + b(11)=>n303,b(10)=>n303,b(9)=>n303,b(8)=>n303,b(7)=>n303,b(6)=>n303, + b(5)=>n303,b(4)=>n303,b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>pwr, + o=>n51); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(175) + mux_24: entity work.mux_5(INTERFACE) port map (d0(4)=>pwr,d0(3)=>pwr, + d0(2)=>pwr,d0(1)=>pwr,d0(0)=>n303,d1(4)=>pwr,d1(3)=>n303,d1(2)=>n303, + d1(1)=>pwr,d1(0)=>n303,cond=>not_stop,o(4)=>n53(4),o(3)=>n53(3), + o(2)=>n53(2),o(1)=>n53(1),o(0)=>n53(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(184) + mux_25: entity work.mux_5(INTERFACE) port map (d0(4)=>pwr,d0(3)=>pwr, + d0(2)=>n303,d0(1)=>pwr,d0(0)=>n303,d1(4)=>n53(4),d1(3)=>n53(3), + d1(2)=>n53(2),d1(1)=>n53(1),d1(0)=>n53(0),cond=>n51,o(4)=>n59(4), + o(3)=>n59(3),o(2)=>n59(2),o(1)=>n59(1),o(0)=>n59(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(189) + equal_26: entity work.equal_32(INTERFACE) port map (a(31)=>n303,a(30)=>n303, + a(29)=>n303,a(28)=>n303,a(27)=>n303,a(26)=>n303,a(25)=>n303, + a(24)=>n303,a(23)=>n303,a(22)=>n303,a(21)=>n303,a(20)=>n303, + a(19)=>n303,a(18)=>n303,a(17)=>n303,a(16)=>n303,a(15)=>n303, + a(14)=>n303,a(13)=>n303,a(12)=>n303,a(11)=>n303,a(10)=>n303, + a(9)=>n303,a(8)=>n303,a(7)=>n303,a(6)=>n303,a(5)=>n303,a(4)=>n303, + a(3)=>n303,a(2)=>ctrl_cnt(2),a(1)=>ctrl_cnt(1),a(0)=>ctrl_cnt(0), + b(31)=>n303,b(30)=>n303,b(29)=>n303,b(28)=>n303,b(27)=>n303, + b(26)=>n303,b(25)=>n303,b(24)=>n303,b(23)=>n303,b(22)=>n303, + b(21)=>n303,b(20)=>n303,b(19)=>n303,b(18)=>n303,b(17)=>n303, + b(16)=>n303,b(15)=>n303,b(14)=>n303,b(13)=>n303,b(12)=>n303, + b(11)=>n303,b(10)=>n303,b(9)=>n303,b(8)=>n303,b(7)=>n303,b(6)=>n303, + b(5)=>n303,b(4)=>n303,b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>pwr, + o=>n65); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(194) + n67 <= n65 and not_reset; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(194) + mux_29: entity work.mux_5(INTERFACE) port map (d0(4)=>pwr,d0(3)=>pwr, + d0(2)=>pwr,d0(1)=>pwr,d0(0)=>n303,d1(4)=>pwr,d1(3)=>pwr,d1(2)=>n303, + d1(1)=>pwr,d1(0)=>n303,cond=>n67,o(4)=>n68(4),o(3)=>n68(3), + o(2)=>n68(2),o(1)=>n68(1),o(0)=>n68(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(201) + n74 <= not dll_lock_q2; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(206) + n75 <= n74 or update; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(206) + mux_32: entity work.mux_5(INTERFACE) port map (d0(4)=>n303,d0(3)=>n303, + d0(2)=>n303,d0(1)=>pwr,d0(0)=>pwr,d1(4)=>n303,d1(3)=>n303,d1(2)=>n303, + d1(1)=>pwr,d1(0)=>n303,cond=>n75,o(4)=>n76(4),o(3)=>n76(3), + o(2)=>n76(2),o(1)=>n76(1),o(0)=>n76(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(213) + equal_33: entity work.equal_5(INTERFACE) port map (a(4)=>freeze_c,a(3)=>stop_c, + a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c,b(4)=>n303, + b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>n303,o=>n82); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(122) + equal_34: entity work.equal_5(INTERFACE) port map (a(4)=>freeze_c,a(3)=>stop_c, + a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c,b(4)=>pwr, + b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>n303,o=>n83); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(138) + equal_35: entity work.equal_5(INTERFACE) port map (a(4)=>freeze_c,a(3)=>stop_c, + a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c,b(4)=>pwr, + b(3)=>n303,b(2)=>n303,b(1)=>n303,b(0)=>n303,o=>n84); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(161) + equal_36: entity work.equal_5(INTERFACE) port map (a(4)=>freeze_c,a(3)=>stop_c, + a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c,b(4)=>pwr, + b(3)=>pwr,b(2)=>n303,b(1)=>pwr,b(0)=>n303,o=>n85); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(173) + equal_37: entity work.equal_5(INTERFACE) port map (a(4)=>freeze_c,a(3)=>stop_c, + a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c,b(4)=>pwr, + b(3)=>pwr,b(2)=>pwr,b(1)=>pwr,b(0)=>n303,o=>n86); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(192) + equal_38: entity work.equal_5(INTERFACE) port map (a(4)=>freeze_c,a(3)=>stop_c, + a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c,b(4)=>n303, + b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>pwr,o=>n87); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(204) + reduce_nor_39: entity work.reduce_nor_6(INTERFACE) port map (a(5)=>n82, + a(4)=>n83,a(3)=>n84,a(2)=>n85,a(1)=>n86,a(0)=>n87,o=>n88); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(221) + select_40: entity work.wide_select_7_35(INTERFACE) port map (sel(6)=>n82, + sel(5)=>n83,sel(4)=>n84,sel(3)=>n85,sel(2)=>n86,sel(1)=>n87, + sel(0)=>n88,data(34)=>n15(4),data(33)=>n15(3),data(32)=>n15(2), + data(31)=>n15(1),data(30)=>n15(0),data(29)=>n36(4),data(28)=>n36(3), + data(27)=>n36(2),data(26)=>n36(1),data(25)=>n36(0),data(24)=>n45(4), + data(23)=>n45(3),data(22)=>n45(2),data(21)=>n45(1),data(20)=>n45(0), + data(19)=>n59(4),data(18)=>n59(3),data(17)=>n59(2),data(16)=>n59(1), + data(15)=>n59(0),data(14)=>n68(4),data(13)=>n68(3),data(12)=>n68(2), + data(11)=>n68(1),data(10)=>n68(0),data(9)=>n76(4),data(8)=>n76(3), + data(7)=>n76(2),data(6)=>n76(1),data(5)=>n76(0),data(4)=>freeze_c, + data(3)=>stop_c,data(2)=>cs_rx_sync(2),data(1)=>uddcntln_c,data(0)=>ready_c, + o(4)=>ns_rx_sync(4),o(3)=>ns_rx_sync(3),o(2)=>ns_rx_sync(2),o(1)=>ns_rx_sync(1), + o(0)=>ns_rx_sync(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(221) + dll_lock_q2_112: VERIFIC_DFFRS (d=>dll_lock_q1,clk=>sync_clk,s=>n303, + r=>rst,q=>dll_lock_q2); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(238) + gnd <= '0' ; + n97 <= dll_lock_q2 and dll_lock; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(264) + LessThan_44: entity work.LessThan_3u_3u(INTERFACE) port map (cin=>n303, + a(2)=>dll_lock_cnt(2),a(1)=>dll_lock_cnt(1),a(0)=>dll_lock_cnt(0), + b(2)=>pwr,b(1)=>n303,b(0)=>pwr,o=>n98); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(264) + n99 <= n97 and n98; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(264) + add_46: entity work.add_32u_32u(INTERFACE) port map (cin=>n303,a(31)=>n303, + a(30)=>n303,a(29)=>n303,a(28)=>n303,a(27)=>n303,a(26)=>n303, + a(25)=>n303,a(24)=>n303,a(23)=>n303,a(22)=>n303,a(21)=>n303, + a(20)=>n303,a(19)=>n303,a(18)=>n303,a(17)=>n303,a(16)=>n303, + a(15)=>n303,a(14)=>n303,a(13)=>n303,a(12)=>n303,a(11)=>n303, + a(10)=>n303,a(9)=>n303,a(8)=>n303,a(7)=>n303,a(6)=>n303,a(5)=>n303, + a(4)=>n303,a(3)=>n303,a(2)=>dll_lock_cnt(2),a(1)=>dll_lock_cnt(1), + a(0)=>dll_lock_cnt(0),b(31)=>n303,b(30)=>n303,b(29)=>n303,b(28)=>n303, + b(27)=>n303,b(26)=>n303,b(25)=>n303,b(24)=>n303,b(23)=>n303, + b(22)=>n303,b(21)=>n303,b(20)=>n303,b(19)=>n303,b(18)=>n303, + b(17)=>n303,b(16)=>n303,b(15)=>n303,b(14)=>n303,b(13)=>n303, + b(12)=>n303,b(11)=>n303,b(10)=>n303,b(9)=>n303,b(8)=>n303,b(7)=>n303, + b(6)=>n303,b(5)=>n303,b(4)=>n303,b(3)=>n303,b(2)=>n303,b(1)=>n303, + b(0)=>pwr,o(31)=>OPEN_net(87),o(30)=>OPEN_net(86),o(29)=>OPEN_net(85), + o(28)=>OPEN_net(84),o(27)=>OPEN_net(83),o(26)=>OPEN_net(82),o(25)=>OPEN_net(81), + o(24)=>OPEN_net(80),o(23)=>OPEN_net(79),o(22)=>OPEN_net(78),o(21)=>OPEN_net(77), + o(20)=>OPEN_net(76),o(19)=>OPEN_net(75),o(18)=>OPEN_net(74),o(17)=>OPEN_net(73), + o(16)=>OPEN_net(72),o(15)=>OPEN_net(71),o(14)=>OPEN_net(70),o(13)=>OPEN_net(69), + o(12)=>OPEN_net(68),o(11)=>OPEN_net(67),o(10)=>OPEN_net(66),o(9)=>OPEN_net(65), + o(8)=>OPEN_net(64),o(7)=>OPEN_net(63),o(6)=>OPEN_net(62),o(5)=>OPEN_net(61), + o(4)=>OPEN_net(60),o(3)=>OPEN_net(59),o(2)=>n101(2),o(1)=>n101(1), + o(0)=>n101(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(266) + mux_47: entity work.mux_3(INTERFACE) port map (d0(2)=>dll_lock_cnt(2), + d0(1)=>dll_lock_cnt(1),d0(0)=>dll_lock_cnt(0),d1(2)=>n101(2), + d1(1)=>n101(1),d1(0)=>n101(0),cond=>n99,o(2)=>n134(2),o(1)=>n134(1), + o(0)=>n134(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(267) + not_equal_48: entity work.not_equal_32(INTERFACE) port map (a(31)=>n303, + a(30)=>n303,a(29)=>n303,a(28)=>n303,a(27)=>n303,a(26)=>n303, + a(25)=>n303,a(24)=>n303,a(23)=>n303,a(22)=>n303,a(21)=>n303, + a(20)=>n303,a(19)=>n303,a(18)=>n303,a(17)=>n303,a(16)=>n303, + a(15)=>n303,a(14)=>n303,a(13)=>n303,a(12)=>n303,a(11)=>n303, + a(10)=>n303,a(9)=>n303,a(8)=>n303,a(7)=>n303,a(6)=>n303,a(5)=>n303, + a(4)=>n303,a(3)=>n303,a(2)=>dll_lock_cnt(2),a(1)=>dll_lock_cnt(1), + a(0)=>dll_lock_cnt(0),b(31)=>n303,b(30)=>n303,b(29)=>n303,b(28)=>n303, + b(27)=>n303,b(26)=>n303,b(25)=>n303,b(24)=>n303,b(23)=>n303, + b(22)=>n303,b(21)=>n303,b(20)=>n303,b(19)=>n303,b(18)=>n303, + b(17)=>n303,b(16)=>n303,b(15)=>n303,b(14)=>n303,b(13)=>n303, + b(12)=>n303,b(11)=>n303,b(10)=>n303,b(9)=>n303,b(8)=>n303,b(7)=>n303, + b(6)=>n303,b(5)=>n303,b(4)=>n303,b(3)=>n303,b(2)=>pwr,b(1)=>n303, + b(0)=>pwr,o=>n138); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(271) + equal_49: entity work.equal_32(INTERFACE) port map (a(31)=>n303,a(30)=>n303, + a(29)=>n303,a(28)=>n303,a(27)=>n303,a(26)=>n303,a(25)=>n303, + a(24)=>n303,a(23)=>n303,a(22)=>n303,a(21)=>n303,a(20)=>n303, + a(19)=>n303,a(18)=>n303,a(17)=>n303,a(16)=>n303,a(15)=>n303, + a(14)=>n303,a(13)=>n303,a(12)=>n303,a(11)=>n303,a(10)=>n303, + a(9)=>n303,a(8)=>n303,a(7)=>n303,a(6)=>n303,a(5)=>n303,a(4)=>n303, + a(3)=>n303,a(2)=>ctrl_cnt(2),a(1)=>ctrl_cnt(1),a(0)=>ctrl_cnt(0), + b(31)=>n303,b(30)=>n303,b(29)=>n303,b(28)=>n303,b(27)=>n303, + b(26)=>n303,b(25)=>n303,b(24)=>n303,b(23)=>n303,b(22)=>n303, + b(21)=>n303,b(20)=>n303,b(19)=>n303,b(18)=>n303,b(17)=>n303, + b(16)=>n303,b(15)=>n303,b(14)=>n303,b(13)=>n303,b(12)=>n303, + b(11)=>n303,b(10)=>n303,b(9)=>n303,b(8)=>n303,b(7)=>n303,b(6)=>n303, + b(5)=>n303,b(4)=>n303,b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>pwr, + o=>n139); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(275) + not_equal_50: entity work.not_equal_5(INTERFACE) port map (a(4)=>freeze_c, + a(3)=>stop_c,a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c, + b(4)=>n303,b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>pwr,o=>n140); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(275) + n141 <= n139 and n140; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(275) + LessThan_52: entity work.LessThan_3u_3u(INTERFACE) port map (cin=>n303, + a(2)=>ctrl_cnt(2),a(1)=>ctrl_cnt(1),a(0)=>ctrl_cnt(0),b(2)=>pwr, + b(1)=>n303,b(0)=>n303,o=>n142); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(280) + add_53: entity work.add_32u_32u(INTERFACE) port map (cin=>n303,a(31)=>n303, + a(30)=>n303,a(29)=>n303,a(28)=>n303,a(27)=>n303,a(26)=>n303, + a(25)=>n303,a(24)=>n303,a(23)=>n303,a(22)=>n303,a(21)=>n303, + a(20)=>n303,a(19)=>n303,a(18)=>n303,a(17)=>n303,a(16)=>n303, + a(15)=>n303,a(14)=>n303,a(13)=>n303,a(12)=>n303,a(11)=>n303, + a(10)=>n303,a(9)=>n303,a(8)=>n303,a(7)=>n303,a(6)=>n303,a(5)=>n303, + a(4)=>n303,a(3)=>n303,a(2)=>ctrl_cnt(2),a(1)=>ctrl_cnt(1),a(0)=>ctrl_cnt(0), + b(31)=>n303,b(30)=>n303,b(29)=>n303,b(28)=>n303,b(27)=>n303, + b(26)=>n303,b(25)=>n303,b(24)=>n303,b(23)=>n303,b(22)=>n303, + b(21)=>n303,b(20)=>n303,b(19)=>n303,b(18)=>n303,b(17)=>n303, + b(16)=>n303,b(15)=>n303,b(14)=>n303,b(13)=>n303,b(12)=>n303, + b(11)=>n303,b(10)=>n303,b(9)=>n303,b(8)=>n303,b(7)=>n303,b(6)=>n303, + b(5)=>n303,b(4)=>n303,b(3)=>n303,b(2)=>n303,b(1)=>n303,b(0)=>pwr, + o(31)=>OPEN_net(58),o(30)=>OPEN_net(57),o(29)=>OPEN_net(56),o(28)=>OPEN_net(55), + o(27)=>OPEN_net(54),o(26)=>OPEN_net(53),o(25)=>OPEN_net(52),o(24)=>OPEN_net(51), + o(23)=>OPEN_net(50),o(22)=>OPEN_net(49),o(21)=>OPEN_net(48),o(20)=>OPEN_net(47), + o(19)=>OPEN_net(46),o(18)=>OPEN_net(45),o(17)=>OPEN_net(44),o(16)=>OPEN_net(43), + o(15)=>OPEN_net(42),o(14)=>OPEN_net(41),o(13)=>OPEN_net(40),o(12)=>OPEN_net(39), + o(11)=>OPEN_net(38),o(10)=>OPEN_net(37),o(9)=>OPEN_net(36),o(8)=>OPEN_net(35), + o(7)=>OPEN_net(34),o(6)=>OPEN_net(33),o(5)=>OPEN_net(32),o(4)=>OPEN_net(31), + o(3)=>OPEN_net(30),o(2)=>n144(2),o(1)=>n144(1),o(0)=>n144(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(282) + mux_54: entity work.mux_3(INTERFACE) port map (d0(2)=>ctrl_cnt(2),d0(1)=>ctrl_cnt(1), + d0(0)=>ctrl_cnt(0),d1(2)=>n144(2),d1(1)=>n144(1),d1(0)=>n144(0), + cond=>n142,o(2)=>n177(2),o(1)=>n177(1),o(0)=>n177(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(283) + mux_55: entity work.mux_3(INTERFACE) port map (d0(2)=>n177(2),d0(1)=>n177(1), + d0(0)=>n177(0),d1(2)=>n303,d1(1)=>n303,d1(0)=>n303,cond=>n141, + o(2)=>n181(2),o(1)=>n181(1),o(0)=>n181(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(283) + mux_56: entity work.mux_3(INTERFACE) port map (d0(2)=>n181(2),d0(1)=>n181(1), + d0(0)=>n181(0),d1(2)=>n303,d1(1)=>pwr,d1(0)=>pwr,cond=>n138, + o(2)=>n185(2),o(1)=>n185(1),o(0)=>n185(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(283) + LessThan_57: entity work.LessThan_3u_3u(INTERFACE) port map (cin=>n303, + a(2)=>ready_cnt(2),a(1)=>ready_cnt(1),a(0)=>ready_cnt(0),b(2)=>pwr, + b(1)=>pwr,b(0)=>pwr,o=>n189); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(287) + n190 <= get_ready and n189; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(287) + add_59: entity work.add_32u_32u(INTERFACE) port map (cin=>n303,a(31)=>n303, + a(30)=>n303,a(29)=>n303,a(28)=>n303,a(27)=>n303,a(26)=>n303, + a(25)=>n303,a(24)=>n303,a(23)=>n303,a(22)=>n303,a(21)=>n303, + a(20)=>n303,a(19)=>n303,a(18)=>n303,a(17)=>n303,a(16)=>n303, + a(15)=>n303,a(14)=>n303,a(13)=>n303,a(12)=>n303,a(11)=>n303, + a(10)=>n303,a(9)=>n303,a(8)=>n303,a(7)=>n303,a(6)=>n303,a(5)=>n303, + a(4)=>n303,a(3)=>n303,a(2)=>ready_cnt(2),a(1)=>ready_cnt(1), + a(0)=>ready_cnt(0),b(31)=>n303,b(30)=>n303,b(29)=>n303,b(28)=>n303, + b(27)=>n303,b(26)=>n303,b(25)=>n303,b(24)=>n303,b(23)=>n303, + b(22)=>n303,b(21)=>n303,b(20)=>n303,b(19)=>n303,b(18)=>n303, + b(17)=>n303,b(16)=>n303,b(15)=>n303,b(14)=>n303,b(13)=>n303, + b(12)=>n303,b(11)=>n303,b(10)=>n303,b(9)=>n303,b(8)=>n303,b(7)=>n303, + b(6)=>n303,b(5)=>n303,b(4)=>n303,b(3)=>n303,b(2)=>n303,b(1)=>n303, + b(0)=>pwr,o(31)=>OPEN_net(29),o(30)=>OPEN_net(28),o(29)=>OPEN_net(27), + o(28)=>OPEN_net(26),o(27)=>OPEN_net(25),o(26)=>OPEN_net(24),o(25)=>OPEN_net(23), + o(24)=>OPEN_net(22),o(23)=>OPEN_net(21),o(22)=>OPEN_net(20),o(21)=>OPEN_net(19), + o(20)=>OPEN_net(18),o(19)=>OPEN_net(17),o(18)=>OPEN_net(16),o(17)=>OPEN_net(15), + o(16)=>OPEN_net(14),o(15)=>OPEN_net(13),o(14)=>OPEN_net(12),o(13)=>OPEN_net(11), + o(12)=>OPEN_net(10),o(11)=>OPEN_net(9),o(10)=>OPEN_net(8),o(9)=>OPEN_net(7), + o(8)=>OPEN_net(6),o(7)=>OPEN_net(5),o(6)=>OPEN_net(4),o(5)=>OPEN_net(3), + o(4)=>OPEN_net(2),o(3)=>OPEN_net(1),o(2)=>n192(2),o(1)=>n192(1), + o(0)=>n192(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(290) + mux_60: entity work.mux_3(INTERFACE) port map (d0(2)=>ready_cnt(2),d0(1)=>ready_cnt(1), + d0(0)=>ready_cnt(0),d1(2)=>n192(2),d1(1)=>n192(1),d1(0)=>n192(0), + cond=>n190,o(2)=>n225(2),o(1)=>n225(1),o(0)=>n225(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(291) + equal_61: entity work.equal_5(INTERFACE) port map (a(4)=>freeze_c,a(3)=>stop_c, + a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c,b(4)=>pwr, + b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>n303,o=>n229); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(294) + equal_62: entity work.equal_5(INTERFACE) port map (a(4)=>ns_rx_sync(4), + a(3)=>ns_rx_sync(3),a(2)=>ns_rx_sync(2),a(1)=>ns_rx_sync(1),a(0)=>ns_rx_sync(0), + b(4)=>pwr,b(3)=>n303,b(2)=>n303,b(1)=>n303,b(0)=>n303,o=>n230); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(294) + n231 <= n229 and n230; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(294) + n232 <= pwr when n231='1' else not_uddcntln; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(297) + equal_65: entity work.equal_5(INTERFACE) port map (a(4)=>freeze_c,a(3)=>stop_c, + a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c,b(4)=>pwr, + b(3)=>n303,b(2)=>n303,b(1)=>n303,b(0)=>n303,o=>n233); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(300) + equal_66: entity work.equal_5(INTERFACE) port map (a(4)=>ns_rx_sync(4), + a(3)=>ns_rx_sync(3),a(2)=>ns_rx_sync(2),a(1)=>ns_rx_sync(1),a(0)=>ns_rx_sync(0), + b(4)=>pwr,b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>n303,o=>n234); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(300) + n235 <= n233 and n234; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(300) + n236 <= pwr when n235='1' else assert_stop; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(303) + equal_69: entity work.equal_5(INTERFACE) port map (a(4)=>freeze_c,a(3)=>stop_c, + a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c,b(4)=>pwr, + b(3)=>pwr,b(2)=>n303,b(1)=>pwr,b(0)=>n303,o=>n237); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(306) + equal_70: entity work.equal_5(INTERFACE) port map (a(4)=>ns_rx_sync(4), + a(3)=>ns_rx_sync(3),a(2)=>ns_rx_sync(2),a(1)=>ns_rx_sync(1),a(0)=>ns_rx_sync(0), + b(4)=>pwr,b(3)=>pwr,b(2)=>pwr,b(1)=>pwr,b(0)=>n303,o=>n238); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(306) + n239 <= n237 and n238; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(306) + n240 <= pwr when n239='1' else not_reset; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(309) + equal_73: entity work.equal_5(INTERFACE) port map (a(4)=>freeze_c,a(3)=>stop_c, + a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c,b(4)=>pwr, + b(3)=>pwr,b(2)=>pwr,b(1)=>pwr,b(0)=>n303,o=>n241); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(312) + equal_74: entity work.equal_5(INTERFACE) port map (a(4)=>ns_rx_sync(4), + a(3)=>ns_rx_sync(3),a(2)=>ns_rx_sync(2),a(1)=>ns_rx_sync(1),a(0)=>ns_rx_sync(0), + b(4)=>pwr,b(3)=>pwr,b(2)=>n303,b(1)=>pwr,b(0)=>n303,o=>n242); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(312) + n243 <= n241 and n242; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(312) + n244 <= pwr when n243='1' else not_stop; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(315) + equal_77: entity work.equal_5(INTERFACE) port map (a(4)=>freeze_c,a(3)=>stop_c, + a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c,b(4)=>pwr, + b(3)=>pwr,b(2)=>n303,b(1)=>pwr,b(0)=>n303,o=>n245); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(318) + equal_78: entity work.equal_5(INTERFACE) port map (a(4)=>ns_rx_sync(4), + a(3)=>ns_rx_sync(3),a(2)=>ns_rx_sync(2),a(1)=>ns_rx_sync(1),a(0)=>ns_rx_sync(0), + b(4)=>pwr,b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>n303,o=>n246); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(318) + n247 <= n245 and n246; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(318) + n248 <= pwr when n247='1' else not_freeze; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(322) + n249 <= n303 when n247='1' else n236; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(322) + equal_82: entity work.equal_5(INTERFACE) port map (a(4)=>freeze_c,a(3)=>stop_c, + a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c,b(4)=>pwr, + b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>n303,o=>n250); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(325) + equal_83: entity work.equal_5(INTERFACE) port map (a(4)=>ns_rx_sync(4), + a(3)=>ns_rx_sync(3),a(2)=>ns_rx_sync(2),a(1)=>ns_rx_sync(1),a(0)=>ns_rx_sync(0), + b(4)=>n303,b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>n303,o=>n251); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(325) + n252 <= n250 and n251; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(325) + n253 <= pwr when n252='1' else get_ready; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(328) + equal_86: entity work.equal_5(INTERFACE) port map (a(4)=>freeze_c,a(3)=>stop_c, + a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c,b(4)=>n303, + b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>pwr,o=>n254); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(332) + equal_87: entity work.equal_5(INTERFACE) port map (a(4)=>ns_rx_sync(4), + a(3)=>ns_rx_sync(3),a(2)=>ns_rx_sync(2),a(1)=>ns_rx_sync(1),a(0)=>ns_rx_sync(0), + b(4)=>n303,b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>n303,o=>n255); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(332) + n256 <= n254 and n255; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(332) + n257 <= n303 when n256='1' else n248; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(344) + n258 <= n303 when n256='1' else n249; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(344) + n259 <= n303 when n256='1' else n244; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(344) + n260 <= n303 when n256='1' else n240; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(344) + n261 <= n303 when n256='1' else n232; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(344) + n262 <= n303 when n256='1' else n253; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(344) + mux_95: entity work.mux_3(INTERFACE) port map (d0(2)=>n225(2),d0(1)=>n225(1), + d0(0)=>n225(0),d1(2)=>n303,d1(1)=>n303,d1(0)=>n303,cond=>n256, + o(2)=>n263(2),o(1)=>n263(1),o(0)=>n263(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(344) + mux_96: entity work.mux_3(INTERFACE) port map (d0(2)=>n134(2),d0(1)=>n134(1), + d0(0)=>n134(0),d1(2)=>n303,d1(1)=>n303,d1(0)=>n303,cond=>n256, + o(2)=>n267(2),o(1)=>n267(1),o(0)=>n267(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(344) + mux_97: entity work.mux_3(INTERFACE) port map (d0(2)=>n185(2),d0(1)=>n185(1), + d0(0)=>n185(0),d1(2)=>n303,d1(1)=>n303,d1(0)=>n303,cond=>n256, + o(2)=>n271(2),o(1)=>n271(1),o(0)=>n271(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(344) + ctrl_cnt_c: entity work.wide_dffrs_3(INTERFACE) port map (d(2)=>n271(2), + d(1)=>n271(1),d(0)=>n271(0),set(2)=>n303,set(1)=>n303,set(0)=>n303, + reset(2)=>rst,reset(1)=>rst,reset(0)=>rst,clock=>sync_clk,q(2)=>ctrl_cnt(2), + q(1)=>ctrl_cnt(1),q(0)=>ctrl_cnt(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(346) + dll_lock_cnt_c: entity work.wide_dffrs_3(INTERFACE) port map (d(2)=>n267(2), + d(1)=>n267(1),d(0)=>n267(0),set(2)=>n303,set(1)=>n303,set(0)=>n303, + reset(2)=>rst,reset(1)=>rst,reset(0)=>rst,clock=>sync_clk,q(2)=>dll_lock_cnt(2), + q(1)=>dll_lock_cnt(1),q(0)=>dll_lock_cnt(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(346) + ready_cnt_c: entity work.wide_dffrs_3(INTERFACE) port map (d(2)=>n263(2), + d(1)=>n263(1),d(0)=>n263(0),set(2)=>n303,set(1)=>n303,set(0)=>n303, + reset(2)=>rst,reset(1)=>rst,reset(0)=>rst,clock=>sync_clk,q(2)=>ready_cnt(2), + q(1)=>ready_cnt(1),q(0)=>ready_cnt(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(346) + ddr_reset_d_118: VERIFIC_DFFRS (d=>n303,clk=>sync_clk,s=>rst,r=>gnd, + q=>ddr_reset_d); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(346) + dll_reset_119: VERIFIC_DFFRS (d=>n256,clk=>sync_clk,s=>rst,r=>gnd,q=>dll_reset_c); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(346) + not_uddcntln_120: VERIFIC_DFFRS (d=>n261,clk=>sync_clk,s=>n303,r=>rst, + q=>not_uddcntln); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(346) + assert_stop_121: VERIFIC_DFFRS (d=>n258,clk=>sync_clk,s=>n303,r=>rst, + q=>assert_stop); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(346) + not_reset_122: VERIFIC_DFFRS (d=>n260,clk=>sync_clk,s=>n303,r=>rst,q=>not_reset); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(346) + not_stop_123: VERIFIC_DFFRS (d=>n259,clk=>sync_clk,s=>n303,r=>rst,q=>not_stop); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(346) + not_freeze_124: VERIFIC_DFFRS (d=>n257,clk=>sync_clk,s=>n303,r=>rst, + q=>not_freeze); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(346) + get_ready_125: VERIFIC_DFFRS (d=>n262,clk=>sync_clk,s=>n303,r=>rst,q=>get_ready); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(346) + dll_lock_q1_111: VERIFIC_DFFRS (d=>dll_lock,clk=>sync_clk,s=>n303,r=>rst, + q=>dll_lock_q1); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(238) + cs_rx_sync_c: entity work.wide_dffrs_5(INTERFACE) port map (d(4)=>ns_rx_sync(4), + d(3)=>ns_rx_sync(3),d(2)=>ns_rx_sync(2),d(1)=>ns_rx_sync(1),d(0)=>ns_rx_sync(0), + set(4)=>n303,set(3)=>n303,set(2)=>n303,set(1)=>rst,set(0)=>n303, + reset(4)=>rst,reset(3)=>rst,reset(2)=>rst,reset(1)=>gnd,reset(0)=>rst, + clock=>sync_clk,q(4)=>freeze_c,q(3)=>stop_c,q(2)=>cs_rx_sync(2), + q(1)=>uddcntln_c,q(0)=>ready_c); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(346) + +end architecture input_4chrxdll_sync; -- syn_module_defined=1 -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(25) + + +library IEEE; +use IEEE.std_logic_1164.all; +library ecp5um; +use ecp5um.components.all; + +entity input_4ch is + port ( + alignwd: in std_logic; + clkin: in std_logic; + dcntl: out std_logic_vector(7 downto 0); + ready: out std_logic; + sclk: out std_logic; + sync_clk: in std_logic; + sync_reset: in std_logic; + update: in std_logic; + datain: in std_logic_vector(4 downto 0); + q: out std_logic_vector(19 downto 0)); +end input_4ch; + +architecture Structure of input_4ch is + + -- internal signal declarations + signal stop: std_logic; + signal scuba_vlo: std_logic; + signal dll_lock: std_logic; + signal freeze: std_logic; + signal uddcntln: std_logic; + signal dll_reset: std_logic; + signal clock_cflag: std_logic; + signal eclki: std_logic; + signal clock_direction: std_logic; + signal clock_move: std_logic; + signal clock_loadn: std_logic; + signal ddrdel: std_logic; + signal buf_clkin: std_logic; + signal qa4: std_logic; + signal qb4: std_logic; + signal qc4: std_logic; + signal qd4: std_logic; + signal qa3: std_logic; + signal qb3: std_logic; + signal qc3: std_logic; + signal qd3: std_logic; + signal qa2: std_logic; + signal qb2: std_logic; + signal qc2: std_logic; + signal qd2: std_logic; + signal qa1: std_logic; + signal qb1: std_logic; + signal qc1: std_logic; + signal qd1: std_logic; + signal qa0: std_logic; + signal qb0: std_logic; + signal qc0: std_logic; + signal qd0: std_logic; + signal reset: std_logic; + signal eclko: std_logic; + signal sclk_t: std_logic; + signal dataini_t4: std_logic; + signal dataini_t3: std_logic; + signal dataini_t2: std_logic; + signal dataini_t1: std_logic; + signal dataini_t0: std_logic; + signal buf_dataini4: std_logic; + signal buf_dataini3: std_logic; + signal buf_dataini2: std_logic; + signal buf_dataini1: std_logic; + signal buf_dataini0: std_logic; + + component input_4chrxdll_sync + port (rst: in std_logic; sync_clk: in std_logic; + update: in std_logic; dll_lock: in std_logic; + dll_reset: out std_logic; uddcntln: out std_logic; + freeze: out std_logic; stop: out std_logic; + ddr_reset: out std_logic; ready: out std_logic); + end component; + attribute IO_TYPE : string; + -- attribute IO_TYPE of Inst7_IB : label is "LVDS"; + attribute IO_TYPE of Inst1_IB4 : label is "LVDS"; + attribute IO_TYPE of Inst1_IB3 : label is "LVDS"; + attribute IO_TYPE of Inst1_IB2 : label is "LVDS"; + attribute IO_TYPE of Inst1_IB1 : label is "LVDS"; + attribute IO_TYPE of Inst1_IB0 : label is "LVDS"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + -- Inst7_IB: IB + -- port map (I=>clkin, O=>buf_clkin); + + Inst6_CLKDIVF: CLKDIVF + generic map (DIV=> "2.0") + port map (CLKI=>eclko, RST=>reset, ALIGNWD=>alignwd, + CDIVX=>sclk_t); +eclko <= clkin; + -- Inst5_ECLKSYNCB: ECLKSYNCB + -- port map (ECLKI=>eclki, STOP=>stop, ECLKO=>eclko); + -- + -- Inst_rxdll_sync: input_4chrxdll_sync + -- port map (rst => sync_reset, sync_clk => sync_clk, update => update, + -- dll_lock => dll_lock, dll_reset => dll_reset, uddcntln => uddcntln, + -- freeze => freeze, stop => stop, ddr_reset => reset, + -- ready => ready); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + -- Inst4_DDRDLLA: DDRDLLA + -- generic map (FORCE_MAX_DELAY=> "NO") + -- port map (CLK=>eclko, RST=>dll_reset, UDDCNTLN=>uddcntln, + -- FREEZE=>freeze, DDRDEL=>ddrdel, LOCK=>dll_lock, + -- DCNTL7=>dcntl(7), DCNTL6=>dcntl(6), DCNTL5=>dcntl(5), + -- DCNTL4=>dcntl(4), DCNTL3=>dcntl(3), DCNTL2=>dcntl(2), + -- DCNTL1=>dcntl(1), DCNTL0=>dcntl(0)); + + Inst3_DLLDELD: DLLDELD + port map (A=>buf_clkin, DDRDEL=>ddrdel, LOADN=>clock_loadn, + MOVE=>clock_move, DIRECTION=>clock_direction, Z=>eclki, + CFLAG=>clock_cflag); + + Inst2_IDDRX2F4: IDDRX2F + port map (D=>dataini_t4, SCLK=>sclk_t, ECLK=>eclko, RST=>reset, + ALIGNWD=>alignwd, Q3=>qd4, Q2=>qc4, Q1=>qb4, Q0=>qa4); + + Inst2_IDDRX2F3: IDDRX2F + port map (D=>dataini_t3, SCLK=>sclk_t, ECLK=>eclko, RST=>reset, + ALIGNWD=>alignwd, Q3=>qd3, Q2=>qc3, Q1=>qb3, Q0=>qa3); + + Inst2_IDDRX2F2: IDDRX2F + port map (D=>dataini_t2, SCLK=>sclk_t, ECLK=>eclko, RST=>reset, + ALIGNWD=>alignwd, Q3=>qd2, Q2=>qc2, Q1=>qb2, Q0=>qa2); + + Inst2_IDDRX2F1: IDDRX2F + port map (D=>dataini_t1, SCLK=>sclk_t, ECLK=>eclko, RST=>reset, + ALIGNWD=>alignwd, Q3=>qd1, Q2=>qc1, Q1=>qb1, Q0=>qa1); + + Inst2_IDDRX2F0: IDDRX2F + port map (D=>dataini_t0, SCLK=>sclk_t, ECLK=>eclko, RST=>reset, + ALIGNWD=>alignwd, Q3=>qd0, Q2=>qc0, Q1=>qb0, Q0=>qa0); + + udel_dataini4: DELAYG + generic map (DEL_VALUE=> 59, DEL_MODE=> "USER_DEFINED") + port map (A=>buf_dataini4, Z=>dataini_t4); + + udel_dataini3: DELAYG + generic map (DEL_VALUE=> 59, DEL_MODE=> "USER_DEFINED") + port map (A=>buf_dataini3, Z=>dataini_t3); + + udel_dataini2: DELAYG + generic map (DEL_VALUE=> 59, DEL_MODE=> "USER_DEFINED") + port map (A=>buf_dataini2, Z=>dataini_t2); + + udel_dataini1: DELAYG + generic map (DEL_VALUE=> 59, DEL_MODE=> "USER_DEFINED") + port map (A=>buf_dataini1, Z=>dataini_t1); + + udel_dataini0: DELAYG + generic map (DEL_VALUE=> 59, DEL_MODE=> "USER_DEFINED") + port map (A=>buf_dataini0, Z=>dataini_t0); + + Inst1_IB4: IB + port map (I=>datain(4), O=>buf_dataini4); + + Inst1_IB3: IB + port map (I=>datain(3), O=>buf_dataini3); + + Inst1_IB2: IB + port map (I=>datain(2), O=>buf_dataini2); + + Inst1_IB1: IB + port map (I=>datain(1), O=>buf_dataini1); + + Inst1_IB0: IB + port map (I=>datain(0), O=>buf_dataini0); + + sclk <= sclk_t; + q(19) <= qd4; + q(18) <= qc4; + q(17) <= qb4; + q(16) <= qa4; + q(15) <= qd3; + q(14) <= qc3; + q(13) <= qb3; + q(12) <= qa3; + q(11) <= qd2; + q(10) <= qc2; + q(9) <= qb2; + q(8) <= qa2; + q(7) <= qd1; + q(6) <= qc1; + q(5) <= qb1; + q(4) <= qa1; + q(3) <= qd0; + q(2) <= qc0; + q(1) <= qb0; + q(0) <= qa0; + clock_direction <= scuba_vlo; + clock_move <= scuba_vlo; + clock_loadn <= uddcntln; +end Structure; diff --git a/adc/cores/input_4ch/input_4ch_edited.vhd b/adc/cores/input_4ch/input_4ch_edited.vhd new file mode 100644 index 0000000..5a3aab4 --- /dev/null +++ b/adc/cores/input_4ch/input_4ch_edited.vhd @@ -0,0 +1,1327 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 +-- Module Version: 5.8 +--/d/jspc29/lattice/diamond/3.12/ispfpga/bin/lin64/scuba -w -n input_4ch -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type iol -mode Receive -io_type LVDS -width 5 -freq_in 350 -gear 4 -aligned -del 59 -data_lane + +-- Tue Apr 30 11:23:01 2024 + + + +-- +-- Verific VHDL Description of OPERATOR equal_32 +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +entity equal_32 is + port (a: in std_logic_vector(31 downto 0); + b: in std_logic_vector(31 downto 0); + o: out std_logic + ); + +end entity equal_32; + +architecture INTERFACE of equal_32 is + signal n1,n2,n3,n4,n5,n6,n7,n8,n9,n10,n11,n12,n13,n14,n15, + n16,n17,n18,n19,n20,n21,n22,n23,n24,n25,n26,n27,n28,n29, + n30,n31,n32,n33,n34,n35,n36,n37,n38,n39,n40,n41,n42,n43, + n44,n45,n46,n47,n48,n49,n50,n51,n52,n53,n54,n55,n56,n57, + n58,n59,n60,n61,n62,n63 : std_logic; +begin + n1 <= a(0) xor b(0); + n2 <= a(1) xor b(1); + n3 <= a(2) xor b(2); + n4 <= a(3) xor b(3); + n5 <= a(4) xor b(4); + n6 <= a(5) xor b(5); + n7 <= a(6) xor b(6); + n8 <= a(7) xor b(7); + n9 <= a(8) xor b(8); + n10 <= a(9) xor b(9); + n11 <= a(10) xor b(10); + n12 <= a(11) xor b(11); + n13 <= a(12) xor b(12); + n14 <= a(13) xor b(13); + n15 <= a(14) xor b(14); + n16 <= a(15) xor b(15); + n17 <= a(16) xor b(16); + n18 <= a(17) xor b(17); + n19 <= a(18) xor b(18); + n20 <= a(19) xor b(19); + n21 <= a(20) xor b(20); + n22 <= a(21) xor b(21); + n23 <= a(22) xor b(22); + n24 <= a(23) xor b(23); + n25 <= a(24) xor b(24); + n26 <= a(25) xor b(25); + n27 <= a(26) xor b(26); + n28 <= a(27) xor b(27); + n29 <= a(28) xor b(28); + n30 <= a(29) xor b(29); + n31 <= a(30) xor b(30); + n32 <= a(31) xor b(31); + n33 <= n1 or n2; + n34 <= n3 or n4; + n35 <= n33 or n34; + n36 <= n5 or n6; + n37 <= n7 or n8; + n38 <= n36 or n37; + n39 <= n35 or n38; + n40 <= n9 or n10; + n41 <= n11 or n12; + n42 <= n40 or n41; + n43 <= n13 or n14; + n44 <= n15 or n16; + n45 <= n43 or n44; + n46 <= n42 or n45; + n47 <= n39 or n46; + n48 <= n17 or n18; + n49 <= n19 or n20; + n50 <= n48 or n49; + n51 <= n21 or n22; + n52 <= n23 or n24; + n53 <= n51 or n52; + n54 <= n50 or n53; + n55 <= n25 or n26; + n56 <= n27 or n28; + n57 <= n55 or n56; + n58 <= n29 or n30; + n59 <= n31 or n32; + n60 <= n58 or n59; + n61 <= n57 or n60; + n62 <= n54 or n61; + n63 <= n47 or n62; + o <= not n63; + +end architecture INTERFACE; + + +-- +-- Verific VHDL Description of OPERATOR mux_5 +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +entity mux_5 is + port (d0: in std_logic_vector(4 downto 0); + d1: in std_logic_vector(4 downto 0); + cond: in std_logic; + o: out std_logic_vector(4 downto 0) + ); + +end entity mux_5; + +architecture INTERFACE of mux_5 is + +begin + o(0) <= d1(0) when cond='1' else d0(0); + o(1) <= d1(1) when cond='1' else d0(1); + o(2) <= d1(2) when cond='1' else d0(2); + o(3) <= d1(3) when cond='1' else d0(3); + o(4) <= d1(4) when cond='1' else d0(4); + +end architecture INTERFACE; + + +-- +-- Verific VHDL Description of OPERATOR equal_5 +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +entity equal_5 is + port (a: in std_logic_vector(4 downto 0); + b: in std_logic_vector(4 downto 0); + o: out std_logic + ); + +end entity equal_5; + +architecture INTERFACE of equal_5 is + signal n1,n2,n3,n4,n5,n6,n7,n8,n9 : std_logic; +begin + n1 <= a(0) xor b(0); + n2 <= a(1) xor b(1); + n3 <= a(2) xor b(2); + n4 <= a(3) xor b(3); + n5 <= a(4) xor b(4); + n6 <= n1 or n2; + n7 <= n4 or n5; + n8 <= n3 or n7; + n9 <= n6 or n8; + o <= not n9; + +end architecture INTERFACE; + + +-- +-- Verific VHDL Description of OPERATOR reduce_nor_6 +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +entity reduce_nor_6 is + port (a: in std_logic_vector(5 downto 0); + o: out std_logic + ); + +end entity reduce_nor_6; + +architecture INTERFACE of reduce_nor_6 is + signal n1,n2,n3,n4,n5 : std_logic; +begin + n1 <= a(1) or a(2); + n2 <= a(0) or n1; + n3 <= a(4) or a(5); + n4 <= a(3) or n3; + n5 <= n2 or n4; + o <= not n5; + +end architecture INTERFACE; + + +-- +-- Verific VHDL Description of OPERATOR Select_7 +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +entity Select_7 is + port (sel: in std_logic_vector(6 downto 0); + data: in std_logic_vector(6 downto 0); + o: out std_logic + ); + +end entity Select_7; + +architecture INTERFACE of Select_7 is + signal n1,n2,n3,n4,n5,n6,n7,n8,n9,n10,n11,n12 : std_logic; +begin + n1 <= data(0) and sel(0); + n2 <= data(1) and sel(1); + n3 <= data(2) and sel(2); + n4 <= data(3) and sel(3); + n5 <= data(4) and sel(4); + n6 <= data(5) and sel(5); + n7 <= data(6) and sel(6); + n8 <= n2 or n3; + n9 <= n1 or n8; + n10 <= n4 or n5; + n11 <= n6 or n7; + n12 <= n10 or n11; + o <= n9 or n12; + +end architecture INTERFACE; + + +-- +-- Verific VHDL Description of OPERATOR wide_select_7_35 +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +entity wide_select_7_35 is + port (sel: in std_logic_vector(6 downto 0); + data: in std_logic_vector(34 downto 0); + o: out std_logic_vector(4 downto 0) + ); + +end entity wide_select_7_35; + +architecture INTERFACE of wide_select_7_35 is + +begin + Select_0: entity work.Select_7(INTERFACE) port map (sel(6)=>sel(6),sel(5)=>sel(5), + sel(4)=>sel(4),sel(3)=>sel(3),sel(2)=>sel(2),sel(1)=>sel(1), + sel(0)=>sel(0),data(6)=>data(30),data(5)=>data(25),data(4)=>data(20), + data(3)=>data(15),data(2)=>data(10),data(1)=>data(5),data(0)=>data(0), + o=>o(0)); + Select_1: entity work.Select_7(INTERFACE) port map (sel(6)=>sel(6),sel(5)=>sel(5), + sel(4)=>sel(4),sel(3)=>sel(3),sel(2)=>sel(2),sel(1)=>sel(1), + sel(0)=>sel(0),data(6)=>data(31),data(5)=>data(26),data(4)=>data(21), + data(3)=>data(16),data(2)=>data(11),data(1)=>data(6),data(0)=>data(1), + o=>o(1)); + Select_2: entity work.Select_7(INTERFACE) port map (sel(6)=>sel(6),sel(5)=>sel(5), + sel(4)=>sel(4),sel(3)=>sel(3),sel(2)=>sel(2),sel(1)=>sel(1), + sel(0)=>sel(0),data(6)=>data(32),data(5)=>data(27),data(4)=>data(22), + data(3)=>data(17),data(2)=>data(12),data(1)=>data(7),data(0)=>data(2), + o=>o(2)); + Select_3: entity work.Select_7(INTERFACE) port map (sel(6)=>sel(6),sel(5)=>sel(5), + sel(4)=>sel(4),sel(3)=>sel(3),sel(2)=>sel(2),sel(1)=>sel(1), + sel(0)=>sel(0),data(6)=>data(33),data(5)=>data(28),data(4)=>data(23), + data(3)=>data(18),data(2)=>data(13),data(1)=>data(8),data(0)=>data(3), + o=>o(3)); + Select_4: entity work.Select_7(INTERFACE) port map (sel(6)=>sel(6),sel(5)=>sel(5), + sel(4)=>sel(4),sel(3)=>sel(3),sel(2)=>sel(2),sel(1)=>sel(1), + sel(0)=>sel(0),data(6)=>data(34),data(5)=>data(29),data(4)=>data(24), + data(3)=>data(19),data(2)=>data(14),data(1)=>data(9),data(0)=>data(4), + o=>o(4)); + +end architecture INTERFACE; + + +-- +-- Verific VHDL Description of OPERATOR LessThan_3u_3u +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +entity LessThan_3u_3u is + port (cin: in std_logic; + a: in std_logic_vector(2 downto 0); + b: in std_logic_vector(2 downto 0); + o: out std_logic + ); + +end entity LessThan_3u_3u; + +architecture INTERFACE of LessThan_3u_3u is + signal n1,n2,n3,n4,n5 : std_logic; +begin + n1 <= a(0) xor b(0); + n2 <= b(0) when n1='1' else cin; + n3 <= a(1) xor b(1); + n4 <= b(1) when n3='1' else n2; + n5 <= a(2) xor b(2); + o <= b(2) when n5='1' else n4; + +end architecture INTERFACE; + + +-- +-- Verific VHDL Description of OPERATOR add_32u_32u +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +entity add_32u_32u is + port (cin: in std_logic; + a: in std_logic_vector(31 downto 0); + b: in std_logic_vector(31 downto 0); + o: out std_logic_vector(31 downto 0); + cout: out std_logic + ); + +end entity add_32u_32u; + +architecture INTERFACE of add_32u_32u is + signal n2,n4,n6,n8,n10,n12,n14,n16,n18,n20,n22,n24,n26,n28, + n30,n32,n34,n36,n38,n40,n42,n44,n46,n48,n50,n52,n54,n56, + n58,n60,n62 : std_logic; +begin + n2 <= a(0) or b(0) when cin='1' else a(0) and b(0); + o(0) <= a(0) xor b(0) xor cin; + n4 <= a(1) or b(1) when n2='1' else a(1) and b(1); + o(1) <= a(1) xor b(1) xor n2; + n6 <= a(2) or b(2) when n4='1' else a(2) and b(2); + o(2) <= a(2) xor b(2) xor n4; + n8 <= a(3) or b(3) when n6='1' else a(3) and b(3); + o(3) <= a(3) xor b(3) xor n6; + n10 <= a(4) or b(4) when n8='1' else a(4) and b(4); + o(4) <= a(4) xor b(4) xor n8; + n12 <= a(5) or b(5) when n10='1' else a(5) and b(5); + o(5) <= a(5) xor b(5) xor n10; + n14 <= a(6) or b(6) when n12='1' else a(6) and b(6); + o(6) <= a(6) xor b(6) xor n12; + n16 <= a(7) or b(7) when n14='1' else a(7) and b(7); + o(7) <= a(7) xor b(7) xor n14; + n18 <= a(8) or b(8) when n16='1' else a(8) and b(8); + o(8) <= a(8) xor b(8) xor n16; + n20 <= a(9) or b(9) when n18='1' else a(9) and b(9); + o(9) <= a(9) xor b(9) xor n18; + n22 <= a(10) or b(10) when n20='1' else a(10) and b(10); + o(10) <= a(10) xor b(10) xor n20; + n24 <= a(11) or b(11) when n22='1' else a(11) and b(11); + o(11) <= a(11) xor b(11) xor n22; + n26 <= a(12) or b(12) when n24='1' else a(12) and b(12); + o(12) <= a(12) xor b(12) xor n24; + n28 <= a(13) or b(13) when n26='1' else a(13) and b(13); + o(13) <= a(13) xor b(13) xor n26; + n30 <= a(14) or b(14) when n28='1' else a(14) and b(14); + o(14) <= a(14) xor b(14) xor n28; + n32 <= a(15) or b(15) when n30='1' else a(15) and b(15); + o(15) <= a(15) xor b(15) xor n30; + n34 <= a(16) or b(16) when n32='1' else a(16) and b(16); + o(16) <= a(16) xor b(16) xor n32; + n36 <= a(17) or b(17) when n34='1' else a(17) and b(17); + o(17) <= a(17) xor b(17) xor n34; + n38 <= a(18) or b(18) when n36='1' else a(18) and b(18); + o(18) <= a(18) xor b(18) xor n36; + n40 <= a(19) or b(19) when n38='1' else a(19) and b(19); + o(19) <= a(19) xor b(19) xor n38; + n42 <= a(20) or b(20) when n40='1' else a(20) and b(20); + o(20) <= a(20) xor b(20) xor n40; + n44 <= a(21) or b(21) when n42='1' else a(21) and b(21); + o(21) <= a(21) xor b(21) xor n42; + n46 <= a(22) or b(22) when n44='1' else a(22) and b(22); + o(22) <= a(22) xor b(22) xor n44; + n48 <= a(23) or b(23) when n46='1' else a(23) and b(23); + o(23) <= a(23) xor b(23) xor n46; + n50 <= a(24) or b(24) when n48='1' else a(24) and b(24); + o(24) <= a(24) xor b(24) xor n48; + n52 <= a(25) or b(25) when n50='1' else a(25) and b(25); + o(25) <= a(25) xor b(25) xor n50; + n54 <= a(26) or b(26) when n52='1' else a(26) and b(26); + o(26) <= a(26) xor b(26) xor n52; + n56 <= a(27) or b(27) when n54='1' else a(27) and b(27); + o(27) <= a(27) xor b(27) xor n54; + n58 <= a(28) or b(28) when n56='1' else a(28) and b(28); + o(28) <= a(28) xor b(28) xor n56; + n60 <= a(29) or b(29) when n58='1' else a(29) and b(29); + o(29) <= a(29) xor b(29) xor n58; + n62 <= a(30) or b(30) when n60='1' else a(30) and b(30); + o(30) <= a(30) xor b(30) xor n60; + cout <= a(31) or b(31) when n62='1' else a(31) and b(31); + o(31) <= a(31) xor b(31) xor n62; + +end architecture INTERFACE; + + +-- +-- Verific VHDL Description of OPERATOR mux_3 +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +entity mux_3 is + port (d0: in std_logic_vector(2 downto 0); + d1: in std_logic_vector(2 downto 0); + cond: in std_logic; + o: out std_logic_vector(2 downto 0) + ); + +end entity mux_3; + +architecture INTERFACE of mux_3 is + +begin + o(0) <= d1(0) when cond='1' else d0(0); + o(1) <= d1(1) when cond='1' else d0(1); + o(2) <= d1(2) when cond='1' else d0(2); + +end architecture INTERFACE; + + +-- +-- Verific VHDL Description of OPERATOR not_equal_32 +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +entity not_equal_32 is + port (a: in std_logic_vector(31 downto 0); + b: in std_logic_vector(31 downto 0); + o: out std_logic + ); + +end entity not_equal_32; + +architecture INTERFACE of not_equal_32 is + signal n1,n2,n3,n4,n5,n6,n7,n8,n9,n10,n11,n12,n13,n14,n15, + n16,n17,n18,n19,n20,n21,n22,n23,n24,n25,n26,n27,n28,n29, + n30,n31,n32,n33,n34,n35,n36,n37,n38,n39,n40,n41,n42,n43, + n44,n45,n46,n47,n48,n49,n50,n51,n52,n53,n54,n55,n56,n57, + n58,n59,n60,n61,n62,n63,n64 : std_logic; +begin + n1 <= a(0) xor b(0); + n2 <= a(1) xor b(1); + n3 <= a(2) xor b(2); + n4 <= a(3) xor b(3); + n5 <= a(4) xor b(4); + n6 <= a(5) xor b(5); + n7 <= a(6) xor b(6); + n8 <= a(7) xor b(7); + n9 <= a(8) xor b(8); + n10 <= a(9) xor b(9); + n11 <= a(10) xor b(10); + n12 <= a(11) xor b(11); + n13 <= a(12) xor b(12); + n14 <= a(13) xor b(13); + n15 <= a(14) xor b(14); + n16 <= a(15) xor b(15); + n17 <= a(16) xor b(16); + n18 <= a(17) xor b(17); + n19 <= a(18) xor b(18); + n20 <= a(19) xor b(19); + n21 <= a(20) xor b(20); + n22 <= a(21) xor b(21); + n23 <= a(22) xor b(22); + n24 <= a(23) xor b(23); + n25 <= a(24) xor b(24); + n26 <= a(25) xor b(25); + n27 <= a(26) xor b(26); + n28 <= a(27) xor b(27); + n29 <= a(28) xor b(28); + n30 <= a(29) xor b(29); + n31 <= a(30) xor b(30); + n32 <= a(31) xor b(31); + n33 <= n1 or n2; + n34 <= n3 or n4; + n35 <= n33 or n34; + n36 <= n5 or n6; + n37 <= n7 or n8; + n38 <= n36 or n37; + n39 <= n35 or n38; + n40 <= n9 or n10; + n41 <= n11 or n12; + n42 <= n40 or n41; + n43 <= n13 or n14; + n44 <= n15 or n16; + n45 <= n43 or n44; + n46 <= n42 or n45; + n47 <= n39 or n46; + n48 <= n17 or n18; + n49 <= n19 or n20; + n50 <= n48 or n49; + n51 <= n21 or n22; + n52 <= n23 or n24; + n53 <= n51 or n52; + n54 <= n50 or n53; + n55 <= n25 or n26; + n56 <= n27 or n28; + n57 <= n55 or n56; + n58 <= n29 or n30; + n59 <= n31 or n32; + n60 <= n58 or n59; + n61 <= n57 or n60; + n62 <= n54 or n61; + n63 <= n47 or n62; + n64 <= not n63; + o <= not n64; + +end architecture INTERFACE; + + +-- +-- Verific VHDL Description of OPERATOR not_equal_5 +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +entity not_equal_5 is + port (a: in std_logic_vector(4 downto 0); + b: in std_logic_vector(4 downto 0); + o: out std_logic + ); + +end entity not_equal_5; + +architecture INTERFACE of not_equal_5 is + signal n1,n2,n3,n4,n5,n6,n7,n8,n9,n10 : std_logic; +begin + n1 <= a(0) xor b(0); + n2 <= a(1) xor b(1); + n3 <= a(2) xor b(2); + n4 <= a(3) xor b(3); + n5 <= a(4) xor b(4); + n6 <= n1 or n2; + n7 <= n4 or n5; + n8 <= n3 or n7; + n9 <= n6 or n8; + n10 <= not n9; + o <= not n10; + +end architecture INTERFACE; + + +-- +-- Verific VHDL Description of OPERATOR wide_dffrs_3 +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +entity wide_dffrs_3 is + port (d: in std_logic_vector(2 downto 0); + set: in std_logic_vector(2 downto 0); + reset: in std_logic_vector(2 downto 0); + clock: in std_logic; + q: out std_logic_vector(2 downto 0) + ); + +end entity wide_dffrs_3; + +architecture INTERFACE of wide_dffrs_3 is + procedure VERIFIC_DFFRS (d: in std_logic; + signal clk: in std_logic; + s: in std_logic; + r: in std_logic; + signal q: inout std_logic + ) is begin + if (s='1') then + q <= '1' ; + elsif (r='1') then + q <= '0' ; + elsif (clk'event and clk='1') then + q <= d ; + end if ; + end procedure VERIFIC_DFFRS; + signal \q[0]_c\,\q[1]_c\,\q[2]_c\ : std_logic; +begin + q(2) <= \q[2]_c\; + q(1) <= \q[1]_c\; + q(0) <= \q[0]_c\; + i1: VERIFIC_DFFRS (d=>d(0),clk=>clock,s=>set(0),r=>reset(0),q=>\q[0]_c\); + i2: VERIFIC_DFFRS (d=>d(1),clk=>clock,s=>set(1),r=>reset(1),q=>\q[1]_c\); + i3: VERIFIC_DFFRS (d=>d(2),clk=>clock,s=>set(2),r=>reset(2),q=>\q[2]_c\); + +end architecture INTERFACE; + + +-- +-- Verific VHDL Description of OPERATOR wide_dffrs_5 +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +entity wide_dffrs_5 is + port (d: in std_logic_vector(4 downto 0); + set: in std_logic_vector(4 downto 0); + reset: in std_logic_vector(4 downto 0); + clock: in std_logic; + q: out std_logic_vector(4 downto 0) + ); + +end entity wide_dffrs_5; + +architecture INTERFACE of wide_dffrs_5 is + procedure VERIFIC_DFFRS (d: in std_logic; + signal clk: in std_logic; + s: in std_logic; + r: in std_logic; + signal q: inout std_logic + ) is begin + if (s='1') then + q <= '1' ; + elsif (r='1') then + q <= '0' ; + elsif (clk'event and clk='1') then + q <= d ; + end if ; + end procedure VERIFIC_DFFRS; + signal \q[0]_c\,\q[1]_c\,\q[2]_c\,\q[3]_c\,\q[4]_c\ : std_logic; +begin + q(4) <= \q[4]_c\; + q(3) <= \q[3]_c\; + q(2) <= \q[2]_c\; + q(1) <= \q[1]_c\; + q(0) <= \q[0]_c\; + i1: VERIFIC_DFFRS (d=>d(0),clk=>clock,s=>set(0),r=>reset(0),q=>\q[0]_c\); + i2: VERIFIC_DFFRS (d=>d(1),clk=>clock,s=>set(1),r=>reset(1),q=>\q[1]_c\); + i3: VERIFIC_DFFRS (d=>d(2),clk=>clock,s=>set(2),r=>reset(2),q=>\q[2]_c\); + i4: VERIFIC_DFFRS (d=>d(3),clk=>clock,s=>set(3),r=>reset(3),q=>\q[3]_c\); + i5: VERIFIC_DFFRS (d=>d(4),clk=>clock,s=>set(4),r=>reset(4),q=>\q[4]_c\); + +end architecture INTERFACE; + + +-- +-- Verific VHDL Description of module input_4chrxdll_sync +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +library ecp5um ; +use ecp5um.components.all ; + +entity input_4chrxdll_sync is + port (rst: in std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(47) + sync_clk: in std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(48) + update: in std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(49) + dll_lock: in std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(50) + dll_reset: out std_logic; -- syn_preserve=1 -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(58) + uddcntln: out std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(53) + freeze: out std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(54) + stop: out std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(55) + ddr_reset: out std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(56) + ready: out std_logic -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(57) + ); + +end entity input_4chrxdll_sync; -- syn_module_defined=1 -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(25) + +architecture input_4chrxdll_sync of input_4chrxdll_sync is + procedure VERIFIC_DFFRS (d: in std_logic; + signal clk: in std_logic; + s: in std_logic; + r: in std_logic; + signal q: inout std_logic + ) is begin + if (s='1') then + q <= '1' ; + elsif (r='1') then + q <= '0' ; + elsif (clk'event and clk='1') then + q <= d ; + end if ; + end procedure VERIFIC_DFFRS; + signal uddcntln_c : std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(53) + signal freeze_c : std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(54) + signal stop_c : std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(55) + signal ready_c : std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(57) + signal dll_reset_c : std_logic; -- syn_preserve=1 -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(58) + signal ddr_reset_d : std_logic; -- syn_preserve=1 -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(75) + signal ctrl_cnt : std_logic_vector(2 downto 0); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(77) + signal dll_lock_cnt : std_logic_vector(2 downto 0); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(78) + signal ready_cnt : std_logic_vector(2 downto 0); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(79) + signal cs_rx_sync : std_logic_vector(4 downto 0); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(81) + signal ns_rx_sync : std_logic_vector(4 downto 0); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(82) + signal dll_lock_q1 : std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(84) + signal dll_lock_q2 : std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(85) + signal not_uddcntln : std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(87) + signal assert_stop : std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(88) + signal not_reset : std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(89) + signal not_stop : std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(90) + signal not_freeze : std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(91) + signal get_ready : std_logic; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(92) + signal n303,pwr,n3,n4,n5,n6,n8 : std_logic; + signal n9 : std_logic_vector(4 downto 0); + signal n15 : std_logic_vector(4 downto 0); + signal n21 : std_logic; + signal n24 : std_logic_vector(4 downto 0); + signal n30 : std_logic_vector(4 downto 0); + signal n36 : std_logic_vector(4 downto 0); + signal n42,n44 : std_logic; + signal n45 : std_logic_vector(4 downto 0); + signal n51 : std_logic; + signal n53 : std_logic_vector(4 downto 0); + signal n59 : std_logic_vector(4 downto 0); + signal n65,n67 : std_logic; + signal n68 : std_logic_vector(4 downto 0); + signal n74,n75 : std_logic; + signal n76 : std_logic_vector(4 downto 0); + signal n82,n83,n84,n85,n86,n87,n88,n97,n98,n99 : std_logic; + signal n101 : std_logic_vector(31 downto 0); + signal n134 : std_logic_vector(2 downto 0); + signal n138,n139,n140,n141,n142 : std_logic; + signal n144 : std_logic_vector(31 downto 0); + signal n177 : std_logic_vector(2 downto 0); + signal n181 : std_logic_vector(2 downto 0); + signal n185 : std_logic_vector(2 downto 0); + signal n189,n190 : std_logic; + signal n192 : std_logic_vector(31 downto 0); + signal n225 : std_logic_vector(2 downto 0); + signal n229,n230,n231,n232,n233,n234,n235,n236,n237,n238,n239, + n240,n241,n242,n243,n244,n245,n246,n247,n248,n249,n250,n251, + n252,n253,n254,n255,n256,n257,n258,n259,n260,n261,n262 : std_logic; + signal n263 : std_logic_vector(2 downto 0); + signal n267 : std_logic_vector(2 downto 0); + signal n271 : std_logic_vector(2 downto 0); + signal gnd : std_logic; signal OPEN_net : std_logic_vector(0 to 87); + +begin + dll_reset <= dll_reset_c; -- syn_preserve=1 -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(58) + uddcntln <= uddcntln_c; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(53) + freeze <= freeze_c; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(54) + stop <= stop_c; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(55) + ready <= ready_c; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(57) + n303 <= '0' ; + pwr <= '1' ; + ddr_reset <= cs_rx_sync(2) or ddr_reset_d; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(114) + equal_4: entity work.equal_32(INTERFACE) port map (a(31)=>n303,a(30)=>n303, + a(29)=>n303,a(28)=>n303,a(27)=>n303,a(26)=>n303,a(25)=>n303, + a(24)=>n303,a(23)=>n303,a(22)=>n303,a(21)=>n303,a(20)=>n303, + a(19)=>n303,a(18)=>n303,a(17)=>n303,a(16)=>n303,a(15)=>n303, + a(14)=>n303,a(13)=>n303,a(12)=>n303,a(11)=>n303,a(10)=>n303, + a(9)=>n303,a(8)=>n303,a(7)=>n303,a(6)=>n303,a(5)=>n303,a(4)=>n303, + a(3)=>n303,a(2)=>dll_lock_cnt(2),a(1)=>dll_lock_cnt(1),a(0)=>dll_lock_cnt(0), + b(31)=>n303,b(30)=>n303,b(29)=>n303,b(28)=>n303,b(27)=>n303, + b(26)=>n303,b(25)=>n303,b(24)=>n303,b(23)=>n303,b(22)=>n303, + b(21)=>n303,b(20)=>n303,b(19)=>n303,b(18)=>n303,b(17)=>n303, + b(16)=>n303,b(15)=>n303,b(14)=>n303,b(13)=>n303,b(12)=>n303, + b(11)=>n303,b(10)=>n303,b(9)=>n303,b(8)=>n303,b(7)=>n303,b(6)=>n303, + b(5)=>n303,b(4)=>n303,b(3)=>n303,b(2)=>pwr,b(1)=>n303,b(0)=>pwr, + o=>n3); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(124) + n4 <= not not_uddcntln; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(124) + n5 <= n3 and n4; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(124) + equal_7: entity work.equal_32(INTERFACE) port map (a(31)=>n303,a(30)=>n303, + a(29)=>n303,a(28)=>n303,a(27)=>n303,a(26)=>n303,a(25)=>n303, + a(24)=>n303,a(23)=>n303,a(22)=>n303,a(21)=>n303,a(20)=>n303, + a(19)=>n303,a(18)=>n303,a(17)=>n303,a(16)=>n303,a(15)=>n303, + a(14)=>n303,a(13)=>n303,a(12)=>n303,a(11)=>n303,a(10)=>n303, + a(9)=>n303,a(8)=>n303,a(7)=>n303,a(6)=>n303,a(5)=>n303,a(4)=>n303, + a(3)=>n303,a(2)=>ready_cnt(2),a(1)=>ready_cnt(1),a(0)=>ready_cnt(0), + b(31)=>n303,b(30)=>n303,b(29)=>n303,b(28)=>n303,b(27)=>n303, + b(26)=>n303,b(25)=>n303,b(24)=>n303,b(23)=>n303,b(22)=>n303, + b(21)=>n303,b(20)=>n303,b(19)=>n303,b(18)=>n303,b(17)=>n303, + b(16)=>n303,b(15)=>n303,b(14)=>n303,b(13)=>n303,b(12)=>n303, + b(11)=>n303,b(10)=>n303,b(9)=>n303,b(8)=>n303,b(7)=>n303,b(6)=>n303, + b(5)=>n303,b(4)=>n303,b(3)=>n303,b(2)=>pwr,b(1)=>pwr,b(0)=>pwr, + o=>n6); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(128) + n8 <= n6 and get_ready; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(128) + mux_10: entity work.mux_5(INTERFACE) port map (d0(4)=>n303,d0(3)=>n303, + d0(2)=>n303,d0(1)=>pwr,d0(0)=>n303,d1(4)=>n303,d1(3)=>n303, + d1(2)=>n303,d1(1)=>pwr,d1(0)=>pwr,cond=>n8,o(4)=>n9(4),o(3)=>n9(3), + o(2)=>n9(2),o(1)=>n9(1),o(0)=>n9(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(135) + mux_11: entity work.mux_5(INTERFACE) port map (d0(4)=>n9(4),d0(3)=>n9(3), + d0(2)=>n9(2),d0(1)=>n9(1),d0(0)=>n9(0),d1(4)=>pwr,d1(3)=>n303, + d1(2)=>n303,d1(1)=>pwr,d1(0)=>n303,cond=>n5,o(4)=>n15(4),o(3)=>n15(3), + o(2)=>n15(2),o(1)=>n15(1),o(0)=>n15(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(135) + equal_12: entity work.equal_32(INTERFACE) port map (a(31)=>n303,a(30)=>n303, + a(29)=>n303,a(28)=>n303,a(27)=>n303,a(26)=>n303,a(25)=>n303, + a(24)=>n303,a(23)=>n303,a(22)=>n303,a(21)=>n303,a(20)=>n303, + a(19)=>n303,a(18)=>n303,a(17)=>n303,a(16)=>n303,a(15)=>n303, + a(14)=>n303,a(13)=>n303,a(12)=>n303,a(11)=>n303,a(10)=>n303, + a(9)=>n303,a(8)=>n303,a(7)=>n303,a(6)=>n303,a(5)=>n303,a(4)=>n303, + a(3)=>n303,a(2)=>ctrl_cnt(2),a(1)=>ctrl_cnt(1),a(0)=>ctrl_cnt(0), + b(31)=>n303,b(30)=>n303,b(29)=>n303,b(28)=>n303,b(27)=>n303, + b(26)=>n303,b(25)=>n303,b(24)=>n303,b(23)=>n303,b(22)=>n303, + b(21)=>n303,b(20)=>n303,b(19)=>n303,b(18)=>n303,b(17)=>n303, + b(16)=>n303,b(15)=>n303,b(14)=>n303,b(13)=>n303,b(12)=>n303, + b(11)=>n303,b(10)=>n303,b(9)=>n303,b(8)=>n303,b(7)=>n303,b(6)=>n303, + b(5)=>n303,b(4)=>n303,b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>pwr, + o=>n21); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(140) + mux_15: entity work.mux_5(INTERFACE) port map (d0(4)=>pwr,d0(3)=>n303, + d0(2)=>n303,d0(1)=>n303,d0(0)=>n303,d1(4)=>n303,d1(3)=>n303, + d1(2)=>n303,d1(1)=>pwr,d1(0)=>n303,cond=>not_freeze,o(4)=>n24(4), + o(3)=>n24(3),o(2)=>n24(2),o(1)=>n24(1),o(0)=>n24(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(153) + mux_16: entity work.mux_5(INTERFACE) port map (d0(4)=>n24(4),d0(3)=>n24(3), + d0(2)=>n24(2),d0(1)=>n24(1),d0(0)=>n24(0),d1(4)=>pwr,d1(3)=>pwr, + d1(2)=>n303,d1(1)=>pwr,d1(0)=>n303,cond=>assert_stop,o(4)=>n30(4), + o(3)=>n30(3),o(2)=>n30(2),o(1)=>n30(1),o(0)=>n30(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(153) + mux_17: entity work.mux_5(INTERFACE) port map (d0(4)=>pwr,d0(3)=>n303, + d0(2)=>n303,d0(1)=>pwr,d0(0)=>n303,d1(4)=>n30(4),d1(3)=>n30(3), + d1(2)=>n30(2),d1(1)=>n30(1),d1(0)=>n30(0),cond=>n21,o(4)=>n36(4), + o(3)=>n36(3),o(2)=>n36(2),o(1)=>n36(1),o(0)=>n36(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(158) + equal_18: entity work.equal_32(INTERFACE) port map (a(31)=>n303,a(30)=>n303, + a(29)=>n303,a(28)=>n303,a(27)=>n303,a(26)=>n303,a(25)=>n303, + a(24)=>n303,a(23)=>n303,a(22)=>n303,a(21)=>n303,a(20)=>n303, + a(19)=>n303,a(18)=>n303,a(17)=>n303,a(16)=>n303,a(15)=>n303, + a(14)=>n303,a(13)=>n303,a(12)=>n303,a(11)=>n303,a(10)=>n303, + a(9)=>n303,a(8)=>n303,a(7)=>n303,a(6)=>n303,a(5)=>n303,a(4)=>n303, + a(3)=>n303,a(2)=>ctrl_cnt(2),a(1)=>ctrl_cnt(1),a(0)=>ctrl_cnt(0), + b(31)=>n303,b(30)=>n303,b(29)=>n303,b(28)=>n303,b(27)=>n303, + b(26)=>n303,b(25)=>n303,b(24)=>n303,b(23)=>n303,b(22)=>n303, + b(21)=>n303,b(20)=>n303,b(19)=>n303,b(18)=>n303,b(17)=>n303, + b(16)=>n303,b(15)=>n303,b(14)=>n303,b(13)=>n303,b(12)=>n303, + b(11)=>n303,b(10)=>n303,b(9)=>n303,b(8)=>n303,b(7)=>n303,b(6)=>n303, + b(5)=>n303,b(4)=>n303,b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>pwr, + o=>n42); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(163) + n44 <= n42 and not_uddcntln; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(163) + mux_21: entity work.mux_5(INTERFACE) port map (d0(4)=>pwr,d0(3)=>n303, + d0(2)=>n303,d0(1)=>n303,d0(0)=>n303,d1(4)=>pwr,d1(3)=>n303, + d1(2)=>n303,d1(1)=>pwr,d1(0)=>n303,cond=>n44,o(4)=>n45(4),o(3)=>n45(3), + o(2)=>n45(2),o(1)=>n45(1),o(0)=>n45(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(170) + equal_22: entity work.equal_32(INTERFACE) port map (a(31)=>n303,a(30)=>n303, + a(29)=>n303,a(28)=>n303,a(27)=>n303,a(26)=>n303,a(25)=>n303, + a(24)=>n303,a(23)=>n303,a(22)=>n303,a(21)=>n303,a(20)=>n303, + a(19)=>n303,a(18)=>n303,a(17)=>n303,a(16)=>n303,a(15)=>n303, + a(14)=>n303,a(13)=>n303,a(12)=>n303,a(11)=>n303,a(10)=>n303, + a(9)=>n303,a(8)=>n303,a(7)=>n303,a(6)=>n303,a(5)=>n303,a(4)=>n303, + a(3)=>n303,a(2)=>ctrl_cnt(2),a(1)=>ctrl_cnt(1),a(0)=>ctrl_cnt(0), + b(31)=>n303,b(30)=>n303,b(29)=>n303,b(28)=>n303,b(27)=>n303, + b(26)=>n303,b(25)=>n303,b(24)=>n303,b(23)=>n303,b(22)=>n303, + b(21)=>n303,b(20)=>n303,b(19)=>n303,b(18)=>n303,b(17)=>n303, + b(16)=>n303,b(15)=>n303,b(14)=>n303,b(13)=>n303,b(12)=>n303, + b(11)=>n303,b(10)=>n303,b(9)=>n303,b(8)=>n303,b(7)=>n303,b(6)=>n303, + b(5)=>n303,b(4)=>n303,b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>pwr, + o=>n51); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(175) + mux_24: entity work.mux_5(INTERFACE) port map (d0(4)=>pwr,d0(3)=>pwr, + d0(2)=>pwr,d0(1)=>pwr,d0(0)=>n303,d1(4)=>pwr,d1(3)=>n303,d1(2)=>n303, + d1(1)=>pwr,d1(0)=>n303,cond=>not_stop,o(4)=>n53(4),o(3)=>n53(3), + o(2)=>n53(2),o(1)=>n53(1),o(0)=>n53(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(184) + mux_25: entity work.mux_5(INTERFACE) port map (d0(4)=>pwr,d0(3)=>pwr, + d0(2)=>n303,d0(1)=>pwr,d0(0)=>n303,d1(4)=>n53(4),d1(3)=>n53(3), + d1(2)=>n53(2),d1(1)=>n53(1),d1(0)=>n53(0),cond=>n51,o(4)=>n59(4), + o(3)=>n59(3),o(2)=>n59(2),o(1)=>n59(1),o(0)=>n59(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(189) + equal_26: entity work.equal_32(INTERFACE) port map (a(31)=>n303,a(30)=>n303, + a(29)=>n303,a(28)=>n303,a(27)=>n303,a(26)=>n303,a(25)=>n303, + a(24)=>n303,a(23)=>n303,a(22)=>n303,a(21)=>n303,a(20)=>n303, + a(19)=>n303,a(18)=>n303,a(17)=>n303,a(16)=>n303,a(15)=>n303, + a(14)=>n303,a(13)=>n303,a(12)=>n303,a(11)=>n303,a(10)=>n303, + a(9)=>n303,a(8)=>n303,a(7)=>n303,a(6)=>n303,a(5)=>n303,a(4)=>n303, + a(3)=>n303,a(2)=>ctrl_cnt(2),a(1)=>ctrl_cnt(1),a(0)=>ctrl_cnt(0), + b(31)=>n303,b(30)=>n303,b(29)=>n303,b(28)=>n303,b(27)=>n303, + b(26)=>n303,b(25)=>n303,b(24)=>n303,b(23)=>n303,b(22)=>n303, + b(21)=>n303,b(20)=>n303,b(19)=>n303,b(18)=>n303,b(17)=>n303, + b(16)=>n303,b(15)=>n303,b(14)=>n303,b(13)=>n303,b(12)=>n303, + b(11)=>n303,b(10)=>n303,b(9)=>n303,b(8)=>n303,b(7)=>n303,b(6)=>n303, + b(5)=>n303,b(4)=>n303,b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>pwr, + o=>n65); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(194) + n67 <= n65 and not_reset; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(194) + mux_29: entity work.mux_5(INTERFACE) port map (d0(4)=>pwr,d0(3)=>pwr, + d0(2)=>pwr,d0(1)=>pwr,d0(0)=>n303,d1(4)=>pwr,d1(3)=>pwr,d1(2)=>n303, + d1(1)=>pwr,d1(0)=>n303,cond=>n67,o(4)=>n68(4),o(3)=>n68(3), + o(2)=>n68(2),o(1)=>n68(1),o(0)=>n68(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(201) + n74 <= not dll_lock_q2; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(206) + n75 <= n74 or update; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(206) + mux_32: entity work.mux_5(INTERFACE) port map (d0(4)=>n303,d0(3)=>n303, + d0(2)=>n303,d0(1)=>pwr,d0(0)=>pwr,d1(4)=>n303,d1(3)=>n303,d1(2)=>n303, + d1(1)=>pwr,d1(0)=>n303,cond=>n75,o(4)=>n76(4),o(3)=>n76(3), + o(2)=>n76(2),o(1)=>n76(1),o(0)=>n76(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(213) + equal_33: entity work.equal_5(INTERFACE) port map (a(4)=>freeze_c,a(3)=>stop_c, + a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c,b(4)=>n303, + b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>n303,o=>n82); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(122) + equal_34: entity work.equal_5(INTERFACE) port map (a(4)=>freeze_c,a(3)=>stop_c, + a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c,b(4)=>pwr, + b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>n303,o=>n83); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(138) + equal_35: entity work.equal_5(INTERFACE) port map (a(4)=>freeze_c,a(3)=>stop_c, + a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c,b(4)=>pwr, + b(3)=>n303,b(2)=>n303,b(1)=>n303,b(0)=>n303,o=>n84); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(161) + equal_36: entity work.equal_5(INTERFACE) port map (a(4)=>freeze_c,a(3)=>stop_c, + a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c,b(4)=>pwr, + b(3)=>pwr,b(2)=>n303,b(1)=>pwr,b(0)=>n303,o=>n85); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(173) + equal_37: entity work.equal_5(INTERFACE) port map (a(4)=>freeze_c,a(3)=>stop_c, + a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c,b(4)=>pwr, + b(3)=>pwr,b(2)=>pwr,b(1)=>pwr,b(0)=>n303,o=>n86); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(192) + equal_38: entity work.equal_5(INTERFACE) port map (a(4)=>freeze_c,a(3)=>stop_c, + a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c,b(4)=>n303, + b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>pwr,o=>n87); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(204) + reduce_nor_39: entity work.reduce_nor_6(INTERFACE) port map (a(5)=>n82, + a(4)=>n83,a(3)=>n84,a(2)=>n85,a(1)=>n86,a(0)=>n87,o=>n88); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(221) + select_40: entity work.wide_select_7_35(INTERFACE) port map (sel(6)=>n82, + sel(5)=>n83,sel(4)=>n84,sel(3)=>n85,sel(2)=>n86,sel(1)=>n87, + sel(0)=>n88,data(34)=>n15(4),data(33)=>n15(3),data(32)=>n15(2), + data(31)=>n15(1),data(30)=>n15(0),data(29)=>n36(4),data(28)=>n36(3), + data(27)=>n36(2),data(26)=>n36(1),data(25)=>n36(0),data(24)=>n45(4), + data(23)=>n45(3),data(22)=>n45(2),data(21)=>n45(1),data(20)=>n45(0), + data(19)=>n59(4),data(18)=>n59(3),data(17)=>n59(2),data(16)=>n59(1), + data(15)=>n59(0),data(14)=>n68(4),data(13)=>n68(3),data(12)=>n68(2), + data(11)=>n68(1),data(10)=>n68(0),data(9)=>n76(4),data(8)=>n76(3), + data(7)=>n76(2),data(6)=>n76(1),data(5)=>n76(0),data(4)=>freeze_c, + data(3)=>stop_c,data(2)=>cs_rx_sync(2),data(1)=>uddcntln_c,data(0)=>ready_c, + o(4)=>ns_rx_sync(4),o(3)=>ns_rx_sync(3),o(2)=>ns_rx_sync(2),o(1)=>ns_rx_sync(1), + o(0)=>ns_rx_sync(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(221) + dll_lock_q2_112: VERIFIC_DFFRS (d=>dll_lock_q1,clk=>sync_clk,s=>n303, + r=>rst,q=>dll_lock_q2); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(238) + gnd <= '0' ; + n97 <= dll_lock_q2 and dll_lock; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(264) + LessThan_44: entity work.LessThan_3u_3u(INTERFACE) port map (cin=>n303, + a(2)=>dll_lock_cnt(2),a(1)=>dll_lock_cnt(1),a(0)=>dll_lock_cnt(0), + b(2)=>pwr,b(1)=>n303,b(0)=>pwr,o=>n98); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(264) + n99 <= n97 and n98; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(264) + add_46: entity work.add_32u_32u(INTERFACE) port map (cin=>n303,a(31)=>n303, + a(30)=>n303,a(29)=>n303,a(28)=>n303,a(27)=>n303,a(26)=>n303, + a(25)=>n303,a(24)=>n303,a(23)=>n303,a(22)=>n303,a(21)=>n303, + a(20)=>n303,a(19)=>n303,a(18)=>n303,a(17)=>n303,a(16)=>n303, + a(15)=>n303,a(14)=>n303,a(13)=>n303,a(12)=>n303,a(11)=>n303, + a(10)=>n303,a(9)=>n303,a(8)=>n303,a(7)=>n303,a(6)=>n303,a(5)=>n303, + a(4)=>n303,a(3)=>n303,a(2)=>dll_lock_cnt(2),a(1)=>dll_lock_cnt(1), + a(0)=>dll_lock_cnt(0),b(31)=>n303,b(30)=>n303,b(29)=>n303,b(28)=>n303, + b(27)=>n303,b(26)=>n303,b(25)=>n303,b(24)=>n303,b(23)=>n303, + b(22)=>n303,b(21)=>n303,b(20)=>n303,b(19)=>n303,b(18)=>n303, + b(17)=>n303,b(16)=>n303,b(15)=>n303,b(14)=>n303,b(13)=>n303, + b(12)=>n303,b(11)=>n303,b(10)=>n303,b(9)=>n303,b(8)=>n303,b(7)=>n303, + b(6)=>n303,b(5)=>n303,b(4)=>n303,b(3)=>n303,b(2)=>n303,b(1)=>n303, + b(0)=>pwr,o(31)=>OPEN_net(87),o(30)=>OPEN_net(86),o(29)=>OPEN_net(85), + o(28)=>OPEN_net(84),o(27)=>OPEN_net(83),o(26)=>OPEN_net(82),o(25)=>OPEN_net(81), + o(24)=>OPEN_net(80),o(23)=>OPEN_net(79),o(22)=>OPEN_net(78),o(21)=>OPEN_net(77), + o(20)=>OPEN_net(76),o(19)=>OPEN_net(75),o(18)=>OPEN_net(74),o(17)=>OPEN_net(73), + o(16)=>OPEN_net(72),o(15)=>OPEN_net(71),o(14)=>OPEN_net(70),o(13)=>OPEN_net(69), + o(12)=>OPEN_net(68),o(11)=>OPEN_net(67),o(10)=>OPEN_net(66),o(9)=>OPEN_net(65), + o(8)=>OPEN_net(64),o(7)=>OPEN_net(63),o(6)=>OPEN_net(62),o(5)=>OPEN_net(61), + o(4)=>OPEN_net(60),o(3)=>OPEN_net(59),o(2)=>n101(2),o(1)=>n101(1), + o(0)=>n101(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(266) + mux_47: entity work.mux_3(INTERFACE) port map (d0(2)=>dll_lock_cnt(2), + d0(1)=>dll_lock_cnt(1),d0(0)=>dll_lock_cnt(0),d1(2)=>n101(2), + d1(1)=>n101(1),d1(0)=>n101(0),cond=>n99,o(2)=>n134(2),o(1)=>n134(1), + o(0)=>n134(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(267) + not_equal_48: entity work.not_equal_32(INTERFACE) port map (a(31)=>n303, + a(30)=>n303,a(29)=>n303,a(28)=>n303,a(27)=>n303,a(26)=>n303, + a(25)=>n303,a(24)=>n303,a(23)=>n303,a(22)=>n303,a(21)=>n303, + a(20)=>n303,a(19)=>n303,a(18)=>n303,a(17)=>n303,a(16)=>n303, + a(15)=>n303,a(14)=>n303,a(13)=>n303,a(12)=>n303,a(11)=>n303, + a(10)=>n303,a(9)=>n303,a(8)=>n303,a(7)=>n303,a(6)=>n303,a(5)=>n303, + a(4)=>n303,a(3)=>n303,a(2)=>dll_lock_cnt(2),a(1)=>dll_lock_cnt(1), + a(0)=>dll_lock_cnt(0),b(31)=>n303,b(30)=>n303,b(29)=>n303,b(28)=>n303, + b(27)=>n303,b(26)=>n303,b(25)=>n303,b(24)=>n303,b(23)=>n303, + b(22)=>n303,b(21)=>n303,b(20)=>n303,b(19)=>n303,b(18)=>n303, + b(17)=>n303,b(16)=>n303,b(15)=>n303,b(14)=>n303,b(13)=>n303, + b(12)=>n303,b(11)=>n303,b(10)=>n303,b(9)=>n303,b(8)=>n303,b(7)=>n303, + b(6)=>n303,b(5)=>n303,b(4)=>n303,b(3)=>n303,b(2)=>pwr,b(1)=>n303, + b(0)=>pwr,o=>n138); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(271) + equal_49: entity work.equal_32(INTERFACE) port map (a(31)=>n303,a(30)=>n303, + a(29)=>n303,a(28)=>n303,a(27)=>n303,a(26)=>n303,a(25)=>n303, + a(24)=>n303,a(23)=>n303,a(22)=>n303,a(21)=>n303,a(20)=>n303, + a(19)=>n303,a(18)=>n303,a(17)=>n303,a(16)=>n303,a(15)=>n303, + a(14)=>n303,a(13)=>n303,a(12)=>n303,a(11)=>n303,a(10)=>n303, + a(9)=>n303,a(8)=>n303,a(7)=>n303,a(6)=>n303,a(5)=>n303,a(4)=>n303, + a(3)=>n303,a(2)=>ctrl_cnt(2),a(1)=>ctrl_cnt(1),a(0)=>ctrl_cnt(0), + b(31)=>n303,b(30)=>n303,b(29)=>n303,b(28)=>n303,b(27)=>n303, + b(26)=>n303,b(25)=>n303,b(24)=>n303,b(23)=>n303,b(22)=>n303, + b(21)=>n303,b(20)=>n303,b(19)=>n303,b(18)=>n303,b(17)=>n303, + b(16)=>n303,b(15)=>n303,b(14)=>n303,b(13)=>n303,b(12)=>n303, + b(11)=>n303,b(10)=>n303,b(9)=>n303,b(8)=>n303,b(7)=>n303,b(6)=>n303, + b(5)=>n303,b(4)=>n303,b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>pwr, + o=>n139); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(275) + not_equal_50: entity work.not_equal_5(INTERFACE) port map (a(4)=>freeze_c, + a(3)=>stop_c,a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c, + b(4)=>n303,b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>pwr,o=>n140); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(275) + n141 <= n139 and n140; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(275) + LessThan_52: entity work.LessThan_3u_3u(INTERFACE) port map (cin=>n303, + a(2)=>ctrl_cnt(2),a(1)=>ctrl_cnt(1),a(0)=>ctrl_cnt(0),b(2)=>pwr, + b(1)=>n303,b(0)=>n303,o=>n142); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(280) + add_53: entity work.add_32u_32u(INTERFACE) port map (cin=>n303,a(31)=>n303, + a(30)=>n303,a(29)=>n303,a(28)=>n303,a(27)=>n303,a(26)=>n303, + a(25)=>n303,a(24)=>n303,a(23)=>n303,a(22)=>n303,a(21)=>n303, + a(20)=>n303,a(19)=>n303,a(18)=>n303,a(17)=>n303,a(16)=>n303, + a(15)=>n303,a(14)=>n303,a(13)=>n303,a(12)=>n303,a(11)=>n303, + a(10)=>n303,a(9)=>n303,a(8)=>n303,a(7)=>n303,a(6)=>n303,a(5)=>n303, + a(4)=>n303,a(3)=>n303,a(2)=>ctrl_cnt(2),a(1)=>ctrl_cnt(1),a(0)=>ctrl_cnt(0), + b(31)=>n303,b(30)=>n303,b(29)=>n303,b(28)=>n303,b(27)=>n303, + b(26)=>n303,b(25)=>n303,b(24)=>n303,b(23)=>n303,b(22)=>n303, + b(21)=>n303,b(20)=>n303,b(19)=>n303,b(18)=>n303,b(17)=>n303, + b(16)=>n303,b(15)=>n303,b(14)=>n303,b(13)=>n303,b(12)=>n303, + b(11)=>n303,b(10)=>n303,b(9)=>n303,b(8)=>n303,b(7)=>n303,b(6)=>n303, + b(5)=>n303,b(4)=>n303,b(3)=>n303,b(2)=>n303,b(1)=>n303,b(0)=>pwr, + o(31)=>OPEN_net(58),o(30)=>OPEN_net(57),o(29)=>OPEN_net(56),o(28)=>OPEN_net(55), + o(27)=>OPEN_net(54),o(26)=>OPEN_net(53),o(25)=>OPEN_net(52),o(24)=>OPEN_net(51), + o(23)=>OPEN_net(50),o(22)=>OPEN_net(49),o(21)=>OPEN_net(48),o(20)=>OPEN_net(47), + o(19)=>OPEN_net(46),o(18)=>OPEN_net(45),o(17)=>OPEN_net(44),o(16)=>OPEN_net(43), + o(15)=>OPEN_net(42),o(14)=>OPEN_net(41),o(13)=>OPEN_net(40),o(12)=>OPEN_net(39), + o(11)=>OPEN_net(38),o(10)=>OPEN_net(37),o(9)=>OPEN_net(36),o(8)=>OPEN_net(35), + o(7)=>OPEN_net(34),o(6)=>OPEN_net(33),o(5)=>OPEN_net(32),o(4)=>OPEN_net(31), + o(3)=>OPEN_net(30),o(2)=>n144(2),o(1)=>n144(1),o(0)=>n144(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(282) + mux_54: entity work.mux_3(INTERFACE) port map (d0(2)=>ctrl_cnt(2),d0(1)=>ctrl_cnt(1), + d0(0)=>ctrl_cnt(0),d1(2)=>n144(2),d1(1)=>n144(1),d1(0)=>n144(0), + cond=>n142,o(2)=>n177(2),o(1)=>n177(1),o(0)=>n177(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(283) + mux_55: entity work.mux_3(INTERFACE) port map (d0(2)=>n177(2),d0(1)=>n177(1), + d0(0)=>n177(0),d1(2)=>n303,d1(1)=>n303,d1(0)=>n303,cond=>n141, + o(2)=>n181(2),o(1)=>n181(1),o(0)=>n181(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(283) + mux_56: entity work.mux_3(INTERFACE) port map (d0(2)=>n181(2),d0(1)=>n181(1), + d0(0)=>n181(0),d1(2)=>n303,d1(1)=>pwr,d1(0)=>pwr,cond=>n138, + o(2)=>n185(2),o(1)=>n185(1),o(0)=>n185(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(283) + LessThan_57: entity work.LessThan_3u_3u(INTERFACE) port map (cin=>n303, + a(2)=>ready_cnt(2),a(1)=>ready_cnt(1),a(0)=>ready_cnt(0),b(2)=>pwr, + b(1)=>pwr,b(0)=>pwr,o=>n189); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(287) + n190 <= get_ready and n189; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(287) + add_59: entity work.add_32u_32u(INTERFACE) port map (cin=>n303,a(31)=>n303, + a(30)=>n303,a(29)=>n303,a(28)=>n303,a(27)=>n303,a(26)=>n303, + a(25)=>n303,a(24)=>n303,a(23)=>n303,a(22)=>n303,a(21)=>n303, + a(20)=>n303,a(19)=>n303,a(18)=>n303,a(17)=>n303,a(16)=>n303, + a(15)=>n303,a(14)=>n303,a(13)=>n303,a(12)=>n303,a(11)=>n303, + a(10)=>n303,a(9)=>n303,a(8)=>n303,a(7)=>n303,a(6)=>n303,a(5)=>n303, + a(4)=>n303,a(3)=>n303,a(2)=>ready_cnt(2),a(1)=>ready_cnt(1), + a(0)=>ready_cnt(0),b(31)=>n303,b(30)=>n303,b(29)=>n303,b(28)=>n303, + b(27)=>n303,b(26)=>n303,b(25)=>n303,b(24)=>n303,b(23)=>n303, + b(22)=>n303,b(21)=>n303,b(20)=>n303,b(19)=>n303,b(18)=>n303, + b(17)=>n303,b(16)=>n303,b(15)=>n303,b(14)=>n303,b(13)=>n303, + b(12)=>n303,b(11)=>n303,b(10)=>n303,b(9)=>n303,b(8)=>n303,b(7)=>n303, + b(6)=>n303,b(5)=>n303,b(4)=>n303,b(3)=>n303,b(2)=>n303,b(1)=>n303, + b(0)=>pwr,o(31)=>OPEN_net(29),o(30)=>OPEN_net(28),o(29)=>OPEN_net(27), + o(28)=>OPEN_net(26),o(27)=>OPEN_net(25),o(26)=>OPEN_net(24),o(25)=>OPEN_net(23), + o(24)=>OPEN_net(22),o(23)=>OPEN_net(21),o(22)=>OPEN_net(20),o(21)=>OPEN_net(19), + o(20)=>OPEN_net(18),o(19)=>OPEN_net(17),o(18)=>OPEN_net(16),o(17)=>OPEN_net(15), + o(16)=>OPEN_net(14),o(15)=>OPEN_net(13),o(14)=>OPEN_net(12),o(13)=>OPEN_net(11), + o(12)=>OPEN_net(10),o(11)=>OPEN_net(9),o(10)=>OPEN_net(8),o(9)=>OPEN_net(7), + o(8)=>OPEN_net(6),o(7)=>OPEN_net(5),o(6)=>OPEN_net(4),o(5)=>OPEN_net(3), + o(4)=>OPEN_net(2),o(3)=>OPEN_net(1),o(2)=>n192(2),o(1)=>n192(1), + o(0)=>n192(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(290) + mux_60: entity work.mux_3(INTERFACE) port map (d0(2)=>ready_cnt(2),d0(1)=>ready_cnt(1), + d0(0)=>ready_cnt(0),d1(2)=>n192(2),d1(1)=>n192(1),d1(0)=>n192(0), + cond=>n190,o(2)=>n225(2),o(1)=>n225(1),o(0)=>n225(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(291) + equal_61: entity work.equal_5(INTERFACE) port map (a(4)=>freeze_c,a(3)=>stop_c, + a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c,b(4)=>pwr, + b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>n303,o=>n229); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(294) + equal_62: entity work.equal_5(INTERFACE) port map (a(4)=>ns_rx_sync(4), + a(3)=>ns_rx_sync(3),a(2)=>ns_rx_sync(2),a(1)=>ns_rx_sync(1),a(0)=>ns_rx_sync(0), + b(4)=>pwr,b(3)=>n303,b(2)=>n303,b(1)=>n303,b(0)=>n303,o=>n230); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(294) + n231 <= n229 and n230; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(294) + n232 <= pwr when n231='1' else not_uddcntln; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(297) + equal_65: entity work.equal_5(INTERFACE) port map (a(4)=>freeze_c,a(3)=>stop_c, + a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c,b(4)=>pwr, + b(3)=>n303,b(2)=>n303,b(1)=>n303,b(0)=>n303,o=>n233); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(300) + equal_66: entity work.equal_5(INTERFACE) port map (a(4)=>ns_rx_sync(4), + a(3)=>ns_rx_sync(3),a(2)=>ns_rx_sync(2),a(1)=>ns_rx_sync(1),a(0)=>ns_rx_sync(0), + b(4)=>pwr,b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>n303,o=>n234); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(300) + n235 <= n233 and n234; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(300) + n236 <= pwr when n235='1' else assert_stop; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(303) + equal_69: entity work.equal_5(INTERFACE) port map (a(4)=>freeze_c,a(3)=>stop_c, + a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c,b(4)=>pwr, + b(3)=>pwr,b(2)=>n303,b(1)=>pwr,b(0)=>n303,o=>n237); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(306) + equal_70: entity work.equal_5(INTERFACE) port map (a(4)=>ns_rx_sync(4), + a(3)=>ns_rx_sync(3),a(2)=>ns_rx_sync(2),a(1)=>ns_rx_sync(1),a(0)=>ns_rx_sync(0), + b(4)=>pwr,b(3)=>pwr,b(2)=>pwr,b(1)=>pwr,b(0)=>n303,o=>n238); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(306) + n239 <= n237 and n238; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(306) + n240 <= pwr when n239='1' else not_reset; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(309) + equal_73: entity work.equal_5(INTERFACE) port map (a(4)=>freeze_c,a(3)=>stop_c, + a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c,b(4)=>pwr, + b(3)=>pwr,b(2)=>pwr,b(1)=>pwr,b(0)=>n303,o=>n241); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(312) + equal_74: entity work.equal_5(INTERFACE) port map (a(4)=>ns_rx_sync(4), + a(3)=>ns_rx_sync(3),a(2)=>ns_rx_sync(2),a(1)=>ns_rx_sync(1),a(0)=>ns_rx_sync(0), + b(4)=>pwr,b(3)=>pwr,b(2)=>n303,b(1)=>pwr,b(0)=>n303,o=>n242); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(312) + n243 <= n241 and n242; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(312) + n244 <= pwr when n243='1' else not_stop; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(315) + equal_77: entity work.equal_5(INTERFACE) port map (a(4)=>freeze_c,a(3)=>stop_c, + a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c,b(4)=>pwr, + b(3)=>pwr,b(2)=>n303,b(1)=>pwr,b(0)=>n303,o=>n245); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(318) + equal_78: entity work.equal_5(INTERFACE) port map (a(4)=>ns_rx_sync(4), + a(3)=>ns_rx_sync(3),a(2)=>ns_rx_sync(2),a(1)=>ns_rx_sync(1),a(0)=>ns_rx_sync(0), + b(4)=>pwr,b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>n303,o=>n246); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(318) + n247 <= n245 and n246; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(318) + n248 <= pwr when n247='1' else not_freeze; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(322) + n249 <= n303 when n247='1' else n236; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(322) + equal_82: entity work.equal_5(INTERFACE) port map (a(4)=>freeze_c,a(3)=>stop_c, + a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c,b(4)=>pwr, + b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>n303,o=>n250); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(325) + equal_83: entity work.equal_5(INTERFACE) port map (a(4)=>ns_rx_sync(4), + a(3)=>ns_rx_sync(3),a(2)=>ns_rx_sync(2),a(1)=>ns_rx_sync(1),a(0)=>ns_rx_sync(0), + b(4)=>n303,b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>n303,o=>n251); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(325) + n252 <= n250 and n251; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(325) + n253 <= pwr when n252='1' else get_ready; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(328) + equal_86: entity work.equal_5(INTERFACE) port map (a(4)=>freeze_c,a(3)=>stop_c, + a(2)=>cs_rx_sync(2),a(1)=>uddcntln_c,a(0)=>ready_c,b(4)=>n303, + b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>pwr,o=>n254); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(332) + equal_87: entity work.equal_5(INTERFACE) port map (a(4)=>ns_rx_sync(4), + a(3)=>ns_rx_sync(3),a(2)=>ns_rx_sync(2),a(1)=>ns_rx_sync(1),a(0)=>ns_rx_sync(0), + b(4)=>n303,b(3)=>n303,b(2)=>n303,b(1)=>pwr,b(0)=>n303,o=>n255); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(332) + n256 <= n254 and n255; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(332) + n257 <= n303 when n256='1' else n248; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(344) + n258 <= n303 when n256='1' else n249; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(344) + n259 <= n303 when n256='1' else n244; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(344) + n260 <= n303 when n256='1' else n240; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(344) + n261 <= n303 when n256='1' else n232; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(344) + n262 <= n303 when n256='1' else n253; -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(344) + mux_95: entity work.mux_3(INTERFACE) port map (d0(2)=>n225(2),d0(1)=>n225(1), + d0(0)=>n225(0),d1(2)=>n303,d1(1)=>n303,d1(0)=>n303,cond=>n256, + o(2)=>n263(2),o(1)=>n263(1),o(0)=>n263(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(344) + mux_96: entity work.mux_3(INTERFACE) port map (d0(2)=>n134(2),d0(1)=>n134(1), + d0(0)=>n134(0),d1(2)=>n303,d1(1)=>n303,d1(0)=>n303,cond=>n256, + o(2)=>n267(2),o(1)=>n267(1),o(0)=>n267(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(344) + mux_97: entity work.mux_3(INTERFACE) port map (d0(2)=>n185(2),d0(1)=>n185(1), + d0(0)=>n185(0),d1(2)=>n303,d1(1)=>n303,d1(0)=>n303,cond=>n256, + o(2)=>n271(2),o(1)=>n271(1),o(0)=>n271(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(344) + ctrl_cnt_c: entity work.wide_dffrs_3(INTERFACE) port map (d(2)=>n271(2), + d(1)=>n271(1),d(0)=>n271(0),set(2)=>n303,set(1)=>n303,set(0)=>n303, + reset(2)=>rst,reset(1)=>rst,reset(0)=>rst,clock=>sync_clk,q(2)=>ctrl_cnt(2), + q(1)=>ctrl_cnt(1),q(0)=>ctrl_cnt(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(346) + dll_lock_cnt_c: entity work.wide_dffrs_3(INTERFACE) port map (d(2)=>n267(2), + d(1)=>n267(1),d(0)=>n267(0),set(2)=>n303,set(1)=>n303,set(0)=>n303, + reset(2)=>rst,reset(1)=>rst,reset(0)=>rst,clock=>sync_clk,q(2)=>dll_lock_cnt(2), + q(1)=>dll_lock_cnt(1),q(0)=>dll_lock_cnt(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(346) + ready_cnt_c: entity work.wide_dffrs_3(INTERFACE) port map (d(2)=>n263(2), + d(1)=>n263(1),d(0)=>n263(0),set(2)=>n303,set(1)=>n303,set(0)=>n303, + reset(2)=>rst,reset(1)=>rst,reset(0)=>rst,clock=>sync_clk,q(2)=>ready_cnt(2), + q(1)=>ready_cnt(1),q(0)=>ready_cnt(0)); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(346) + ddr_reset_d_118: VERIFIC_DFFRS (d=>n303,clk=>sync_clk,s=>rst,r=>gnd, + q=>ddr_reset_d); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(346) + dll_reset_119: VERIFIC_DFFRS (d=>n256,clk=>sync_clk,s=>rst,r=>gnd,q=>dll_reset_c); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(346) + not_uddcntln_120: VERIFIC_DFFRS (d=>n261,clk=>sync_clk,s=>n303,r=>rst, + q=>not_uddcntln); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(346) + assert_stop_121: VERIFIC_DFFRS (d=>n258,clk=>sync_clk,s=>n303,r=>rst, + q=>assert_stop); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(346) + not_reset_122: VERIFIC_DFFRS (d=>n260,clk=>sync_clk,s=>n303,r=>rst,q=>not_reset); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(346) + not_stop_123: VERIFIC_DFFRS (d=>n259,clk=>sync_clk,s=>n303,r=>rst,q=>not_stop); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(346) + not_freeze_124: VERIFIC_DFFRS (d=>n257,clk=>sync_clk,s=>n303,r=>rst, + q=>not_freeze); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(346) + get_ready_125: VERIFIC_DFFRS (d=>n262,clk=>sync_clk,s=>n303,r=>rst,q=>get_ready); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(346) + dll_lock_q1_111: VERIFIC_DFFRS (d=>dll_lock,clk=>sync_clk,s=>n303,r=>rst, + q=>dll_lock_q1); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(238) + cs_rx_sync_c: entity work.wide_dffrs_5(INTERFACE) port map (d(4)=>ns_rx_sync(4), + d(3)=>ns_rx_sync(3),d(2)=>ns_rx_sync(2),d(1)=>ns_rx_sync(1),d(0)=>ns_rx_sync(0), + set(4)=>n303,set(3)=>n303,set(2)=>n303,set(1)=>rst,set(0)=>n303, + reset(4)=>rst,reset(3)=>rst,reset(2)=>rst,reset(1)=>gnd,reset(0)=>rst, + clock=>sync_clk,q(4)=>freeze_c,q(3)=>stop_c,q(2)=>cs_rx_sync(2), + q(1)=>uddcntln_c,q(0)=>ready_c); -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(346) + +end architecture input_4chrxdll_sync; -- syn_module_defined=1 -- /d/jspc29/lattice/diamond/3.12/ispfpga/sa5p00/data/rxdll_sync.v(25) + + +library IEEE; +use IEEE.std_logic_1164.all; +library ecp5um; +use ecp5um.components.all; + +entity input_4ch is + port ( + alignwd: in std_logic; + clkin: in std_logic; + sclk: out std_logic; + datain: in std_logic_vector(4 downto 0); + q: out std_logic_vector(19 downto 0)); +end input_4ch; + +architecture Structure of input_4ch is + + -- internal signal declarations + signal stop: std_logic; + signal scuba_vlo: std_logic; + signal dll_lock: std_logic; + signal freeze: std_logic; + signal uddcntln: std_logic; + signal dll_reset: std_logic; + signal clock_cflag: std_logic; + signal eclki: std_logic; + signal clock_direction: std_logic; + signal clock_move: std_logic; + signal clock_loadn: std_logic; + signal ddrdel: std_logic; + signal buf_clkin: std_logic; + signal qa4: std_logic; + signal qb4: std_logic; + signal qc4: std_logic; + signal qd4: std_logic; + signal qa3: std_logic; + signal qb3: std_logic; + signal qc3: std_logic; + signal qd3: std_logic; + signal qa2: std_logic; + signal qb2: std_logic; + signal qc2: std_logic; + signal qd2: std_logic; + signal qa1: std_logic; + signal qb1: std_logic; + signal qc1: std_logic; + signal qd1: std_logic; + signal qa0: std_logic; + signal qb0: std_logic; + signal qc0: std_logic; + signal qd0: std_logic; + signal reset: std_logic; + signal eclko: std_logic; + signal sclk_t: std_logic; + signal dataini_t4: std_logic; + signal dataini_t3: std_logic; + signal dataini_t2: std_logic; + signal dataini_t1: std_logic; + signal dataini_t0: std_logic; + signal buf_dataini4: std_logic; + signal buf_dataini3: std_logic; + signal buf_dataini2: std_logic; + signal buf_dataini1: std_logic; + signal buf_dataini0: std_logic; + + component input_4chrxdll_sync + port (rst: in std_logic; sync_clk: in std_logic; + update: in std_logic; dll_lock: in std_logic; + dll_reset: out std_logic; uddcntln: out std_logic; + freeze: out std_logic; stop: out std_logic; + ddr_reset: out std_logic; ready: out std_logic); + end component; + attribute IO_TYPE : string; + -- attribute IO_TYPE of Inst7_IB : label is "LVDS"; + attribute IO_TYPE of Inst1_IB4 : label is "LVDS"; + attribute IO_TYPE of Inst1_IB3 : label is "LVDS"; + attribute IO_TYPE of Inst1_IB2 : label is "LVDS"; + attribute IO_TYPE of Inst1_IB1 : label is "LVDS"; + attribute IO_TYPE of Inst1_IB0 : label is "LVDS"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + -- Inst7_IB: IB + -- port map (I=>clkin, O=>buf_clkin); + + Inst6_CLKDIVF: CLKDIVF + generic map (DIV=> "2.0") + port map (CLKI=>eclko, RST=>reset, ALIGNWD=>alignwd, + CDIVX=>sclk_t); +eclko <= clkin; + -- Inst5_ECLKSYNCB: ECLKSYNCB + -- port map (ECLKI=>eclki, STOP=>stop, ECLKO=>eclko); + -- + -- Inst_rxdll_sync: input_4chrxdll_sync + -- port map (rst => sync_reset, sync_clk => sync_clk, update => update, + -- dll_lock => dll_lock, dll_reset => dll_reset, uddcntln => uddcntln, + -- freeze => freeze, stop => stop, ddr_reset => reset, + -- ready => ready); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + -- Inst4_DDRDLLA: DDRDLLA + -- generic map (FORCE_MAX_DELAY=> "NO") + -- port map (CLK=>eclko, RST=>dll_reset, UDDCNTLN=>uddcntln, + -- FREEZE=>freeze, DDRDEL=>ddrdel, LOCK=>dll_lock, + -- DCNTL7=>dcntl(7), DCNTL6=>dcntl(6), DCNTL5=>dcntl(5), + -- DCNTL4=>dcntl(4), DCNTL3=>dcntl(3), DCNTL2=>dcntl(2), + -- DCNTL1=>dcntl(1), DCNTL0=>dcntl(0)); + + Inst3_DLLDELD: DLLDELD + port map (A=>buf_clkin, DDRDEL=>ddrdel, LOADN=>clock_loadn, + MOVE=>clock_move, DIRECTION=>clock_direction, Z=>eclki, + CFLAG=>clock_cflag); + + Inst2_IDDRX2F4: IDDRX2F + port map (D=>dataini_t4, SCLK=>sclk_t, ECLK=>eclko, RST=>reset, + ALIGNWD=>alignwd, Q3=>qd4, Q2=>qc4, Q1=>qb4, Q0=>qa4); + + Inst2_IDDRX2F3: IDDRX2F + port map (D=>dataini_t3, SCLK=>sclk_t, ECLK=>eclko, RST=>reset, + ALIGNWD=>alignwd, Q3=>qd3, Q2=>qc3, Q1=>qb3, Q0=>qa3); + + Inst2_IDDRX2F2: IDDRX2F + port map (D=>dataini_t2, SCLK=>sclk_t, ECLK=>eclko, RST=>reset, + ALIGNWD=>alignwd, Q3=>qd2, Q2=>qc2, Q1=>qb2, Q0=>qa2); + + Inst2_IDDRX2F1: IDDRX2F + port map (D=>dataini_t1, SCLK=>sclk_t, ECLK=>eclko, RST=>reset, + ALIGNWD=>alignwd, Q3=>qd1, Q2=>qc1, Q1=>qb1, Q0=>qa1); + + Inst2_IDDRX2F0: IDDRX2F + port map (D=>dataini_t0, SCLK=>sclk_t, ECLK=>eclko, RST=>reset, + ALIGNWD=>alignwd, Q3=>qd0, Q2=>qc0, Q1=>qb0, Q0=>qa0); + + udel_dataini4: DELAYG + generic map (DEL_VALUE=> 59, DEL_MODE=> "USER_DEFINED") + port map (A=>buf_dataini4, Z=>dataini_t4); + + udel_dataini3: DELAYG + generic map (DEL_VALUE=> 59, DEL_MODE=> "USER_DEFINED") + port map (A=>buf_dataini3, Z=>dataini_t3); + + udel_dataini2: DELAYG + generic map (DEL_VALUE=> 59, DEL_MODE=> "USER_DEFINED") + port map (A=>buf_dataini2, Z=>dataini_t2); + + udel_dataini1: DELAYG + generic map (DEL_VALUE=> 59, DEL_MODE=> "USER_DEFINED") + port map (A=>buf_dataini1, Z=>dataini_t1); + + udel_dataini0: DELAYG + generic map (DEL_VALUE=> 59, DEL_MODE=> "USER_DEFINED") + port map (A=>buf_dataini0, Z=>dataini_t0); + + Inst1_IB4: IB + port map (I=>datain(4), O=>buf_dataini4); + + Inst1_IB3: IB + port map (I=>datain(3), O=>buf_dataini3); + + Inst1_IB2: IB + port map (I=>datain(2), O=>buf_dataini2); + + Inst1_IB1: IB + port map (I=>datain(1), O=>buf_dataini1); + + Inst1_IB0: IB + port map (I=>datain(0), O=>buf_dataini0); + + sclk <= sclk_t; + q(19) <= qd4; + q(18) <= qc4; + q(17) <= qb4; + q(16) <= qa4; + q(15) <= qd3; + q(14) <= qc3; + q(13) <= qb3; + q(12) <= qa3; + q(11) <= qd2; + q(10) <= qc2; + q(9) <= qb2; + q(8) <= qa2; + q(7) <= qd1; + q(6) <= qc1; + q(5) <= qb1; + q(4) <= qa1; + q(3) <= qd0; + q(2) <= qc0; + q(1) <= qb0; + q(0) <= qa0; + clock_direction <= scuba_vlo; + clock_move <= scuba_vlo; + clock_loadn <= uddcntln; +end Structure; diff --git a/adc/cores/mulaccsub3/mulaccsub3.cst b/adc/cores/mulaccsub3/mulaccsub3.cst new file mode 100644 index 0000000..33be04f --- /dev/null +++ b/adc/cores/mulaccsub3/mulaccsub3.cst @@ -0,0 +1,3 @@ +Date=05/27/2024 +Time=10:38:56 + diff --git a/adc/cores/mulaccsub3/mulaccsub3.fdc b/adc/cores/mulaccsub3/mulaccsub3.fdc new file mode 100644 index 0000000..6fbcac9 --- /dev/null +++ b/adc/cores/mulaccsub3/mulaccsub3.fdc @@ -0,0 +1,2 @@ +###==== Start Configuration + diff --git a/adc/cores/mulaccsub3/mulaccsub3.lpc b/adc/cores/mulaccsub3/mulaccsub3.lpc new file mode 100644 index 0000000..dbe8267 --- /dev/null +++ b/adc/cores/mulaccsub3/mulaccsub3.lpc @@ -0,0 +1,67 @@ +[Device] +Family=ecp5um +PartType=LFE5UM-85F +PartName=LFE5UM-85F-8BG756C +SpeedGrade=8 +Package=CABGA756 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=MMAC +CoreRevision=2.2 +ModuleName=mulaccsub3 +SourceFormat=vhdl +ParameterFileVersion=1.0 +Date=05/27/2024 +Time=10:38:56 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +widtha=9 +widthb=18 +widthp=45 +gsr=ENABLED +area_speed=Area +reset=SYNC +addsub=ACCUM+MULTA-MULTB +InputA=Parallel +InputB=Parallel +SignedA=Signed +SignedB=Unsigned +shiftouta=0 +shiftoutb=0 +EnIRA=1 +EnIRB=1 +EnPR=0 +EnOR=1 +EnRST=1 +EnCE=1 +EnIRA=1 +EnIRAClk=CLK0 +EnIRACE=CE0 +EnIRARST=RST0 +EnIRB=1 +EnIRBClk=CLK0 +EnIRBCE=CE0 +EnIRBRST=RST0 +EnPR=0 +EnPRClk= +EnPRCE= +EnPRRST= +EnOR=1 +EnORClk=InputA +EnORCE=CE0 +EnORRST=InputA + +[Command] +cmd_line= -w -n mulaccsub3 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type dspmmac -widtha 9 -widthb 18 -widthp 45 -area -load -macsub -signed -unsignedb -rega -regaclk CLK0 -regace CE0 -regarst RST0 -regb -regbclk CLK0 -regbce CE0 -regbrst RST0 -rego -regoclk CLK0 -regorst RST0 -regoce CE0 -enable_sync -clk0 -ce0 -rst0 diff --git a/adc/cores/mulaccsub3/mulaccsub3.sbx b/adc/cores/mulaccsub3/mulaccsub3.sbx new file mode 100644 index 0000000..92a3a72 --- /dev/null +++ b/adc/cores/mulaccsub3/mulaccsub3.sbx @@ -0,0 +1,304 @@ + + + + Lattice Semiconductor Corporation + LEGACY + MMAC + 2.2 + + + Diamond_Simulation + simulation + + ./mulaccsub3.vhd + vhdlSource + + + + Diamond_Synthesis + synthesis + + ./mulaccsub3.vhd + vhdlSource + + + + + + Configuration + none + ${sbp_path}/generate_core.tcl + CONFIG + + + + + + + + LFE5UM-85F-8BG756C + synplify + 2024-05-27.10:34:05 + 2024-05-27.10:38:58 + 3.12.1.454 + VHDL + + false + false + false + false + false + false + false + false + false + false + LPM + PRIMARY + PRIMARY + false + false + + + + + + Family + ecp5um + + + OperatingCondition + COM + + + Package + CABGA756 + + + PartName + LFE5UM-85F-8BG756C + + + PartType + LFE5UM-85F + + + SpeedGrade + 8 + + + Status + P + + + + CoreName + MMAC + + + CoreRevision + 2.2 + + + CoreStatus + Demo + + + CoreType + LPM + + + Date + 05/27/2024 + + + ModuleName + mulaccsub3 + + + ParameterFileVersion + 1.0 + + + SourceFormat + vhdl + + + Time + 10:38:56 + + + VendorName + Lattice Semiconductor Corporation + + + + Destination + Synplicity + + + EDIF + 1 + + + EnCE + 1 + + + EnIRA + 1 + + + EnIRACE + CE0 + + + EnIRAClk + CLK0 + + + EnIRARST + RST0 + + + EnIRB + 1 + + + EnIRBCE + CE0 + + + EnIRBClk + CLK0 + + + EnIRBRST + RST0 + + + EnOR + 1 + + + EnORCE + CE0 + + + EnORClk + InputA + + + EnORRST + InputA + + + EnPR + 0 + + + EnPRCE + + + + EnPRClk + + + + EnPRRST + + + + EnRST + 1 + + + Expression + BusA(0 to 7) + + + IO + 0 + + + InputA + Parallel + + + InputB + Parallel + + + Order + Big Endian [MSB:LSB] + + + SignedA + Signed + + + SignedB + Unsigned + + + VHDL + 1 + + + Verilog + 0 + + + addsub + ACCUM+MULTA-MULTB + + + area_speed + Area + + + gsr + ENABLED + + + reset + SYNC + + + shiftouta + 0 + + + shiftoutb + 0 + + + widtha + 9 + + + widthb + 18 + + + widthp + 45 + + + + cmd_line + -w -n mulaccsub3 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type dspmmac -widtha 9 -widthb 18 -widthp 45 -area -load -macsub -signed -unsignedb -rega -regaclk CLK0 -regace CE0 -regarst RST0 -regb -regbclk CLK0 -regbce CE0 -regbrst RST0 -rego -regoclk CLK0 -regorst RST0 -regoce CE0 -enable_sync -clk0 -ce0 -rst0 + + + + + + + LATTICE + LOCAL + mulaccsub3 + 1.0 + + + + diff --git a/adc/cores/mulaccsub3/mulaccsub3.vhd b/adc/cores/mulaccsub3/mulaccsub3.vhd new file mode 100644 index 0000000..ebc9a22 --- /dev/null +++ b/adc/cores/mulaccsub3/mulaccsub3.vhd @@ -0,0 +1,942 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 +-- Module Version: 2.2 +--/d/jspc29/lattice/diamond/3.12/ispfpga/bin/lin64/scuba -w -n mulaccsub3 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type dspmmac -widtha 9 -widthb 18 -widthp 45 -area -load -macsub -signed -unsignedb -rega -regaclk CLK0 -regace CE0 -regarst RST0 -regb -regbclk CLK0 -regbce CE0 -regbrst RST0 -rego -regoclk CLK0 -regorst RST0 -regoce CE0 -enable_sync -clk0 -ce0 -rst0 -fdc /local/trb/git/trb5sc/adc/cores/mulaccsub3/mulaccsub3.fdc + +-- Mon May 27 10:38:58 2024 + +library IEEE; +use IEEE.std_logic_1164.all; +library ecp5um; +use ecp5um.components.all; + +entity mulaccsub3 is + port ( + CLK0: in std_logic; + CE0: in std_logic; + RST0: in std_logic; + ACCUMSLOAD: in std_logic; + A0: in std_logic_vector(8 downto 0); + B0: in std_logic_vector(17 downto 0); + A1: in std_logic_vector(8 downto 0); + B1: in std_logic_vector(17 downto 0); + LD: in std_logic_vector(44 downto 0); + OVERFLOW: out std_logic; + ACCUM: out std_logic_vector(44 downto 0)); +end mulaccsub3; + +architecture Structure of mulaccsub3 is + + -- internal signal declarations + signal low_inv: std_logic; + signal under: std_logic; + signal over: std_logic; + signal mulaccsub3_alu_signedr_1_0: std_logic; + signal mulaccsub3_alu_output_r_1_0_53: std_logic; + signal mulaccsub3_alu_output_r_1_0_52: std_logic; + signal mulaccsub3_alu_output_r_1_0_51: std_logic; + signal mulaccsub3_alu_output_r_1_0_50: std_logic; + signal mulaccsub3_alu_output_r_1_0_49: std_logic; + signal mulaccsub3_alu_output_r_1_0_48: std_logic; + signal mulaccsub3_alu_output_r_1_0_47: std_logic; + signal mulaccsub3_alu_output_r_1_0_46: std_logic; + signal mulaccsub3_alu_output_r_1_0_45: std_logic; + signal mulaccsub3_alu_output_r_1_0_44: std_logic; + signal mulaccsub3_alu_output_r_1_0_43: std_logic; + signal mulaccsub3_alu_output_r_1_0_42: std_logic; + signal mulaccsub3_alu_output_r_1_0_41: std_logic; + signal mulaccsub3_alu_output_r_1_0_40: std_logic; + signal mulaccsub3_alu_output_r_1_0_39: std_logic; + signal mulaccsub3_alu_output_r_1_0_38: std_logic; + signal mulaccsub3_alu_output_r_1_0_37: std_logic; + signal mulaccsub3_alu_output_r_1_0_36: std_logic; + signal mulaccsub3_alu_output_r_1_0_35: std_logic; + signal mulaccsub3_alu_output_r_1_0_34: std_logic; + signal mulaccsub3_alu_output_r_1_0_33: std_logic; + signal mulaccsub3_alu_output_r_1_0_32: std_logic; + signal mulaccsub3_alu_output_r_1_0_31: std_logic; + signal mulaccsub3_alu_output_r_1_0_30: std_logic; + signal mulaccsub3_alu_output_r_1_0_29: std_logic; + signal mulaccsub3_alu_output_r_1_0_28: std_logic; + signal mulaccsub3_alu_output_r_1_0_27: std_logic; + signal mulaccsub3_alu_output_r_1_0_26: std_logic; + signal mulaccsub3_alu_output_r_1_0_25: std_logic; + signal mulaccsub3_alu_output_r_1_0_24: std_logic; + signal mulaccsub3_alu_output_r_1_0_23: std_logic; + signal mulaccsub3_alu_output_r_1_0_22: std_logic; + signal mulaccsub3_alu_output_r_1_0_21: std_logic; + signal mulaccsub3_alu_output_r_1_0_20: std_logic; + signal mulaccsub3_alu_output_r_1_0_19: std_logic; + signal mulaccsub3_alu_output_r_1_0_18: std_logic; + signal mulaccsub3_alu_output_r_1_0_17: std_logic; + signal mulaccsub3_alu_output_r_1_0_16: std_logic; + signal mulaccsub3_alu_output_r_1_0_15: std_logic; + signal mulaccsub3_alu_output_r_1_0_14: std_logic; + signal mulaccsub3_alu_output_r_1_0_13: std_logic; + signal mulaccsub3_alu_output_r_1_0_12: std_logic; + signal mulaccsub3_alu_output_r_1_0_11: std_logic; + signal mulaccsub3_alu_output_r_1_0_10: std_logic; + signal mulaccsub3_alu_output_r_1_0_9: std_logic; + signal mulaccsub3_alu_output_r_1_0_8: std_logic; + signal mulaccsub3_alu_output_r_1_0_7: std_logic; + signal mulaccsub3_alu_output_r_1_0_6: std_logic; + signal mulaccsub3_alu_output_r_1_0_5: std_logic; + signal mulaccsub3_alu_output_r_1_0_4: std_logic; + signal mulaccsub3_alu_output_r_1_0_3: std_logic; + signal mulaccsub3_alu_output_r_1_0_2: std_logic; + signal mulaccsub3_alu_output_r_1_0_1: std_logic; + signal mulaccsub3_alu_output_r_1_0_0: std_logic; + signal mulaccsub3_alu_signedcin_1_0: std_logic; + signal load_inv: std_logic; + signal mulaccsub3_alu_in_cin_1_0_53: std_logic; + signal mulaccsub3_alu_in_cin_1_0_52: std_logic; + signal mulaccsub3_alu_in_cin_1_0_51: std_logic; + signal mulaccsub3_alu_in_cin_1_0_50: std_logic; + signal mulaccsub3_alu_in_cin_1_0_49: std_logic; + signal mulaccsub3_alu_in_cin_1_0_48: std_logic; + signal mulaccsub3_alu_in_cin_1_0_47: std_logic; + signal mulaccsub3_alu_in_cin_1_0_46: std_logic; + signal mulaccsub3_alu_in_cin_1_0_45: std_logic; + signal mulaccsub3_alu_in_cin_1_0_44: std_logic; + signal mulaccsub3_alu_in_cin_1_0_43: std_logic; + signal mulaccsub3_alu_in_cin_1_0_42: std_logic; + signal mulaccsub3_alu_in_cin_1_0_41: std_logic; + signal mulaccsub3_alu_in_cin_1_0_40: std_logic; + signal mulaccsub3_alu_in_cin_1_0_39: std_logic; + signal mulaccsub3_alu_in_cin_1_0_38: std_logic; + signal mulaccsub3_alu_in_cin_1_0_37: std_logic; + signal mulaccsub3_alu_in_cin_1_0_36: std_logic; + signal mulaccsub3_alu_in_cin_1_0_35: std_logic; + signal mulaccsub3_alu_in_cin_1_0_34: std_logic; + signal mulaccsub3_alu_in_cin_1_0_33: std_logic; + signal mulaccsub3_alu_in_cin_1_0_32: std_logic; + signal mulaccsub3_alu_in_cin_1_0_31: std_logic; + signal mulaccsub3_alu_in_cin_1_0_30: std_logic; + signal mulaccsub3_alu_in_cin_1_0_29: std_logic; + signal mulaccsub3_alu_in_cin_1_0_28: std_logic; + signal mulaccsub3_alu_in_cin_1_0_27: std_logic; + signal mulaccsub3_alu_in_cin_1_0_26: std_logic; + signal mulaccsub3_alu_in_cin_1_0_25: std_logic; + signal mulaccsub3_alu_in_cin_1_0_24: std_logic; + signal mulaccsub3_alu_in_cin_1_0_23: std_logic; + signal mulaccsub3_alu_in_cin_1_0_22: std_logic; + signal mulaccsub3_alu_in_cin_1_0_21: std_logic; + signal mulaccsub3_alu_in_cin_1_0_20: std_logic; + signal mulaccsub3_alu_in_cin_1_0_19: std_logic; + signal mulaccsub3_alu_in_cin_1_0_18: std_logic; + signal mulaccsub3_alu_in_cin_1_0_17: std_logic; + signal mulaccsub3_alu_in_cin_1_0_16: std_logic; + signal mulaccsub3_alu_in_cin_1_0_15: std_logic; + signal mulaccsub3_alu_in_cin_1_0_14: std_logic; + signal mulaccsub3_alu_in_cin_1_0_13: std_logic; + signal mulaccsub3_alu_in_cin_1_0_12: std_logic; + signal mulaccsub3_alu_in_cin_1_0_11: std_logic; + signal mulaccsub3_alu_in_cin_1_0_10: std_logic; + signal mulaccsub3_alu_in_cin_1_0_9: std_logic; + signal mulaccsub3_alu_in_cin_1_0_8: std_logic; + signal mulaccsub3_alu_in_cin_1_0_7: std_logic; + signal mulaccsub3_alu_in_cin_1_0_6: std_logic; + signal mulaccsub3_alu_in_cin_1_0_5: std_logic; + signal mulaccsub3_alu_in_cin_1_0_4: std_logic; + signal mulaccsub3_alu_in_cin_1_0_3: std_logic; + signal mulaccsub3_alu_in_cin_1_0_2: std_logic; + signal mulaccsub3_alu_in_cin_1_0_1: std_logic; + signal mulaccsub3_alu_in_cin_1_0_0: std_logic; + signal mulaccsub3_0_mult_out_rob_0_17: std_logic; + signal mulaccsub3_0_mult_out_roa_0_17: std_logic; + signal mulaccsub3_0_mult_out_rob_0_16: std_logic; + signal mulaccsub3_0_mult_out_roa_0_16: std_logic; + signal mulaccsub3_0_mult_out_rob_0_15: std_logic; + signal mulaccsub3_0_mult_out_roa_0_15: std_logic; + signal mulaccsub3_0_mult_out_rob_0_14: std_logic; + signal mulaccsub3_0_mult_out_roa_0_14: std_logic; + signal mulaccsub3_0_mult_out_rob_0_13: std_logic; + signal mulaccsub3_0_mult_out_roa_0_13: std_logic; + signal mulaccsub3_0_mult_out_rob_0_12: std_logic; + signal mulaccsub3_0_mult_out_roa_0_12: std_logic; + signal mulaccsub3_0_mult_out_rob_0_11: std_logic; + signal mulaccsub3_0_mult_out_roa_0_11: std_logic; + signal mulaccsub3_0_mult_out_rob_0_10: std_logic; + signal mulaccsub3_0_mult_out_roa_0_10: std_logic; + signal mulaccsub3_0_mult_out_rob_0_9: std_logic; + signal mulaccsub3_0_mult_out_roa_0_9: std_logic; + signal mulaccsub3_0_mult_out_rob_0_8: std_logic; + signal mulaccsub3_0_mult_out_roa_0_8: std_logic; + signal mulaccsub3_0_mult_out_rob_0_7: std_logic; + signal mulaccsub3_0_mult_out_roa_0_7: std_logic; + signal mulaccsub3_0_mult_out_rob_0_6: std_logic; + signal mulaccsub3_0_mult_out_roa_0_6: std_logic; + signal mulaccsub3_0_mult_out_rob_0_5: std_logic; + signal mulaccsub3_0_mult_out_roa_0_5: std_logic; + signal mulaccsub3_0_mult_out_rob_0_4: std_logic; + signal mulaccsub3_0_mult_out_roa_0_4: std_logic; + signal mulaccsub3_0_mult_out_rob_0_3: std_logic; + signal mulaccsub3_0_mult_out_roa_0_3: std_logic; + signal mulaccsub3_0_mult_out_rob_0_2: std_logic; + signal mulaccsub3_0_mult_out_roa_0_2: std_logic; + signal mulaccsub3_0_mult_out_rob_0_1: std_logic; + signal mulaccsub3_0_mult_out_roa_0_1: std_logic; + signal mulaccsub3_0_mult_out_rob_0_0: std_logic; + signal mulaccsub3_0_mult_out_roa_0_0: std_logic; + signal mulaccsub3_0_mult_out_p_0_35: std_logic; + signal mulaccsub3_0_mult_out_p_0_34: std_logic; + signal mulaccsub3_0_mult_out_p_0_33: std_logic; + signal mulaccsub3_0_mult_out_p_0_32: std_logic; + signal mulaccsub3_0_mult_out_p_0_31: std_logic; + signal mulaccsub3_0_mult_out_p_0_30: std_logic; + signal mulaccsub3_0_mult_out_p_0_29: std_logic; + signal mulaccsub3_0_mult_out_p_0_28: std_logic; + signal mulaccsub3_0_mult_out_p_0_27: std_logic; + signal mulaccsub3_0_mult_out_p_0_26: std_logic; + signal mulaccsub3_0_mult_out_p_0_25: std_logic; + signal mulaccsub3_0_mult_out_p_0_24: std_logic; + signal mulaccsub3_0_mult_out_p_0_23: std_logic; + signal mulaccsub3_0_mult_out_p_0_22: std_logic; + signal mulaccsub3_0_mult_out_p_0_21: std_logic; + signal mulaccsub3_0_mult_out_p_0_20: std_logic; + signal mulaccsub3_0_mult_out_p_0_19: std_logic; + signal mulaccsub3_0_mult_out_p_0_18: std_logic; + signal mulaccsub3_0_mult_out_p_0_17: std_logic; + signal mulaccsub3_0_mult_out_p_0_16: std_logic; + signal mulaccsub3_0_mult_out_p_0_15: std_logic; + signal mulaccsub3_0_mult_out_p_0_14: std_logic; + signal mulaccsub3_0_mult_out_p_0_13: std_logic; + signal mulaccsub3_0_mult_out_p_0_12: std_logic; + signal mulaccsub3_0_mult_out_p_0_11: std_logic; + signal mulaccsub3_0_mult_out_p_0_10: std_logic; + signal mulaccsub3_0_mult_out_p_0_9: std_logic; + signal mulaccsub3_0_mult_out_p_0_8: std_logic; + signal mulaccsub3_0_mult_out_p_0_7: std_logic; + signal mulaccsub3_0_mult_out_p_0_6: std_logic; + signal mulaccsub3_0_mult_out_p_0_5: std_logic; + signal mulaccsub3_0_mult_out_p_0_4: std_logic; + signal mulaccsub3_0_mult_out_p_0_3: std_logic; + signal mulaccsub3_0_mult_out_p_0_2: std_logic; + signal mulaccsub3_0_mult_out_p_0_1: std_logic; + signal mulaccsub3_0_mult_out_p_0_0: std_logic; + signal mulaccsub3_0_mult_out_signedp_0: std_logic; + signal mulaccsub3_0_mult_out_rob_1_17: std_logic; + signal mulaccsub3_0_mult_out_roa_1_17: std_logic; + signal mulaccsub3_0_mult_out_rob_1_16: std_logic; + signal mulaccsub3_0_mult_out_roa_1_16: std_logic; + signal mulaccsub3_0_mult_out_rob_1_15: std_logic; + signal mulaccsub3_0_mult_out_roa_1_15: std_logic; + signal mulaccsub3_0_mult_out_rob_1_14: std_logic; + signal mulaccsub3_0_mult_out_roa_1_14: std_logic; + signal mulaccsub3_0_mult_out_rob_1_13: std_logic; + signal mulaccsub3_0_mult_out_roa_1_13: std_logic; + signal mulaccsub3_0_mult_out_rob_1_12: std_logic; + signal mulaccsub3_0_mult_out_roa_1_12: std_logic; + signal mulaccsub3_0_mult_out_rob_1_11: std_logic; + signal mulaccsub3_0_mult_out_roa_1_11: std_logic; + signal mulaccsub3_0_mult_out_rob_1_10: std_logic; + signal mulaccsub3_0_mult_out_roa_1_10: std_logic; + signal mulaccsub3_0_mult_out_rob_1_9: std_logic; + signal mulaccsub3_0_mult_out_roa_1_9: std_logic; + signal mulaccsub3_0_mult_out_rob_1_8: std_logic; + signal mulaccsub3_0_mult_out_roa_1_8: std_logic; + signal mulaccsub3_0_mult_out_rob_1_7: std_logic; + signal mulaccsub3_0_mult_out_roa_1_7: std_logic; + signal mulaccsub3_0_mult_out_rob_1_6: std_logic; + signal mulaccsub3_0_mult_out_roa_1_6: std_logic; + signal mulaccsub3_0_mult_out_rob_1_5: std_logic; + signal mulaccsub3_0_mult_out_roa_1_5: std_logic; + signal mulaccsub3_0_mult_out_rob_1_4: std_logic; + signal mulaccsub3_0_mult_out_roa_1_4: std_logic; + signal mulaccsub3_0_mult_out_rob_1_3: std_logic; + signal mulaccsub3_0_mult_out_roa_1_3: std_logic; + signal mulaccsub3_0_mult_out_rob_1_2: std_logic; + signal mulaccsub3_0_mult_out_roa_1_2: std_logic; + signal mulaccsub3_0_mult_out_rob_1_1: std_logic; + signal mulaccsub3_0_mult_out_roa_1_1: std_logic; + signal mulaccsub3_0_mult_out_rob_1_0: std_logic; + signal mulaccsub3_0_mult_out_roa_1_0: std_logic; + signal mulaccsub3_0_mult_out_p_1_35: std_logic; + signal mulaccsub3_0_mult_out_p_1_34: std_logic; + signal mulaccsub3_0_mult_out_p_1_33: std_logic; + signal mulaccsub3_0_mult_out_p_1_32: std_logic; + signal mulaccsub3_0_mult_out_p_1_31: std_logic; + signal mulaccsub3_0_mult_out_p_1_30: std_logic; + signal mulaccsub3_0_mult_out_p_1_29: std_logic; + signal mulaccsub3_0_mult_out_p_1_28: std_logic; + signal mulaccsub3_0_mult_out_p_1_27: std_logic; + signal mulaccsub3_0_mult_out_p_1_26: std_logic; + signal mulaccsub3_0_mult_out_p_1_25: std_logic; + signal mulaccsub3_0_mult_out_p_1_24: std_logic; + signal mulaccsub3_0_mult_out_p_1_23: std_logic; + signal mulaccsub3_0_mult_out_p_1_22: std_logic; + signal mulaccsub3_0_mult_out_p_1_21: std_logic; + signal mulaccsub3_0_mult_out_p_1_20: std_logic; + signal mulaccsub3_0_mult_out_p_1_19: std_logic; + signal mulaccsub3_0_mult_out_p_1_18: std_logic; + signal mulaccsub3_0_mult_out_p_1_17: std_logic; + signal mulaccsub3_0_mult_out_p_1_16: std_logic; + signal mulaccsub3_0_mult_out_p_1_15: std_logic; + signal mulaccsub3_0_mult_out_p_1_14: std_logic; + signal mulaccsub3_0_mult_out_p_1_13: std_logic; + signal mulaccsub3_0_mult_out_p_1_12: std_logic; + signal mulaccsub3_0_mult_out_p_1_11: std_logic; + signal mulaccsub3_0_mult_out_p_1_10: std_logic; + signal mulaccsub3_0_mult_out_p_1_9: std_logic; + signal mulaccsub3_0_mult_out_p_1_8: std_logic; + signal mulaccsub3_0_mult_out_p_1_7: std_logic; + signal mulaccsub3_0_mult_out_p_1_6: std_logic; + signal mulaccsub3_0_mult_out_p_1_5: std_logic; + signal mulaccsub3_0_mult_out_p_1_4: std_logic; + signal mulaccsub3_0_mult_out_p_1_3: std_logic; + signal mulaccsub3_0_mult_out_p_1_2: std_logic; + signal mulaccsub3_0_mult_out_p_1_1: std_logic; + signal mulaccsub3_0_mult_out_p_1_0: std_logic; + signal mulaccsub3_0_mult_out_signedp_1: std_logic; + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + INV_1: INV + port map (A=>scuba_vlo, Z=>low_inv); + + INV_0: INV + port map (A=>ACCUMSLOAD, Z=>load_inv); + + OR2_t0: OR2 + port map (A=>over, B=>under, Z=>OVERFLOW); + + dsp_alu_0: ALU54B + generic map (CLK3_DIV=> "ENABLED", CLK2_DIV=> "ENABLED", + CLK1_DIV=> "ENABLED", CLK0_DIV=> "ENABLED", REG_INPUTCFB_RST=> "RST0", + REG_INPUTCFB_CE=> "CE0", REG_INPUTCFB_CLK=> "NONE", + REG_OPCODEIN_1_RST=> "RST0", REG_OPCODEIN_1_CE=> "CE0", + REG_OPCODEIN_1_CLK=> "NONE", REG_OPCODEIN_0_RST=> "RST0", + REG_OPCODEIN_0_CE=> "CE0", REG_OPCODEIN_0_CLK=> "NONE", + REG_OPCODEOP1_1_CLK=> "NONE", REG_OPCODEOP1_0_CLK=> "NONE", + REG_OPCODEOP0_1_RST=> "RST0", REG_OPCODEOP0_1_CE=> "CE0", + REG_OPCODEOP0_1_CLK=> "NONE", REG_OPCODEOP0_0_RST=> "RST0", + REG_OPCODEOP0_0_CE=> "CE0", REG_OPCODEOP0_0_CLK=> "NONE", + REG_INPUTC1_RST=> "RST0", REG_INPUTC1_CE=> "CE0", + REG_INPUTC1_CLK=> "NONE", REG_INPUTC0_RST=> "RST0", + REG_INPUTC0_CE=> "CE0", REG_INPUTC0_CLK=> "NONE", LEGACY=> "DISABLED", + REG_FLAG_RST=> "RST0", REG_FLAG_CE=> "CE0", REG_FLAG_CLK=> "CLK0", + REG_OUTPUT1_RST=> "RST0", REG_OUTPUT1_CE=> "CE0", + REG_OUTPUT1_CLK=> "CLK0", REG_OUTPUT0_RST=> "RST0", + REG_OUTPUT0_CE=> "CE0", REG_OUTPUT0_CLK=> "CLK0", MULT9_MODE=> "DISABLED", + RNDPAT=> "0x00000000000000", MASKPAT=> "0x00000000000000", MCPAT=> "0x00000000000000", + MASK01=> "0x1FFFFFFFFFFFFF", MASKPAT_SOURCE=> "STATIC", + MCPAT_SOURCE=> "STATIC", RESETMODE=> "SYNC", GSR=> "ENABLED") + port map (A35=>mulaccsub3_0_mult_out_rob_0_17, + A34=>mulaccsub3_0_mult_out_rob_0_16, + A33=>mulaccsub3_0_mult_out_rob_0_15, + A32=>mulaccsub3_0_mult_out_rob_0_14, + A31=>mulaccsub3_0_mult_out_rob_0_13, + A30=>mulaccsub3_0_mult_out_rob_0_12, + A29=>mulaccsub3_0_mult_out_rob_0_11, + A28=>mulaccsub3_0_mult_out_rob_0_10, + A27=>mulaccsub3_0_mult_out_rob_0_9, + A26=>mulaccsub3_0_mult_out_rob_0_8, + A25=>mulaccsub3_0_mult_out_rob_0_7, + A24=>mulaccsub3_0_mult_out_rob_0_6, + A23=>mulaccsub3_0_mult_out_rob_0_5, + A22=>mulaccsub3_0_mult_out_rob_0_4, + A21=>mulaccsub3_0_mult_out_rob_0_3, + A20=>mulaccsub3_0_mult_out_rob_0_2, + A19=>mulaccsub3_0_mult_out_rob_0_1, + A18=>mulaccsub3_0_mult_out_rob_0_0, + A17=>mulaccsub3_0_mult_out_roa_0_17, + A16=>mulaccsub3_0_mult_out_roa_0_16, + A15=>mulaccsub3_0_mult_out_roa_0_15, + A14=>mulaccsub3_0_mult_out_roa_0_14, + A13=>mulaccsub3_0_mult_out_roa_0_13, + A12=>mulaccsub3_0_mult_out_roa_0_12, + A11=>mulaccsub3_0_mult_out_roa_0_11, + A10=>mulaccsub3_0_mult_out_roa_0_10, + A9=>mulaccsub3_0_mult_out_roa_0_9, + A8=>mulaccsub3_0_mult_out_roa_0_8, + A7=>mulaccsub3_0_mult_out_roa_0_7, + A6=>mulaccsub3_0_mult_out_roa_0_6, + A5=>mulaccsub3_0_mult_out_roa_0_5, + A4=>mulaccsub3_0_mult_out_roa_0_4, + A3=>mulaccsub3_0_mult_out_roa_0_3, + A2=>mulaccsub3_0_mult_out_roa_0_2, + A1=>mulaccsub3_0_mult_out_roa_0_1, + A0=>mulaccsub3_0_mult_out_roa_0_0, + B35=>mulaccsub3_0_mult_out_rob_1_17, + B34=>mulaccsub3_0_mult_out_rob_1_16, + B33=>mulaccsub3_0_mult_out_rob_1_15, + B32=>mulaccsub3_0_mult_out_rob_1_14, + B31=>mulaccsub3_0_mult_out_rob_1_13, + B30=>mulaccsub3_0_mult_out_rob_1_12, + B29=>mulaccsub3_0_mult_out_rob_1_11, + B28=>mulaccsub3_0_mult_out_rob_1_10, + B27=>mulaccsub3_0_mult_out_rob_1_9, + B26=>mulaccsub3_0_mult_out_rob_1_8, + B25=>mulaccsub3_0_mult_out_rob_1_7, + B24=>mulaccsub3_0_mult_out_rob_1_6, + B23=>mulaccsub3_0_mult_out_rob_1_5, + B22=>mulaccsub3_0_mult_out_rob_1_4, + B21=>mulaccsub3_0_mult_out_rob_1_3, + B20=>mulaccsub3_0_mult_out_rob_1_2, + B19=>mulaccsub3_0_mult_out_rob_1_1, + B18=>mulaccsub3_0_mult_out_rob_1_0, + B17=>mulaccsub3_0_mult_out_roa_1_17, + B16=>mulaccsub3_0_mult_out_roa_1_16, + B15=>mulaccsub3_0_mult_out_roa_1_15, + B14=>mulaccsub3_0_mult_out_roa_1_14, + B13=>mulaccsub3_0_mult_out_roa_1_13, + B12=>mulaccsub3_0_mult_out_roa_1_12, + B11=>mulaccsub3_0_mult_out_roa_1_11, + B10=>mulaccsub3_0_mult_out_roa_1_10, + B9=>mulaccsub3_0_mult_out_roa_1_9, + B8=>mulaccsub3_0_mult_out_roa_1_8, + B7=>mulaccsub3_0_mult_out_roa_1_7, + B6=>mulaccsub3_0_mult_out_roa_1_6, + B5=>mulaccsub3_0_mult_out_roa_1_5, + B4=>mulaccsub3_0_mult_out_roa_1_4, + B3=>mulaccsub3_0_mult_out_roa_1_3, + B2=>mulaccsub3_0_mult_out_roa_1_2, + B1=>mulaccsub3_0_mult_out_roa_1_1, + B0=>mulaccsub3_0_mult_out_roa_1_0, CFB53=>scuba_vlo, + CFB52=>scuba_vlo, CFB51=>scuba_vlo, CFB50=>scuba_vlo, + CFB49=>scuba_vlo, CFB48=>scuba_vlo, CFB47=>scuba_vlo, + CFB46=>scuba_vlo, CFB45=>scuba_vlo, CFB44=>scuba_vlo, + CFB43=>scuba_vlo, CFB42=>scuba_vlo, CFB41=>scuba_vlo, + CFB40=>scuba_vlo, CFB39=>scuba_vlo, CFB38=>scuba_vlo, + CFB37=>scuba_vlo, CFB36=>scuba_vlo, CFB35=>scuba_vlo, + CFB34=>scuba_vlo, CFB33=>scuba_vlo, CFB32=>scuba_vlo, + CFB31=>scuba_vlo, CFB30=>scuba_vlo, CFB29=>scuba_vlo, + CFB28=>scuba_vlo, CFB27=>scuba_vlo, CFB26=>scuba_vlo, + CFB25=>scuba_vlo, CFB24=>scuba_vlo, CFB23=>scuba_vlo, + CFB22=>scuba_vlo, CFB21=>scuba_vlo, CFB20=>scuba_vlo, + CFB19=>scuba_vlo, CFB18=>scuba_vlo, CFB17=>scuba_vlo, + CFB16=>scuba_vlo, CFB15=>scuba_vlo, CFB14=>scuba_vlo, + CFB13=>scuba_vlo, CFB12=>scuba_vlo, CFB11=>scuba_vlo, + CFB10=>scuba_vlo, CFB9=>scuba_vlo, CFB8=>scuba_vlo, + CFB7=>scuba_vlo, CFB6=>scuba_vlo, CFB5=>scuba_vlo, + CFB4=>scuba_vlo, CFB3=>scuba_vlo, CFB2=>scuba_vlo, + CFB1=>scuba_vlo, CFB0=>scuba_vlo, C53=>LD(44), C52=>LD(43), + C51=>LD(42), C50=>LD(41), C49=>LD(40), C48=>LD(39), + C47=>LD(38), C46=>LD(37), C45=>LD(36), C44=>LD(35), + C43=>LD(34), C42=>LD(33), C41=>LD(32), C40=>LD(31), + C39=>LD(30), C38=>LD(29), C37=>LD(28), C36=>LD(27), + C35=>LD(26), C34=>LD(25), C33=>LD(24), C32=>LD(23), + C31=>LD(22), C30=>LD(21), C29=>LD(20), C28=>LD(19), + C27=>LD(18), C26=>LD(17), C25=>LD(16), C24=>LD(15), + C23=>LD(14), C22=>LD(13), C21=>LD(12), C20=>LD(11), + C19=>LD(10), C18=>LD(9), C17=>LD(8), C16=>LD(7), C15=>LD(6), + C14=>LD(5), C13=>LD(4), C12=>LD(3), C11=>LD(2), C10=>LD(1), + C9=>LD(0), C8=>scuba_vlo, C7=>scuba_vlo, C6=>scuba_vlo, + C5=>scuba_vlo, C4=>scuba_vlo, C3=>scuba_vlo, C2=>scuba_vlo, + C1=>scuba_vlo, C0=>scuba_vlo, CE0=>CE0, CE1=>scuba_vhi, + CE2=>scuba_vhi, CE3=>scuba_vhi, CLK0=>CLK0, CLK1=>CLK0, + CLK2=>scuba_vlo, CLK3=>scuba_vlo, RST0=>RST0, + RST1=>scuba_vlo, RST2=>scuba_vlo, RST3=>scuba_vlo, + SIGNEDIA=>mulaccsub3_0_mult_out_signedp_0, + SIGNEDIB=>mulaccsub3_0_mult_out_signedp_1, + SIGNEDCIN=>mulaccsub3_alu_signedcin_1_0, + MA35=>mulaccsub3_0_mult_out_p_0_35, + MA34=>mulaccsub3_0_mult_out_p_0_34, + MA33=>mulaccsub3_0_mult_out_p_0_33, + MA32=>mulaccsub3_0_mult_out_p_0_32, + MA31=>mulaccsub3_0_mult_out_p_0_31, + MA30=>mulaccsub3_0_mult_out_p_0_30, + MA29=>mulaccsub3_0_mult_out_p_0_29, + MA28=>mulaccsub3_0_mult_out_p_0_28, + MA27=>mulaccsub3_0_mult_out_p_0_27, + MA26=>mulaccsub3_0_mult_out_p_0_26, + MA25=>mulaccsub3_0_mult_out_p_0_25, + MA24=>mulaccsub3_0_mult_out_p_0_24, + MA23=>mulaccsub3_0_mult_out_p_0_23, + MA22=>mulaccsub3_0_mult_out_p_0_22, + MA21=>mulaccsub3_0_mult_out_p_0_21, + MA20=>mulaccsub3_0_mult_out_p_0_20, + MA19=>mulaccsub3_0_mult_out_p_0_19, + MA18=>mulaccsub3_0_mult_out_p_0_18, + MA17=>mulaccsub3_0_mult_out_p_0_17, + MA16=>mulaccsub3_0_mult_out_p_0_16, + MA15=>mulaccsub3_0_mult_out_p_0_15, + MA14=>mulaccsub3_0_mult_out_p_0_14, + MA13=>mulaccsub3_0_mult_out_p_0_13, + MA12=>mulaccsub3_0_mult_out_p_0_12, + MA11=>mulaccsub3_0_mult_out_p_0_11, + MA10=>mulaccsub3_0_mult_out_p_0_10, + MA9=>mulaccsub3_0_mult_out_p_0_9, + MA8=>mulaccsub3_0_mult_out_p_0_8, + MA7=>mulaccsub3_0_mult_out_p_0_7, + MA6=>mulaccsub3_0_mult_out_p_0_6, + MA5=>mulaccsub3_0_mult_out_p_0_5, + MA4=>mulaccsub3_0_mult_out_p_0_4, + MA3=>mulaccsub3_0_mult_out_p_0_3, + MA2=>mulaccsub3_0_mult_out_p_0_2, + MA1=>mulaccsub3_0_mult_out_p_0_1, + MA0=>mulaccsub3_0_mult_out_p_0_0, + MB35=>mulaccsub3_0_mult_out_p_1_35, + MB34=>mulaccsub3_0_mult_out_p_1_34, + MB33=>mulaccsub3_0_mult_out_p_1_33, + MB32=>mulaccsub3_0_mult_out_p_1_32, + MB31=>mulaccsub3_0_mult_out_p_1_31, + MB30=>mulaccsub3_0_mult_out_p_1_30, + MB29=>mulaccsub3_0_mult_out_p_1_29, + MB28=>mulaccsub3_0_mult_out_p_1_28, + MB27=>mulaccsub3_0_mult_out_p_1_27, + MB26=>mulaccsub3_0_mult_out_p_1_26, + MB25=>mulaccsub3_0_mult_out_p_1_25, + MB24=>mulaccsub3_0_mult_out_p_1_24, + MB23=>mulaccsub3_0_mult_out_p_1_23, + MB22=>mulaccsub3_0_mult_out_p_1_22, + MB21=>mulaccsub3_0_mult_out_p_1_21, + MB20=>mulaccsub3_0_mult_out_p_1_20, + MB19=>mulaccsub3_0_mult_out_p_1_19, + MB18=>mulaccsub3_0_mult_out_p_1_18, + MB17=>mulaccsub3_0_mult_out_p_1_17, + MB16=>mulaccsub3_0_mult_out_p_1_16, + MB15=>mulaccsub3_0_mult_out_p_1_15, + MB14=>mulaccsub3_0_mult_out_p_1_14, + MB13=>mulaccsub3_0_mult_out_p_1_13, + MB12=>mulaccsub3_0_mult_out_p_1_12, + MB11=>mulaccsub3_0_mult_out_p_1_11, + MB10=>mulaccsub3_0_mult_out_p_1_10, + MB9=>mulaccsub3_0_mult_out_p_1_9, + MB8=>mulaccsub3_0_mult_out_p_1_8, + MB7=>mulaccsub3_0_mult_out_p_1_7, + MB6=>mulaccsub3_0_mult_out_p_1_6, + MB5=>mulaccsub3_0_mult_out_p_1_5, + MB4=>mulaccsub3_0_mult_out_p_1_4, + MB3=>mulaccsub3_0_mult_out_p_1_3, + MB2=>mulaccsub3_0_mult_out_p_1_2, + MB1=>mulaccsub3_0_mult_out_p_1_1, + MB0=>mulaccsub3_0_mult_out_p_1_0, + CIN53=>mulaccsub3_alu_in_cin_1_0_53, + CIN52=>mulaccsub3_alu_in_cin_1_0_52, + CIN51=>mulaccsub3_alu_in_cin_1_0_51, + CIN50=>mulaccsub3_alu_in_cin_1_0_50, + CIN49=>mulaccsub3_alu_in_cin_1_0_49, + CIN48=>mulaccsub3_alu_in_cin_1_0_48, + CIN47=>mulaccsub3_alu_in_cin_1_0_47, + CIN46=>mulaccsub3_alu_in_cin_1_0_46, + CIN45=>mulaccsub3_alu_in_cin_1_0_45, + CIN44=>mulaccsub3_alu_in_cin_1_0_44, + CIN43=>mulaccsub3_alu_in_cin_1_0_43, + CIN42=>mulaccsub3_alu_in_cin_1_0_42, + CIN41=>mulaccsub3_alu_in_cin_1_0_41, + CIN40=>mulaccsub3_alu_in_cin_1_0_40, + CIN39=>mulaccsub3_alu_in_cin_1_0_39, + CIN38=>mulaccsub3_alu_in_cin_1_0_38, + CIN37=>mulaccsub3_alu_in_cin_1_0_37, + CIN36=>mulaccsub3_alu_in_cin_1_0_36, + CIN35=>mulaccsub3_alu_in_cin_1_0_35, + CIN34=>mulaccsub3_alu_in_cin_1_0_34, + CIN33=>mulaccsub3_alu_in_cin_1_0_33, + CIN32=>mulaccsub3_alu_in_cin_1_0_32, + CIN31=>mulaccsub3_alu_in_cin_1_0_31, + CIN30=>mulaccsub3_alu_in_cin_1_0_30, + CIN29=>mulaccsub3_alu_in_cin_1_0_29, + CIN28=>mulaccsub3_alu_in_cin_1_0_28, + CIN27=>mulaccsub3_alu_in_cin_1_0_27, + CIN26=>mulaccsub3_alu_in_cin_1_0_26, + CIN25=>mulaccsub3_alu_in_cin_1_0_25, + CIN24=>mulaccsub3_alu_in_cin_1_0_24, + CIN23=>mulaccsub3_alu_in_cin_1_0_23, + CIN22=>mulaccsub3_alu_in_cin_1_0_22, + CIN21=>mulaccsub3_alu_in_cin_1_0_21, + CIN20=>mulaccsub3_alu_in_cin_1_0_20, + CIN19=>mulaccsub3_alu_in_cin_1_0_19, + CIN18=>mulaccsub3_alu_in_cin_1_0_18, + CIN17=>mulaccsub3_alu_in_cin_1_0_17, + CIN16=>mulaccsub3_alu_in_cin_1_0_16, + CIN15=>mulaccsub3_alu_in_cin_1_0_15, + CIN14=>mulaccsub3_alu_in_cin_1_0_14, + CIN13=>mulaccsub3_alu_in_cin_1_0_13, + CIN12=>mulaccsub3_alu_in_cin_1_0_12, + CIN11=>mulaccsub3_alu_in_cin_1_0_11, + CIN10=>mulaccsub3_alu_in_cin_1_0_10, + CIN9=>mulaccsub3_alu_in_cin_1_0_9, + CIN8=>mulaccsub3_alu_in_cin_1_0_8, + CIN7=>mulaccsub3_alu_in_cin_1_0_7, + CIN6=>mulaccsub3_alu_in_cin_1_0_6, + CIN5=>mulaccsub3_alu_in_cin_1_0_5, + CIN4=>mulaccsub3_alu_in_cin_1_0_4, + CIN3=>mulaccsub3_alu_in_cin_1_0_3, + CIN2=>mulaccsub3_alu_in_cin_1_0_2, + CIN1=>mulaccsub3_alu_in_cin_1_0_1, + CIN0=>mulaccsub3_alu_in_cin_1_0_0, OP10=>scuba_vlo, + OP9=>scuba_vhi, OP8=>scuba_vlo, OP7=>scuba_vhi, + OP6=>load_inv, OP5=>ACCUMSLOAD, OP4=>scuba_vhi, + OP3=>scuba_vlo, OP2=>scuba_vhi, OP1=>scuba_vlo, + OP0=>scuba_vhi, R53=>mulaccsub3_alu_output_r_1_0_53, + R52=>mulaccsub3_alu_output_r_1_0_52, + R51=>mulaccsub3_alu_output_r_1_0_51, + R50=>mulaccsub3_alu_output_r_1_0_50, + R49=>mulaccsub3_alu_output_r_1_0_49, + R48=>mulaccsub3_alu_output_r_1_0_48, + R47=>mulaccsub3_alu_output_r_1_0_47, + R46=>mulaccsub3_alu_output_r_1_0_46, + R45=>mulaccsub3_alu_output_r_1_0_45, + R44=>mulaccsub3_alu_output_r_1_0_44, + R43=>mulaccsub3_alu_output_r_1_0_43, + R42=>mulaccsub3_alu_output_r_1_0_42, + R41=>mulaccsub3_alu_output_r_1_0_41, + R40=>mulaccsub3_alu_output_r_1_0_40, + R39=>mulaccsub3_alu_output_r_1_0_39, + R38=>mulaccsub3_alu_output_r_1_0_38, + R37=>mulaccsub3_alu_output_r_1_0_37, + R36=>mulaccsub3_alu_output_r_1_0_36, + R35=>mulaccsub3_alu_output_r_1_0_35, + R34=>mulaccsub3_alu_output_r_1_0_34, + R33=>mulaccsub3_alu_output_r_1_0_33, + R32=>mulaccsub3_alu_output_r_1_0_32, + R31=>mulaccsub3_alu_output_r_1_0_31, + R30=>mulaccsub3_alu_output_r_1_0_30, + R29=>mulaccsub3_alu_output_r_1_0_29, + R28=>mulaccsub3_alu_output_r_1_0_28, + R27=>mulaccsub3_alu_output_r_1_0_27, + R26=>mulaccsub3_alu_output_r_1_0_26, + R25=>mulaccsub3_alu_output_r_1_0_25, + R24=>mulaccsub3_alu_output_r_1_0_24, + R23=>mulaccsub3_alu_output_r_1_0_23, + R22=>mulaccsub3_alu_output_r_1_0_22, + R21=>mulaccsub3_alu_output_r_1_0_21, + R20=>mulaccsub3_alu_output_r_1_0_20, + R19=>mulaccsub3_alu_output_r_1_0_19, + R18=>mulaccsub3_alu_output_r_1_0_18, + R17=>mulaccsub3_alu_output_r_1_0_17, + R16=>mulaccsub3_alu_output_r_1_0_16, + R15=>mulaccsub3_alu_output_r_1_0_15, + R14=>mulaccsub3_alu_output_r_1_0_14, + R13=>mulaccsub3_alu_output_r_1_0_13, + R12=>mulaccsub3_alu_output_r_1_0_12, + R11=>mulaccsub3_alu_output_r_1_0_11, + R10=>mulaccsub3_alu_output_r_1_0_10, + R9=>mulaccsub3_alu_output_r_1_0_9, + R8=>mulaccsub3_alu_output_r_1_0_8, + R7=>mulaccsub3_alu_output_r_1_0_7, + R6=>mulaccsub3_alu_output_r_1_0_6, + R5=>mulaccsub3_alu_output_r_1_0_5, + R4=>mulaccsub3_alu_output_r_1_0_4, + R3=>mulaccsub3_alu_output_r_1_0_3, + R2=>mulaccsub3_alu_output_r_1_0_2, + R1=>mulaccsub3_alu_output_r_1_0_1, + R0=>mulaccsub3_alu_output_r_1_0_0, CO53=>open, CO52=>open, + CO51=>open, CO50=>open, CO49=>open, CO48=>open, CO47=>open, + CO46=>open, CO45=>open, CO44=>open, CO43=>open, CO42=>open, + CO41=>open, CO40=>open, CO39=>open, CO38=>open, CO37=>open, + CO36=>open, CO35=>open, CO34=>open, CO33=>open, CO32=>open, + CO31=>open, CO30=>open, CO29=>open, CO28=>open, CO27=>open, + CO26=>open, CO25=>open, CO24=>open, CO23=>open, CO22=>open, + CO21=>open, CO20=>open, CO19=>open, CO18=>open, CO17=>open, + CO16=>open, CO15=>open, CO14=>open, CO13=>open, CO12=>open, + CO11=>open, CO10=>open, CO9=>open, CO8=>open, CO7=>open, + CO6=>open, CO5=>open, CO4=>open, CO3=>open, CO2=>open, + CO1=>open, CO0=>open, EQZ=>open, EQZM=>open, EQOM=>open, + EQPAT=>open, EQPATB=>open, OVER=>over, UNDER=>under, + OVERUNDER=>open, SIGNEDR=>mulaccsub3_alu_signedr_1_0); + + dsp_mult_1: MULT18X18D + generic map (CLK3_DIV=> "ENABLED", CLK2_DIV=> "ENABLED", + CLK1_DIV=> "ENABLED", CLK0_DIV=> "ENABLED", HIGHSPEED_CLK=> "NONE", + REG_INPUTC_RST=> "RST0", REG_INPUTC_CE=> "CE0", REG_INPUTC_CLK=> "NONE", + SOURCEB_MODE=> "B_SHIFT", MULT_BYPASS=> "DISABLED", + CAS_MATCH_REG=> "FALSE", RESETMODE=> "SYNC", GSR=> "ENABLED", + REG_OUTPUT_RST=> "RST0", REG_OUTPUT_CE=> "CE0", REG_OUTPUT_CLK=> "NONE", + REG_PIPELINE_RST=> "RST0", REG_PIPELINE_CE=> "CE0", + REG_PIPELINE_CLK=> "NONE", REG_INPUTB_RST=> "RST0", + REG_INPUTB_CE=> "CE0", REG_INPUTB_CLK=> "CLK0", REG_INPUTA_RST=> "RST0", + REG_INPUTA_CE=> "CE0", REG_INPUTA_CLK=> "CLK0") + port map (A17=>A0(8), A16=>A0(7), A15=>A0(6), A14=>A0(5), + A13=>A0(4), A12=>A0(3), A11=>A0(2), A10=>A0(1), A9=>A0(0), + A8=>scuba_vlo, A7=>scuba_vlo, A6=>scuba_vlo, A5=>scuba_vlo, + A4=>scuba_vlo, A3=>scuba_vlo, A2=>scuba_vlo, A1=>scuba_vlo, + A0=>scuba_vlo, B17=>B0(17), B16=>B0(16), B15=>B0(15), + B14=>B0(14), B13=>B0(13), B12=>B0(12), B11=>B0(11), + B10=>B0(10), B9=>B0(9), B8=>B0(8), B7=>B0(7), B6=>B0(6), + B5=>B0(5), B4=>B0(4), B3=>B0(3), B2=>B0(2), B1=>B0(1), + B0=>B0(0), C17=>scuba_vlo, C16=>scuba_vlo, C15=>scuba_vlo, + C14=>scuba_vlo, C13=>scuba_vlo, C12=>scuba_vlo, + C11=>scuba_vlo, C10=>scuba_vlo, C9=>scuba_vlo, C8=>scuba_vlo, + C7=>scuba_vlo, C6=>scuba_vlo, C5=>scuba_vlo, C4=>scuba_vlo, + C3=>scuba_vlo, C2=>scuba_vlo, C1=>scuba_vlo, C0=>scuba_vlo, + SIGNEDA=>scuba_vhi, SIGNEDB=>scuba_vlo, SOURCEA=>scuba_vlo, + SOURCEB=>scuba_vlo, CE0=>CE0, CE1=>scuba_vhi, CE2=>scuba_vhi, + CE3=>scuba_vhi, CLK0=>CLK0, CLK1=>scuba_vlo, CLK2=>scuba_vlo, + CLK3=>scuba_vlo, RST0=>RST0, RST1=>scuba_vlo, + RST2=>scuba_vlo, RST3=>scuba_vlo, SRIA17=>scuba_vlo, + SRIA16=>scuba_vlo, SRIA15=>scuba_vlo, SRIA14=>scuba_vlo, + SRIA13=>scuba_vlo, SRIA12=>scuba_vlo, SRIA11=>scuba_vlo, + SRIA10=>scuba_vlo, SRIA9=>scuba_vlo, SRIA8=>scuba_vlo, + SRIA7=>scuba_vlo, SRIA6=>scuba_vlo, SRIA5=>scuba_vlo, + SRIA4=>scuba_vlo, SRIA3=>scuba_vlo, SRIA2=>scuba_vlo, + SRIA1=>scuba_vlo, SRIA0=>scuba_vlo, SRIB17=>scuba_vlo, + SRIB16=>scuba_vlo, SRIB15=>scuba_vlo, SRIB14=>scuba_vlo, + SRIB13=>scuba_vlo, SRIB12=>scuba_vlo, SRIB11=>scuba_vlo, + SRIB10=>scuba_vlo, SRIB9=>scuba_vlo, SRIB8=>scuba_vlo, + SRIB7=>scuba_vlo, SRIB6=>scuba_vlo, SRIB5=>scuba_vlo, + SRIB4=>scuba_vlo, SRIB3=>scuba_vlo, SRIB2=>scuba_vlo, + SRIB1=>scuba_vlo, SRIB0=>scuba_vlo, SROA17=>open, + SROA16=>open, SROA15=>open, SROA14=>open, SROA13=>open, + SROA12=>open, SROA11=>open, SROA10=>open, SROA9=>open, + SROA8=>open, SROA7=>open, SROA6=>open, SROA5=>open, + SROA4=>open, SROA3=>open, SROA2=>open, SROA1=>open, + SROA0=>open, SROB17=>open, SROB16=>open, SROB15=>open, + SROB14=>open, SROB13=>open, SROB12=>open, SROB11=>open, + SROB10=>open, SROB9=>open, SROB8=>open, SROB7=>open, + SROB6=>open, SROB5=>open, SROB4=>open, SROB3=>open, + SROB2=>open, SROB1=>open, SROB0=>open, + ROA17=>mulaccsub3_0_mult_out_roa_0_17, + ROA16=>mulaccsub3_0_mult_out_roa_0_16, + ROA15=>mulaccsub3_0_mult_out_roa_0_15, + ROA14=>mulaccsub3_0_mult_out_roa_0_14, + ROA13=>mulaccsub3_0_mult_out_roa_0_13, + ROA12=>mulaccsub3_0_mult_out_roa_0_12, + ROA11=>mulaccsub3_0_mult_out_roa_0_11, + ROA10=>mulaccsub3_0_mult_out_roa_0_10, + ROA9=>mulaccsub3_0_mult_out_roa_0_9, + ROA8=>mulaccsub3_0_mult_out_roa_0_8, + ROA7=>mulaccsub3_0_mult_out_roa_0_7, + ROA6=>mulaccsub3_0_mult_out_roa_0_6, + ROA5=>mulaccsub3_0_mult_out_roa_0_5, + ROA4=>mulaccsub3_0_mult_out_roa_0_4, + ROA3=>mulaccsub3_0_mult_out_roa_0_3, + ROA2=>mulaccsub3_0_mult_out_roa_0_2, + ROA1=>mulaccsub3_0_mult_out_roa_0_1, + ROA0=>mulaccsub3_0_mult_out_roa_0_0, + ROB17=>mulaccsub3_0_mult_out_rob_0_17, + ROB16=>mulaccsub3_0_mult_out_rob_0_16, + ROB15=>mulaccsub3_0_mult_out_rob_0_15, + ROB14=>mulaccsub3_0_mult_out_rob_0_14, + ROB13=>mulaccsub3_0_mult_out_rob_0_13, + ROB12=>mulaccsub3_0_mult_out_rob_0_12, + ROB11=>mulaccsub3_0_mult_out_rob_0_11, + ROB10=>mulaccsub3_0_mult_out_rob_0_10, + ROB9=>mulaccsub3_0_mult_out_rob_0_9, + ROB8=>mulaccsub3_0_mult_out_rob_0_8, + ROB7=>mulaccsub3_0_mult_out_rob_0_7, + ROB6=>mulaccsub3_0_mult_out_rob_0_6, + ROB5=>mulaccsub3_0_mult_out_rob_0_5, + ROB4=>mulaccsub3_0_mult_out_rob_0_4, + ROB3=>mulaccsub3_0_mult_out_rob_0_3, + ROB2=>mulaccsub3_0_mult_out_rob_0_2, + ROB1=>mulaccsub3_0_mult_out_rob_0_1, + ROB0=>mulaccsub3_0_mult_out_rob_0_0, ROC17=>open, + ROC16=>open, ROC15=>open, ROC14=>open, ROC13=>open, + ROC12=>open, ROC11=>open, ROC10=>open, ROC9=>open, + ROC8=>open, ROC7=>open, ROC6=>open, ROC5=>open, ROC4=>open, + ROC3=>open, ROC2=>open, ROC1=>open, ROC0=>open, + P35=>mulaccsub3_0_mult_out_p_0_35, + P34=>mulaccsub3_0_mult_out_p_0_34, + P33=>mulaccsub3_0_mult_out_p_0_33, + P32=>mulaccsub3_0_mult_out_p_0_32, + P31=>mulaccsub3_0_mult_out_p_0_31, + P30=>mulaccsub3_0_mult_out_p_0_30, + P29=>mulaccsub3_0_mult_out_p_0_29, + P28=>mulaccsub3_0_mult_out_p_0_28, + P27=>mulaccsub3_0_mult_out_p_0_27, + P26=>mulaccsub3_0_mult_out_p_0_26, + P25=>mulaccsub3_0_mult_out_p_0_25, + P24=>mulaccsub3_0_mult_out_p_0_24, + P23=>mulaccsub3_0_mult_out_p_0_23, + P22=>mulaccsub3_0_mult_out_p_0_22, + P21=>mulaccsub3_0_mult_out_p_0_21, + P20=>mulaccsub3_0_mult_out_p_0_20, + P19=>mulaccsub3_0_mult_out_p_0_19, + P18=>mulaccsub3_0_mult_out_p_0_18, + P17=>mulaccsub3_0_mult_out_p_0_17, + P16=>mulaccsub3_0_mult_out_p_0_16, + P15=>mulaccsub3_0_mult_out_p_0_15, + P14=>mulaccsub3_0_mult_out_p_0_14, + P13=>mulaccsub3_0_mult_out_p_0_13, + P12=>mulaccsub3_0_mult_out_p_0_12, + P11=>mulaccsub3_0_mult_out_p_0_11, + P10=>mulaccsub3_0_mult_out_p_0_10, + P9=>mulaccsub3_0_mult_out_p_0_9, + P8=>mulaccsub3_0_mult_out_p_0_8, + P7=>mulaccsub3_0_mult_out_p_0_7, + P6=>mulaccsub3_0_mult_out_p_0_6, + P5=>mulaccsub3_0_mult_out_p_0_5, + P4=>mulaccsub3_0_mult_out_p_0_4, + P3=>mulaccsub3_0_mult_out_p_0_3, + P2=>mulaccsub3_0_mult_out_p_0_2, + P1=>mulaccsub3_0_mult_out_p_0_1, + P0=>mulaccsub3_0_mult_out_p_0_0, + SIGNEDP=>mulaccsub3_0_mult_out_signedp_0); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + dsp_mult_0: MULT18X18D + generic map (CLK3_DIV=> "ENABLED", CLK2_DIV=> "ENABLED", + CLK1_DIV=> "ENABLED", CLK0_DIV=> "ENABLED", HIGHSPEED_CLK=> "NONE", + REG_INPUTC_RST=> "RST0", REG_INPUTC_CE=> "CE0", REG_INPUTC_CLK=> "NONE", + SOURCEB_MODE=> "B_SHIFT", MULT_BYPASS=> "DISABLED", + CAS_MATCH_REG=> "FALSE", RESETMODE=> "SYNC", GSR=> "ENABLED", + REG_OUTPUT_RST=> "RST0", REG_OUTPUT_CE=> "CE0", REG_OUTPUT_CLK=> "NONE", + REG_PIPELINE_RST=> "RST0", REG_PIPELINE_CE=> "CE0", + REG_PIPELINE_CLK=> "NONE", REG_INPUTB_RST=> "RST0", + REG_INPUTB_CE=> "CE0", REG_INPUTB_CLK=> "CLK0", REG_INPUTA_RST=> "RST0", + REG_INPUTA_CE=> "CE0", REG_INPUTA_CLK=> "CLK0") + port map (A17=>A1(8), A16=>A1(7), A15=>A1(6), A14=>A1(5), + A13=>A1(4), A12=>A1(3), A11=>A1(2), A10=>A1(1), A9=>A1(0), + A8=>scuba_vlo, A7=>scuba_vlo, A6=>scuba_vlo, A5=>scuba_vlo, + A4=>scuba_vlo, A3=>scuba_vlo, A2=>scuba_vlo, A1=>scuba_vlo, + A0=>scuba_vlo, B17=>B1(17), B16=>B1(16), B15=>B1(15), + B14=>B1(14), B13=>B1(13), B12=>B1(12), B11=>B1(11), + B10=>B1(10), B9=>B1(9), B8=>B1(8), B7=>B1(7), B6=>B1(6), + B5=>B1(5), B4=>B1(4), B3=>B1(3), B2=>B1(2), B1=>B1(1), + B0=>B1(0), C17=>scuba_vlo, C16=>scuba_vlo, C15=>scuba_vlo, + C14=>scuba_vlo, C13=>scuba_vlo, C12=>scuba_vlo, + C11=>scuba_vlo, C10=>scuba_vlo, C9=>scuba_vlo, C8=>scuba_vlo, + C7=>scuba_vlo, C6=>scuba_vlo, C5=>scuba_vlo, C4=>scuba_vlo, + C3=>scuba_vlo, C2=>scuba_vlo, C1=>scuba_vlo, C0=>scuba_vlo, + SIGNEDA=>scuba_vhi, SIGNEDB=>scuba_vlo, SOURCEA=>scuba_vlo, + SOURCEB=>scuba_vlo, CE0=>CE0, CE1=>scuba_vhi, CE2=>scuba_vhi, + CE3=>scuba_vhi, CLK0=>CLK0, CLK1=>scuba_vlo, CLK2=>scuba_vlo, + CLK3=>scuba_vlo, RST0=>RST0, RST1=>scuba_vlo, + RST2=>scuba_vlo, RST3=>scuba_vlo, SRIA17=>scuba_vlo, + SRIA16=>scuba_vlo, SRIA15=>scuba_vlo, SRIA14=>scuba_vlo, + SRIA13=>scuba_vlo, SRIA12=>scuba_vlo, SRIA11=>scuba_vlo, + SRIA10=>scuba_vlo, SRIA9=>scuba_vlo, SRIA8=>scuba_vlo, + SRIA7=>scuba_vlo, SRIA6=>scuba_vlo, SRIA5=>scuba_vlo, + SRIA4=>scuba_vlo, SRIA3=>scuba_vlo, SRIA2=>scuba_vlo, + SRIA1=>scuba_vlo, SRIA0=>scuba_vlo, SRIB17=>scuba_vlo, + SRIB16=>scuba_vlo, SRIB15=>scuba_vlo, SRIB14=>scuba_vlo, + SRIB13=>scuba_vlo, SRIB12=>scuba_vlo, SRIB11=>scuba_vlo, + SRIB10=>scuba_vlo, SRIB9=>scuba_vlo, SRIB8=>scuba_vlo, + SRIB7=>scuba_vlo, SRIB6=>scuba_vlo, SRIB5=>scuba_vlo, + SRIB4=>scuba_vlo, SRIB3=>scuba_vlo, SRIB2=>scuba_vlo, + SRIB1=>scuba_vlo, SRIB0=>scuba_vlo, SROA17=>open, + SROA16=>open, SROA15=>open, SROA14=>open, SROA13=>open, + SROA12=>open, SROA11=>open, SROA10=>open, SROA9=>open, + SROA8=>open, SROA7=>open, SROA6=>open, SROA5=>open, + SROA4=>open, SROA3=>open, SROA2=>open, SROA1=>open, + SROA0=>open, SROB17=>open, SROB16=>open, SROB15=>open, + SROB14=>open, SROB13=>open, SROB12=>open, SROB11=>open, + SROB10=>open, SROB9=>open, SROB8=>open, SROB7=>open, + SROB6=>open, SROB5=>open, SROB4=>open, SROB3=>open, + SROB2=>open, SROB1=>open, SROB0=>open, + ROA17=>mulaccsub3_0_mult_out_roa_1_17, + ROA16=>mulaccsub3_0_mult_out_roa_1_16, + ROA15=>mulaccsub3_0_mult_out_roa_1_15, + ROA14=>mulaccsub3_0_mult_out_roa_1_14, + ROA13=>mulaccsub3_0_mult_out_roa_1_13, + ROA12=>mulaccsub3_0_mult_out_roa_1_12, + ROA11=>mulaccsub3_0_mult_out_roa_1_11, + ROA10=>mulaccsub3_0_mult_out_roa_1_10, + ROA9=>mulaccsub3_0_mult_out_roa_1_9, + ROA8=>mulaccsub3_0_mult_out_roa_1_8, + ROA7=>mulaccsub3_0_mult_out_roa_1_7, + ROA6=>mulaccsub3_0_mult_out_roa_1_6, + ROA5=>mulaccsub3_0_mult_out_roa_1_5, + ROA4=>mulaccsub3_0_mult_out_roa_1_4, + ROA3=>mulaccsub3_0_mult_out_roa_1_3, + ROA2=>mulaccsub3_0_mult_out_roa_1_2, + ROA1=>mulaccsub3_0_mult_out_roa_1_1, + ROA0=>mulaccsub3_0_mult_out_roa_1_0, + ROB17=>mulaccsub3_0_mult_out_rob_1_17, + ROB16=>mulaccsub3_0_mult_out_rob_1_16, + ROB15=>mulaccsub3_0_mult_out_rob_1_15, + ROB14=>mulaccsub3_0_mult_out_rob_1_14, + ROB13=>mulaccsub3_0_mult_out_rob_1_13, + ROB12=>mulaccsub3_0_mult_out_rob_1_12, + ROB11=>mulaccsub3_0_mult_out_rob_1_11, + ROB10=>mulaccsub3_0_mult_out_rob_1_10, + ROB9=>mulaccsub3_0_mult_out_rob_1_9, + ROB8=>mulaccsub3_0_mult_out_rob_1_8, + ROB7=>mulaccsub3_0_mult_out_rob_1_7, + ROB6=>mulaccsub3_0_mult_out_rob_1_6, + ROB5=>mulaccsub3_0_mult_out_rob_1_5, + ROB4=>mulaccsub3_0_mult_out_rob_1_4, + ROB3=>mulaccsub3_0_mult_out_rob_1_3, + ROB2=>mulaccsub3_0_mult_out_rob_1_2, + ROB1=>mulaccsub3_0_mult_out_rob_1_1, + ROB0=>mulaccsub3_0_mult_out_rob_1_0, ROC17=>open, + ROC16=>open, ROC15=>open, ROC14=>open, ROC13=>open, + ROC12=>open, ROC11=>open, ROC10=>open, ROC9=>open, + ROC8=>open, ROC7=>open, ROC6=>open, ROC5=>open, ROC4=>open, + ROC3=>open, ROC2=>open, ROC1=>open, ROC0=>open, + P35=>mulaccsub3_0_mult_out_p_1_35, + P34=>mulaccsub3_0_mult_out_p_1_34, + P33=>mulaccsub3_0_mult_out_p_1_33, + P32=>mulaccsub3_0_mult_out_p_1_32, + P31=>mulaccsub3_0_mult_out_p_1_31, + P30=>mulaccsub3_0_mult_out_p_1_30, + P29=>mulaccsub3_0_mult_out_p_1_29, + P28=>mulaccsub3_0_mult_out_p_1_28, + P27=>mulaccsub3_0_mult_out_p_1_27, + P26=>mulaccsub3_0_mult_out_p_1_26, + P25=>mulaccsub3_0_mult_out_p_1_25, + P24=>mulaccsub3_0_mult_out_p_1_24, + P23=>mulaccsub3_0_mult_out_p_1_23, + P22=>mulaccsub3_0_mult_out_p_1_22, + P21=>mulaccsub3_0_mult_out_p_1_21, + P20=>mulaccsub3_0_mult_out_p_1_20, + P19=>mulaccsub3_0_mult_out_p_1_19, + P18=>mulaccsub3_0_mult_out_p_1_18, + P17=>mulaccsub3_0_mult_out_p_1_17, + P16=>mulaccsub3_0_mult_out_p_1_16, + P15=>mulaccsub3_0_mult_out_p_1_15, + P14=>mulaccsub3_0_mult_out_p_1_14, + P13=>mulaccsub3_0_mult_out_p_1_13, + P12=>mulaccsub3_0_mult_out_p_1_12, + P11=>mulaccsub3_0_mult_out_p_1_11, + P10=>mulaccsub3_0_mult_out_p_1_10, + P9=>mulaccsub3_0_mult_out_p_1_9, + P8=>mulaccsub3_0_mult_out_p_1_8, + P7=>mulaccsub3_0_mult_out_p_1_7, + P6=>mulaccsub3_0_mult_out_p_1_6, + P5=>mulaccsub3_0_mult_out_p_1_5, + P4=>mulaccsub3_0_mult_out_p_1_4, + P3=>mulaccsub3_0_mult_out_p_1_3, + P2=>mulaccsub3_0_mult_out_p_1_2, + P1=>mulaccsub3_0_mult_out_p_1_1, + P0=>mulaccsub3_0_mult_out_p_1_0, + SIGNEDP=>mulaccsub3_0_mult_out_signedp_1); + + ACCUM(44) <= mulaccsub3_alu_output_r_1_0_53; + ACCUM(43) <= mulaccsub3_alu_output_r_1_0_52; + ACCUM(42) <= mulaccsub3_alu_output_r_1_0_51; + ACCUM(41) <= mulaccsub3_alu_output_r_1_0_50; + ACCUM(40) <= mulaccsub3_alu_output_r_1_0_49; + ACCUM(39) <= mulaccsub3_alu_output_r_1_0_48; + ACCUM(38) <= mulaccsub3_alu_output_r_1_0_47; + ACCUM(37) <= mulaccsub3_alu_output_r_1_0_46; + ACCUM(36) <= mulaccsub3_alu_output_r_1_0_45; + ACCUM(35) <= mulaccsub3_alu_output_r_1_0_44; + ACCUM(34) <= mulaccsub3_alu_output_r_1_0_43; + ACCUM(33) <= mulaccsub3_alu_output_r_1_0_42; + ACCUM(32) <= mulaccsub3_alu_output_r_1_0_41; + ACCUM(31) <= mulaccsub3_alu_output_r_1_0_40; + ACCUM(30) <= mulaccsub3_alu_output_r_1_0_39; + ACCUM(29) <= mulaccsub3_alu_output_r_1_0_38; + ACCUM(28) <= mulaccsub3_alu_output_r_1_0_37; + ACCUM(27) <= mulaccsub3_alu_output_r_1_0_36; + ACCUM(26) <= mulaccsub3_alu_output_r_1_0_35; + ACCUM(25) <= mulaccsub3_alu_output_r_1_0_34; + ACCUM(24) <= mulaccsub3_alu_output_r_1_0_33; + ACCUM(23) <= mulaccsub3_alu_output_r_1_0_32; + ACCUM(22) <= mulaccsub3_alu_output_r_1_0_31; + ACCUM(21) <= mulaccsub3_alu_output_r_1_0_30; + ACCUM(20) <= mulaccsub3_alu_output_r_1_0_29; + ACCUM(19) <= mulaccsub3_alu_output_r_1_0_28; + ACCUM(18) <= mulaccsub3_alu_output_r_1_0_27; + ACCUM(17) <= mulaccsub3_alu_output_r_1_0_26; + ACCUM(16) <= mulaccsub3_alu_output_r_1_0_25; + ACCUM(15) <= mulaccsub3_alu_output_r_1_0_24; + ACCUM(14) <= mulaccsub3_alu_output_r_1_0_23; + ACCUM(13) <= mulaccsub3_alu_output_r_1_0_22; + ACCUM(12) <= mulaccsub3_alu_output_r_1_0_21; + ACCUM(11) <= mulaccsub3_alu_output_r_1_0_20; + ACCUM(10) <= mulaccsub3_alu_output_r_1_0_19; + ACCUM(9) <= mulaccsub3_alu_output_r_1_0_18; + ACCUM(8) <= mulaccsub3_alu_output_r_1_0_17; + ACCUM(7) <= mulaccsub3_alu_output_r_1_0_16; + ACCUM(6) <= mulaccsub3_alu_output_r_1_0_15; + ACCUM(5) <= mulaccsub3_alu_output_r_1_0_14; + ACCUM(4) <= mulaccsub3_alu_output_r_1_0_13; + ACCUM(3) <= mulaccsub3_alu_output_r_1_0_12; + ACCUM(2) <= mulaccsub3_alu_output_r_1_0_11; + ACCUM(1) <= mulaccsub3_alu_output_r_1_0_10; + ACCUM(0) <= mulaccsub3_alu_output_r_1_0_9; +end Structure; diff --git a/adc/par.p2t b/adc/par.p2t index 4e8a89b..e168739 100644 --- a/adc/par.p2t +++ b/adc/par.p2t @@ -4,7 +4,7 @@ #-m nodelist.txt # Controlled by the compile.pl script. #-n 1 # Controlled by the compile.pl script. -s 10 --t 9 +-t 11 -c 2 -e 2 -i 10 diff --git a/adc/source/adc_addon.vhd b/adc/source/adc_addon.vhd new file mode 100644 index 0000000..390d9a9 --- /dev/null +++ b/adc/source/adc_addon.vhd @@ -0,0 +1,287 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.adc_package.all; + + +entity adc_addon is + generic ( + ACTIVE_CHANNELS : integer := 2 + ); + port( + CLK : in std_logic; -- 100 MHz + CLK_ADCRAW : in std_logic; -- 350 MHz + RESET : in std_logic; + + FCO_A : in std_logic; + DATA_A : in std_logic_vector(3 downto 0); + DCO_A : in std_logic; + + READOUT_RX : in READOUT_RX; + READOUT_TX : out readout_tx_array_t(0 to ACTIVE_CHANNELS-1); + + TRIGGER_OUT : out std_logic_vector(ACTIVE_CHANNELS-1 downto 0); + + BUS_RX : in CTRLBUS_RX; + BUS_TX : out CTRLBUS_TX + ); +end entity; + + +architecture arch of adc_addon is + + + + signal data_in_a : std_logic_vector(55 downto 0); + signal data_valid_a : std_logic; + signal debug_a : std_logic_vector(31 downto 0); + + signal basic_control_strobes : std_logic_vector(31 downto 0); + alias STROBE_reset_a : std_logic is basic_control_strobes(0); + alias STROBE_shift_align_a : std_logic is basic_control_strobes(1); + + signal basic_control : std_logic_vector(31 downto 0); + alias CONF_adc_stop : std_logic is basic_control(0); + alias CONF_baseline_always_on : std_logic is basic_control(1); + + type config_arr_t is array(0 to ACTIVE_CHANNELS-1) of cfg_t; + signal config : config_arr_t; + + type brv_arr_t is array (0 to ACTIVE_CHANNELS-1, 0 to 3) of unsigned(31 downto 0); + signal baseline_reset_value : brv_arr_t := (others => (others => (others => '0'))); + + type config_mem_t is array(0 to 1023) of std_logic_vector(31 downto 0); + signal config_mem : config_mem_t; + signal read_mem : std_logic; + signal config_mem_out : std_logic_vector(31 downto 0); + + type proc_reg_data_t is array(0 to ACTIVE_CHANNELS-1) of std_logic_vector(31 downto 0); + signal proc_reg_addr : std_logic_vector(3 downto 0); + signal proc_reg_data : proc_reg_data_t; + signal proc_reg_read : std_logic_vector(15 downto 0); + signal proc_reg_ready : std_logic_vector(ACTIVE_CHANNELS-1 downto 0); + signal proc_reg_device : integer range 0 to ACTIVE_CHANNELS-1; + + signal psa_data : std_logic_vector(8 downto 0); + signal psa_write : std_logic_vector(ACTIVE_CHANNELS-1 downto 0); + signal psa_addr : std_logic_vector(5 downto 0); + +begin + +------------------------------------------------------------------------------- +-- ADC Input +------------------------------------------------------------------------------- +THE_INPUT_A : entity work.adc_input + port map( + CLK => CLK, + RESET => RESET, + RESET_ADC => STROBE_reset_a, + + CLK_ADCRAW => CLK_ADCRAW, + ADC_DATA => FCO_A & DATA_A, + SHIFT_ALIGN_IN => STROBE_shift_align_a, + + DATA_OUT => data_in_a, + DATA_VALID_OUT => data_valid_a, + DEBUG_OUT => debug_a + ); + + +------------------------------------------------------------------------------- +-- ADC Data Processors +------------------------------------------------------------------------------- +gen_processors : for i in 0 to ACTIVE_CHANNELS-1 generate + THE_ADC_PROC : entity work.adc_processor + generic map( + DEVICE => i + ) + port map( + CLK => CLK, + + ADC_DATA => data_in_a((i+1)*14-1 downto i*14), + ADC_VALID => data_valid_a, + + STOP_IN => CONF_adc_stop, + TRIGGER_OUT => TRIGGER_OUT(i), + + CONTROL => basic_control(15 downto 0), + CONFIG => config(i), + + PSA_DATA => psa_data, + PSA_ADDR => psa_addr, + PSA_WRITE => psa_write(i), + + PROC_REG_ADDR => proc_reg_addr, + PROC_REG_READ => proc_reg_read(i), + PROC_REG_DATA => proc_reg_data(i), + PROC_REG_READY => proc_reg_ready(i), + + READOUT_RX => READOUT_RX, + READOUT_TX => READOUT_TX(i) + + ); +end generate; + + + +------------------------------------------------------------------------------- +-- Control and Status Registers +------------------------------------------------------------------------------- + +-- reg 000 control strobes +-- reg 010-01f input ADC A registers +-- reg 020-02f input ADC B registers +-- reg 100-10f .. 190-19f * per channel configuration for each ADC channel +-- reg 200-20f .. 290-29f * per channel configuration for each ADC channel block mode +-- reg 400-40f .. 490-49f processor status registers +-- reg 800-83f .. a40-a7f PSA factor memory +-- * readback from RAM, not from register itself + +PROC_REGS : process + variable blocknum : integer range 0 to 3; + variable ch : integer range 0 to 15; + variable chpsa : integer range 0 to 15; +begin + wait until rising_edge(CLK); + basic_control_strobes <= (others => '0'); + read_mem <= '0'; + proc_reg_read <= (others => '0'); + psa_write <= (others => '0'); + config_mem_out <= config_mem(to_integer(unsigned(BUS_RX.addr(9 downto 0)))); + + BUS_TX.ack <= read_mem; + BUS_TX.data <= (others => '0'); + BUS_TX.unknown <= '0'; + BUS_TX.nack <= '0'; + + if read_mem = '1' then + BUS_TX.data <= config_mem_out; + end if; + + if or_all(proc_reg_ready) = '1' then + BUS_TX.data <= proc_reg_data(proc_reg_device); + BUS_TX.ack <= '1'; + end if; + + ch := to_integer(unsigned(BUS_RX.addr(7 downto 4))); + chpsa := to_integer(unsigned(BUS_RX.addr(9 downto 6))); + blocknum := to_integer(unsigned(BUS_RX.addr(1 downto 0))); + + if BUS_RX.write = '1' then + BUS_TX.ack <= '1'; + if BUS_RX.addr(11 downto 10) = "00" then + config_mem(to_integer(unsigned(BUS_RX.addr(9 downto 0)))) <= BUS_RX.data; + end if; + + if BUS_RX.addr(11 downto 8) = x"0" then + case BUS_RX.addr(7 downto 0) is + when x"00" => basic_control_strobes <= BUS_RX.data; + when x"01" => basic_control <= BUS_RX.data; + when others => BUS_TX.ack <= '0'; BUS_TX.unknown <= '1'; + end case; + elsif BUS_RX.addr(11 downto 8) = x"1" and ch < ACTIVE_CHANNELS then --100-19f basic configuration registers per channel + case BUS_RX.addr(3 downto 0) is + when x"0" => config(ch).buffer_depth <= unsigned(BUS_RX.data(10 downto 0)); + config(ch).samples_after <= unsigned(BUS_RX.data(26 downto 16)); + when x"1" => config(ch).block_count <= unsigned(BUS_RX.data( 1 downto 0)); + config(ch).presum <= unsigned(BUS_RX.data(10 downto 4)); + config(ch).averaging <= unsigned(BUS_RX.data(19 downto 16)); + when x"2" => config(ch).trigger_threshold <= signed (BUS_RX.data(19 downto 0)); + config(ch).trigger_abovebelow <= BUS_RX.data(24); + config(ch).trigger_enable <= BUS_RX.data(28); + when x"3" => config(ch).readout_threshold <= unsigned(BUS_RX.data(19 downto 0)); + config(ch).readout_abovebelow <= BUS_RX.data(24); + when x"4" => config(ch).baseline_fix_value <= unsigned(BUS_RX.data); + config(ch).baseline_subtract <= BUS_RX.data(29); + when x"5" => config(ch).channel_disable <= BUS_RX.data(0); + config(ch).processing_mode <= to_integer(unsigned(BUS_RX.data(5 downto 4))); + when x"6" => config(ch).check_word1 <= BUS_RX.data(17 downto 0); + config(ch).check_word_enable <= BUS_RX.data(31); + + when others => BUS_TX.ack <= '0'; BUS_TX.unknown <= '1'; + end case; + + elsif BUS_RX.addr(11 downto 8) = x"2" and ch < ACTIVE_CHANNELS then --200-29f block mode settings + case BUS_RX.addr(3 downto 2) is + when "00" => config(ch).block_avg(blocknum) <= unsigned(BUS_RX.data( 7 downto 0)); + config(ch).block_sums(blocknum) <= unsigned(BUS_RX.data(15 downto 8)); + config(ch).block_scale(blocknum) <= unsigned(BUS_RX.data(23 downto 16)); + when others => BUS_TX.ack <= '0'; BUS_TX.unknown <= '1'; + end case; + elsif BUS_RX.addr(11 downto 10) = "10" and chpsa < ACTIVE_CHANNELS then --8,9,a,b + psa_data <= BUS_RX.data(8 downto 0); + psa_write(chpsa) <= '1'; + psa_addr <= BUS_RX.addr(5 downto 0); + + else + BUS_TX.ack <= '0'; + BUS_TX.unknown <= '1'; + end if; + + + + + elsif BUS_RX.read = '1' then + BUS_TX.ack <= '1'; + if BUS_RX.addr(11 downto 8) = x"0" then --0 + case BUS_RX.addr(7 downto 0) is + when x"00" => BUS_TX.data <= (others => '0'); + when x"01" => BUS_TX.data <= basic_control; + when x"10" => BUS_TX.data(13 downto 0) <= data_in_a(13 downto 0); + when x"11" => BUS_TX.data(13 downto 0) <= data_in_a(27 downto 14); + when x"12" => BUS_TX.data(13 downto 0) <= data_in_a(41 downto 28); + when x"13" => BUS_TX.data(13 downto 0) <= data_in_a(55 downto 42); + when x"14" => BUS_TX.data <= debug_a; + when others => BUS_TX.ack <= '0'; BUS_TX.unknown <= '1'; + end case; + elsif BUS_RX.addr(11 downto 10) = "00" then --1,2,3 + read_mem <= '1'; + BUS_TX.ack <= '0'; + + elsif BUS_RX.addr(11 downto 8) = "0100" and ch < ACTIVE_CHANNELS then --4 + proc_reg_device <= ch; + proc_reg_addr <= BUS_RX.addr(3 downto 0); + proc_reg_read(ch) <= '1'; + BUS_TX.ack <= '0'; + + + else + BUS_TX.ack <= '0'; + BUS_TX.unknown <= '1'; + + end if; + end if; + +end process; + + +------------------------------------------------------------------------------- +-- Baselines settings +------------------------------------------------------------------------------- + +--TODO should be moved to processors & simplified +gen_copy_settings : for ch in 0 to ACTIVE_CHANNELS-1 generate + config(ch).baseline_always_on <= CONF_baseline_always_on; + + proc_baseline_reset_value : process begin + wait until rising_edge(CLK); + baseline_reset_value(ch, 3) <= (others => '0'); + baseline_reset_value(ch, 3)(to_integer(config(ch).averaging)+14-1 downto to_integer(config(ch).averaging)) <= (others => not config(ch).trigger_threshold(16)); + baseline_reset_value(ch, 2) <= baseline_reset_value(ch, 3); + baseline_reset_value(ch, 1) <= baseline_reset_value(ch, 2) (23 downto 0) * resize(config(ch).presum+1,8); + baseline_reset_value(ch, 0) <= baseline_reset_value(ch, 1); + + -- config(ch).baseline_subtract <= config(ch).baseline_fix_value(29); + + if config(ch).baseline_fix_value(30) = '0' then + config(ch).baseline_reset_value <= baseline_reset_value(ch,0); + else + config(ch).baseline_reset_value <= config(ch).baseline_fix_value(31) & '0' & config(ch).baseline_fix_value(29 downto 0); + end if; + end process; +end generate; + +end architecture; diff --git a/adc/source/adc_input.vhd b/adc/source/adc_input.vhd new file mode 100644 index 0000000..3e137ae --- /dev/null +++ b/adc/source/adc_input.vhd @@ -0,0 +1,172 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.adc_package.all; + + +entity adc_input is + port( + CLK : in std_logic; -- 100 MHz + RESET : in std_logic; + RESET_ADC : in std_logic; + + CLK_ADCRAW : in std_logic; --350 MHz + ADC_DATA : in std_logic_vector(4 downto 0); + SHIFT_ALIGN_IN : in std_logic; + + DATA_OUT : out std_logic_vector(4*14-1 downto 0); + DATA_VALID_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(31 downto 0) + ); +end entity; + + + +architecture arch of adc_input is + +signal clk_data : std_logic; -- 175 MHz +signal reset_adc_q : std_logic; + +type data_in_arr_t is array(0 to 4) of std_logic_vector( 3 downto 0); +type data_word_arr_t is array(0 to 4) of std_logic_vector(13 downto 0); + +signal data_in : std_logic_vector(19 downto 0); +signal data_reg : data_in_arr_t; +signal data_regreg : data_in_arr_t; +signal data_store : data_word_arr_t; +signal data_word : data_word_arr_t; + +signal store_valid : std_logic; +signal state : std_logic_vector(3 downto 0); + +signal data_valid : std_logic; +signal cdt_fifo_empty : std_logic; +signal last_cdt_fifo_empty, lastlast_cdt_fifo_empty : std_logic; + + +begin + + +THE_RESET_SYNC : entity work.pulse_sync port map(RESET_A_IN => '0',CLK_A_IN => CLK, PULSE_A_IN => RESET_ADC, + RESET_B_IN => '0',CLK_B_IN => clk_data, PULSE_B_OUT => reset_adc_q); + + +THE_INPUT : entity work.input_4ch + port map ( + alignwd => SHIFT_ALIGN_IN, + clkin => CLK_ADCRAW, + sclk => clk_data, + datain => ADC_DATA, + q => data_in + ); + + +data_reg(4) <= data_in(19 downto 16) when rising_edge(clk_data); +data_reg(3) <= data_in(15 downto 12) when rising_edge(clk_data); +data_reg(2) <= data_in(11 downto 8 ) when rising_edge(clk_data); +data_reg(1) <= data_in( 7 downto 4 ) when rising_edge(clk_data); +data_reg(0) <= data_in( 3 downto 0 ) when rising_edge(clk_data); + + +PROC_DATA_SORTER : process begin + wait until rising_edge(clk_data); + + store_valid <= '0'; + data_regreg <= data_reg; + + case state is + when x"0" => + --do init stuff + state <= x"1"; + when x"1" => + if data_reg(4) = "0011" then + state <= x"2"; + end if; + when x"2" => + data_store(0)(13 downto 12) <= data_regreg(0)(1 downto 0); + data_store(1)(13 downto 12) <= data_regreg(1)(1 downto 0); + data_store(2)(13 downto 12) <= data_regreg(2)(1 downto 0); + data_store(3)(13 downto 12) <= data_regreg(3)(1 downto 0); + + data_store(0)(11 downto 8) <= data_reg(0); + data_store(1)(11 downto 8) <= data_reg(1); + data_store(2)(11 downto 8) <= data_reg(2); + data_store(3)(11 downto 8) <= data_reg(3); + state <= x"3"; + when x"3" => + data_store(0)( 7 downto 4) <= data_reg(0); + data_store(1)( 7 downto 4) <= data_reg(1); + data_store(2)( 7 downto 4) <= data_reg(2); + data_store(3)( 7 downto 4) <= data_reg(3); + state <= x"4"; + when x"4" => + data_store(0)( 3 downto 0) <= data_reg(0); + data_store(1)( 3 downto 0) <= data_reg(1); + data_store(2)( 3 downto 0) <= data_reg(2); + data_store(3)( 3 downto 0) <= data_reg(3); + state <= x"5"; + store_valid <= '1'; + when x"5" => + data_store(0)(13 downto 10) <= data_reg(0); + data_store(1)(13 downto 10) <= data_reg(1); + data_store(2)(13 downto 10) <= data_reg(2); + data_store(3)(13 downto 10) <= data_reg(3); + state <= x"6"; + when x"6" => + data_store(0)( 9 downto 6) <= data_reg(0); + data_store(1)( 9 downto 6) <= data_reg(1); + data_store(2)( 9 downto 6) <= data_reg(2); + data_store(3)( 9 downto 6) <= data_reg(3); + state <= x"7"; + when x"7" => + data_store(0)( 5 downto 2) <= data_reg(0); + data_store(1)( 5 downto 2) <= data_reg(1); + data_store(2)( 5 downto 2) <= data_reg(2); + data_store(3)( 5 downto 2) <= data_reg(3); + state <= x"8"; + when x"8" => + data_store(0)( 1 downto 0) <= data_reg(0)(3 downto 2); + data_store(1)( 1 downto 0) <= data_reg(1)(3 downto 2); + data_store(2)( 1 downto 0) <= data_reg(2)(3 downto 2); + data_store(3)( 1 downto 0) <= data_reg(3)(3 downto 2); + store_valid <= '1'; + state <= x"2"; + + end case; + + if reset_adc_q = '1' THEN + state <= x"0"; + end if; +end process; + + +THE_CDT : entity work.fifo_cdt_70x16 + port map ( + Data(55 downto 0) => data_store(3) & data_store(2) & data_store(1) & data_store(0), + WrClock => clk_data, + RdClock => clk, + WrEn => store_valid, + RdEn => '1', + Reset => reset_adc_q, + RPReset => RESET, + Q(55 downto 0) => DATA_OUT, + Empty => cdt_fifo_empty + ); + +last_cdt_fifo_empty <= cdt_fifo_empty when rising_edge(CLK); +lastlast_cdt_fifo_empty <= last_cdt_fifo_empty when rising_edge(CLK); + +DATA_VALID_OUT <= not lastlast_cdt_fifo_empty and not RESET; + + + +DEBUG_OUT(3 downto 0) <= state; +DEBUG_OUT(23 downto 4) <= data_reg(4) & data_reg(3) & data_reg(2) & data_reg(1) & data_reg(0); +DEBUG_OUT(24) <= cdt_fifo_empty; +DEBUG_OUT(25) <= store_valid; + + +end architecture; diff --git a/adc/source/adc_package.vhd b/adc/source/adc_package.vhd new file mode 100644 index 0000000..6dc8c77 --- /dev/null +++ b/adc/source/adc_package.vhd @@ -0,0 +1,45 @@ +library ieee; +USE IEEE.std_logic_1164.ALL; +use ieee.numeric_std.all; +use work.trb_net_std.all; + +package adc_package is + +type unsigned_array_8 is array (integer range <>) of unsigned( 7 downto 0); + + +type cfg_t is record + buffer_depth : unsigned(10 downto 0); + samples_after : unsigned(10 downto 0); + block_count : unsigned( 1 downto 0); + trigger_threshold : signed (19 downto 0); + trigger_abovebelow : std_logic; + readout_threshold : signed (19 downto 0); + readout_abovebelow : std_logic; + presum : unsigned( 6 downto 0); + averaging : unsigned( 3 downto 0); + baseline_always_on : std_logic; + baseline_reset_value : unsigned(31 downto 0); + baseline_fix_value : unsigned(31 downto 0); + baseline_subtract : std_logic; + block_avg : unsigned_array_8(0 to 3); + block_sums : unsigned_array_8(0 to 3); + block_scale : unsigned_array_8(0 to 3); + + processing_mode : integer range 0 to 3; --0: normal block processing, 1: pulse shape processing + trigger_enable : std_logic; + channel_disable : std_logic; + check_word1 : std_logic_vector(17 downto 0); + check_word_enable : std_logic; + + +end record; + +end package; + + +package body adc_package is +end package body; + + + diff --git a/adc/source/adc_processor.vhd b/adc/source/adc_processor.vhd new file mode 100644 index 0000000..c51321e --- /dev/null +++ b/adc/source/adc_processor.vhd @@ -0,0 +1,706 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb3_components.all; +use work.adc_package.all; + +entity adc_processor is + generic( + DEVICE : integer range 0 to 15 := 15; + RESOLUTION : integer range 10 to 18 := 14 + ); + port( + CLK : in std_logic; + + ADC_DATA : in std_logic_vector(RESOLUTION-1 downto 0); + ADC_VALID : in std_logic; + STOP_IN : in std_logic; + TRIGGER_OUT: out std_logic; + + CONTROL : in std_logic_vector(15 downto 0); + CONFIG : in cfg_t; + + + PSA_DATA : in std_logic_vector(8 downto 0); + PSA_WRITE : in std_logic; + PSA_ADDR : in std_logic_vector(5 downto 0); + + PROC_REG_READ : in std_logic; + PROC_REG_ADDR : in std_logic_vector(3 downto 0); + PROC_REG_DATA : out std_logic_vector(31 downto 0); + PROC_REG_READY: out std_logic; + + READOUT_RX : in READOUT_RX; + READOUT_TX : out READOUT_TX + + ); +end entity; + + + + + +architecture arch of adc_processor is + +attribute syn_hier : string; +attribute syn_ramstyle : string; +attribute syn_keep : boolean; +attribute syn_preserve : boolean; +attribute syn_hier of arch : architecture is "hard"; + +type ram_t is array (0 to 1023) of unsigned(23 downto 0); +signal ram_write : std_logic := '0'; +signal ram_read : std_logic := '0'; +signal ram_data_in : unsigned(23 downto 0); +signal ram_data_out : unsigned(23 downto 0); +signal reg_ram_data_out : unsigned(23 downto 0); + +signal baseline : unsigned(19 downto 0); +signal baseline_averages : unsigned(31 downto 0); + + +signal ram_rd_move_value : unsigned( 9 downto 0) := (others => '0'); +signal ram_wr_pointer : unsigned( 9 downto 0) := (others => '0'); +signal ram_rd_pointer : unsigned( 9 downto 0) := (others => '0'); +signal ram_count : unsigned( 9 downto 0) := (others => '0'); +signal ram_reset : std_logic; +signal ram_clear : std_logic; +signal last_ramread : std_logic; +signal ram_valid : std_logic; +signal ram_rd_move : std_logic; +signal ram_remove : std_logic; +signal reg_ram_remove : std_logic; +signal reg2_ram_remove : std_logic; + + +signal trigger_gen : std_logic; +signal stop_writing : std_logic; +signal ram : ram_t := (others => (others => '0')); +attribute syn_ramstyle of ram : signal is "block_ram"; + + +signal after_trg_cnt : unsigned(11 downto 0) := (others => '1'); +signal stop_writing_rdo : std_logic := '0'; + +type state_t is (IDLE, DO_RELEASE, RELEASE_DIRECT, WAIT_FOR_END, CHECK_STATUS_TRIGGER, START, SEND_STATUS, READOUT, PSA_READOUT); +signal state : state_t; +signal statebits : std_logic_vector(7 downto 0); +signal rdostatebits : std_logic_vector(3 downto 0); + + + +signal reg_CONTROL : std_logic_vector(15 downto 0); +alias CONTROL_adc_stop : std_logic is reg_CONTROL(0); +alias CONTROL_baseline_always_on : std_logic is reg_CONTROL(1); +alias CONTROL_ram_clear : std_logic is reg_CONTROL(4); +alias CONTROL_ram_reset : std_logic is reg_CONTROL(5); +alias CONTROL_baseline_reset : std_logic is reg_CONTROL(8); +alias CONTROL_readout_reset : std_logic is reg_CONTROL(12); + +signal reg_CONFIG : cfg_t; + +signal invalid_word_count : unsigned(31 downto 0); + +signal thresh_counter : unsigned( 9 downto 0); +signal readout_flag : std_logic; +signal reset_threshold_counter : std_logic; + +type psa_ram_t is array (0 to 63) of std_logic_vector(8 downto 0); + +signal psa_write_i : std_logic; +signal psa_addr_i : std_logic_vector(5 downto 0); +signal psa_data_i : std_logic_vector(8 downto 0); +signal psa_ram_out_t : std_logic_vector(8 downto 0); +signal psa_ram_out : std_logic_vector(8 downto 0); +signal psa_ram : psa_ram_t; + +type psa_state_t is (PSA_IDLE, PSA_START_CHANNEL, PSA_WAIT_RAM, PSA_WAIT_RAM2, PSA_CALC, PSA_WAITWRITE, PSA_WAITWRITE2, PSA_DOWRITE, PSA_FINISH, PSA_WAIT_AFTER); +type rdo_state_t is (RDO_IDLE, READ_CHANNEL, NEXT_BLOCK, RDO_DONE, RDO_FINISH, RDO_WAIT_AFTER); + +signal psa_output : std_logic_vector(44 downto 0); +signal psa_clear : std_logic; +signal psa_enable : std_logic; +signal psa_pointer : integer range 0 to 64 := 0; +signal ram_read_psa : std_logic := '0'; +signal psa_state : psa_state_t := PSA_IDLE; +signal psa_adcdata : std_logic_vector(17 downto 0); +signal psa_current_baseline : std_logic_vector(17 downto 0); +signal word_counter : unsigned(7 downto 0); +signal readout_finished : std_logic; + + +signal RDO_data_psa : std_logic_vector(31 downto 0) := (others => '0'); +signal RDO_data_main : std_logic_vector(31 downto 0) := (others => '0'); +signal RDO_data_proc : std_logic_vector(31 downto 0) := (others => '0'); + +signal RDO_write_psa : std_logic := '0'; +signal RDO_write_main : std_logic := '0'; +signal RDO_write_proc : std_logic := '0'; + + +signal finished_readout : std_logic; +signal readout_psa_finished : std_logic; +signal prepare_header : std_logic; +signal prepare_header_valid : std_logic; +signal last_prepare_header : std_logic; +signal ram_read_rdo : std_logic; +signal blockcurrent : integer range 0 to 3 := 0; +signal last_blockcurrent : integer range 0 to 3 := 0; +signal readout_state : rdo_state_t; +signal myavg : unsigned(7 downto 0); + +signal current_baseline : unsigned(19 downto 0); + +begin + +reg_CONFIG <= CONFIG when rising_edge(CLK); +reg_CONTROL <= CONTROL when rising_edge(CLK); + + +------------------------------------------------------------------------------- +-- Status registers --TODO +------------------------------------------------------------------------------- + + + +------------------------------------------------------------------------------- +-- Check words +------------------------------------------------------------------------------- + THE_WORD_CHECK : process begin + wait until rising_edge(CLK); + if ADC_VALID = '1' then + if ADC_DATA(RESOLUTION-1 downto 0) /= reg_CONFIG.check_word1(RESOLUTION-1 downto 0) and + ADC_DATA(RESOLUTION-1 downto 0) /= not reg_CONFIG.check_word1(RESOLUTION-1 downto 0) and + reg_CONFIG.check_word_enable = '1' then + invalid_word_count <= invalid_word_count + 1; + end if; + end if; + end process; + + +------------------------------------------------------------------------------- +-- Preprocessing +------------------------------------------------------------------------------- + proc_preprocessor : process + variable cnt : integer range 0 to 127 := 0; + begin + wait until rising_edge(CLK); + ram_write <= '0'; + if ADC_VALID = '1' then + + if cnt = 0 then + ram_data_in(19 downto 0) <= resize(unsigned(ADC_DATA(RESOLUTION-1 downto 0)),20); + ram_data_in(23) <= trigger_gen; + else + ram_data_in(19 downto 0) <= ram_data_in(19 downto 0) + resize(unsigned(ADC_DATA(RESOLUTION-1 downto 0)),20); + ram_data_in(23) <= ram_data_in(23) or trigger_gen; + end if; + + if cnt = to_integer(reg_CONFIG.presum) then + cnt := 0; + ram_write <= not stop_writing; + elsif reg_CONFIG.presum /= 0 then + cnt := cnt + 1; + end if; + end if; + end process; + + +------------------------------------------------------------------------------- +-- Data buffers +------------------------------------------------------------------------------- + proc_buffer_enable : process begin + wait until rising_edge(CLK); + if READOUT_RX.valid_timing_trg = '1' then + after_trg_cnt(10 downto 0) <= reg_CONFIG.samples_after; + after_trg_cnt(11) <= '0'; + elsif state = IDLE then + stop_writing_rdo <= '0'; + after_trg_cnt <= (others => '1'); + elsif or_all(std_logic_vector(after_trg_cnt)) = '0' then + stop_writing_rdo <= '1'; + after_trg_cnt <= (others => '1'); + elsif after_trg_cnt(11) = '0' and ram_write = '1' then + after_trg_cnt <= after_trg_cnt - 1; + end if; + + stop_writing <= stop_writing_rdo or STOP_IN; + + end process; + + + + + PROC_RAM : process begin + wait until rising_edge(CLK); + if ram_write = '1' then + ram(to_integer(ram_wr_pointer)) <= ram_data_in; + end if; + ram_data_out <= ram(to_integer(ram_rd_pointer)); + reg_ram_data_out <= ram_data_out; + end process; + + proc_buffer_write : process begin + wait until rising_edge(CLK); + if ram_reset = '1' then + ram_wr_pointer <= (others => '0'); + elsif ram_write = '1' then + ram_wr_pointer <= ram_wr_pointer + 1; + end if; + end process; + + + proc_buffer_rotate : process begin + wait until rising_edge(CLK); + if ram_count >= reg_CONFIG.buffer_depth and ram_write = '1' then + ram_remove <= '1'; + else + ram_remove <= '0'; + end if; + reg_ram_remove <= ram_remove; + reg2_ram_remove <= reg_ram_remove; + end process; + + + proc_buffer_reader : process begin + wait until rising_edge(CLK); + + if (ram_read or ram_remove) = ram_write then + ram_count <= ram_wr_pointer - ram_rd_pointer; + elsif (ram_read or ram_remove) = '1' then + ram_count <= ram_wr_pointer - ram_rd_pointer -1; + elsif ram_write = '1' then + ram_count <= ram_wr_pointer - ram_rd_pointer +1; + end if; + + if ram_reset = '1' then + ram_rd_pointer <= (others => '1'); --one behind write pointer + elsif ram_clear = '1' then + ram_rd_pointer <= ram_wr_pointer; + elsif ram_read = '1' then + ram_rd_pointer <= ram_rd_pointer + 1; + elsif ram_remove = '1' then + ram_rd_pointer <= ram_rd_pointer + 1; + elsif ram_rd_move = '1' then + ram_rd_pointer <= ram_rd_pointer - ram_rd_move_value; + end if; + + end process; + + +------------------------------------------------------------------------------- +-- Baseline +------------------------------------------------------------------------------- + proc_baseline_calc : process begin + wait until rising_edge(CLK); + if CONTROL_baseline_reset = '1' or reg_CONFIG.baseline_reset_value(31) = '1' then + baseline_averages <= "00" & reg_CONFIG.baseline_reset_value(29 downto 0); + elsif reg2_ram_remove = '1' and (reg_ram_data_out(23) = '0' or reg_CONFIG.baseline_always_on = '1') then + baseline_averages <= baseline_averages + + resize(reg_ram_data_out(19 downto 0),32) + - resize(baseline_averages(to_integer(reg_CONFIG.averaging)+19 downto to_integer(reg_CONFIG.averaging)),32); + end if; + baseline <= baseline_averages(to_integer(reg_CONFIG.averaging)+19 downto to_integer(reg_CONFIG.averaging)); + end process; + + + +------------------------------------------------------------------------------- +-- Trigger Output +------------------------------------------------------------------------------- + + proc_trigger : process begin + wait until rising_edge(CLK); + if ram_write = '1' then + if (ram_data_in(19 downto 0) > unsigned(signed(baseline) + reg_CONFIG.trigger_threshold) and reg_CONFIG.trigger_abovebelow = '0') + or (ram_data_in(19 downto 0) < unsigned(signed(baseline) + reg_CONFIG.trigger_threshold) and reg_CONFIG.trigger_abovebelow = '1') then + trigger_gen <= '1'; + else + trigger_gen <= '0'; + end if; + end if; + end process; + +TRIGGER_OUT <= trigger_gen and reg_CONFIG.trigger_enable when rising_edge(CLK); + + +------------------------------------------------------------------------------- +-- Readout Threshold +------------------------------------------------------------------------------- + + proc_readout_threshold : process begin + wait until rising_edge(CLK); + if thresh_counter > 0 and ram_write = '1' then + thresh_counter <= thresh_counter - 1; + end if; + + if thresh_counter > 0 then + readout_flag <= '1'; + else + readout_flag <= '0'; + end if; + + if (ram_data_in(19 downto 0) > unsigned(signed(baseline) + reg_CONFIG.readout_threshold) and reg_CONFIG.readout_abovebelow = '0') + or (ram_data_in(19 downto 0) < unsigned(signed(baseline) + reg_CONFIG.readout_threshold) and reg_CONFIG.readout_abovebelow = '1') then + reset_threshold_counter <= '1'; + else + reset_threshold_counter <= '0'; + end if; + + if reset_threshold_counter = '1' then + thresh_counter <= reg_CONFIG.buffer_depth(9 downto 0); + end if; + end process; + + +------------------------------------------------------------------------------- +-- Memory for PSA coefficients +------------------------------------------------------------------------------- + psa_write_i <= PSA_WRITE when rising_edge(CLK); + psa_addr_i <= PSA_ADDR when rising_edge(CLK); + psa_data_i <= PSA_DATA when rising_edge(CLK); + psa_ram_out <= psa_ram_out_t when rising_edge(CLK); + + THE_PSA_MEMORY: process begin + wait until rising_edge(CLK); + if psa_write_i = '1' then + psa_ram(to_integer(unsigned(psa_addr_i))) <= psa_data_i; + end if; + psa_ram_out_t <= psa_ram(psa_pointer); + end process; + + +------------------------------------------------------------------------------- +-- Multiply Accumulate for PSA +------------------------------------------------------------------------------- + +THE_MULACC : entity work.mulaccsub3 + port map( + CLK0 => CLK, + CE0 => psa_enable, + RST0 => psa_clear, + ACCUMSLOAD => '0', + A0 => psa_ram_out, + B0 => psa_adcdata, + A1 => psa_ram_out, + B1 => psa_current_baseline, + LD => (others => '0'), + OVERFLOW => open, + ACCUM => psa_output + ); + + + +------------------------------------------------------------------------------- +-- Readout State Machine +------------------------------------------------------------------------------- +proc_readout : process begin + wait until rising_edge(CLK); + READOUT_TX.busy_release <= '0'; + READOUT_TX.data_finished <= '0'; + RDO_data_main <= (others => '0'); + RDO_write_main <= '0'; + finished_readout <= '0'; + + case state is + when IDLE => + READOUT_TX.statusbits <= (others => '0'); + if READOUT_RX.valid_notiming_trg = '1' then + state <= CHECK_STATUS_TRIGGER; + elsif READOUT_RX.data_valid = '1' then --seems to have missed trigger... + READOUT_TX.statusbits <= (23 => '1', others => '0'); --event not found + state <= RELEASE_DIRECT; + elsif READOUT_RX.valid_timing_trg = '1' then + state <= START; + end if; + + when RELEASE_DIRECT => + state <= DO_RELEASE; + + when DO_RELEASE => + if READOUT_RX.data_valid = '1' then + finished_readout <= '1'; + READOUT_TX.busy_release <= '1'; + READOUT_TX.data_finished <= '1'; + state <= WAIT_FOR_END; + end if; + + when WAIT_FOR_END => + if READOUT_RX.data_valid = '0' then + state <= IDLE; + end if; + + when CHECK_STATUS_TRIGGER => + if READOUT_RX.data_valid = '1' then + if READOUT_RX.trg_type = x"E" then + state <= SEND_STATUS; + word_counter <= (others => '0'); + else + state <= RELEASE_DIRECT; + end if; + end if; + + when START => + if stop_writing_rdo = '1' and reg_CONFIG.processing_mode = 0 then + state <= READOUT; + elsif stop_writing_rdo = '1' and reg_CONFIG.processing_mode = 1 then + state <= PSA_READOUT; + end if; + + when READOUT => + if readout_finished = '1' then + state <= RELEASE_DIRECT; + end if; + + when PSA_READOUT => + if readout_psa_finished = '1' then + state <= RELEASE_DIRECT; + end if; + + when SEND_STATUS => + RDO_write_main <= '1'; + RDO_data_main <= x"2" & std_logic_vector(word_counter) & x"00000"; + word_counter <= word_counter + 1; + state <= RELEASE_DIRECT; + + end case; + + if CONTROL_readout_reset = '1' then + state <= IDLE; + end if; +end process; + + +------------------------------------------------------------------------------- +-- Data Reading State Machine +------------------------------------------------------------------------------- + +PROC_RDO_FSM : process + variable readcount : integer range 0 to 255 := 0; +begin + wait until rising_edge(CLK); + readout_finished <= '0'; + ram_read_rdo <= '0'; + prepare_header <= '0'; + + case readout_state is + when RDO_IDLE => + if state = READOUT then + blockcurrent <= 0; + readcount := to_integer(reg_CONFIG.block_sums(0) * reg_CONFIG.block_avg(0)); + readout_state <= READ_CHANNEL; + prepare_header <= '1'; + end if; + + when READ_CHANNEL => + ram_read_rdo <= '1'; + if readcount = 1 or ram_count = 1 then + if blockcurrent < to_integer(reg_CONFIG.block_count)-1 then + readout_state <= NEXT_BLOCK; + else + readout_state <= RDO_DONE; + end if; + else + readcount := readcount - 1; + end if; + + when NEXT_BLOCK => + blockcurrent <= blockcurrent + 1; + readcount := to_integer(reg_CONFIG.block_sums(blockcurrent + 1) * reg_CONFIG.block_avg(blockcurrent + 1)); + readout_state <= READ_CHANNEL; + + + when RDO_DONE => + readout_state <= RDO_FINISH; + + when RDO_FINISH => + readout_finished <= '1'; + readout_state <= RDO_WAIT_AFTER; + + when RDO_WAIT_AFTER => + readout_state <= RDO_IDLE; + + end case; +end process; + + +last_ramread <= ram_read when rising_edge(CLK); +ram_valid <= last_ramread when rising_edge(CLK); +last_prepare_header <= prepare_header when rising_edge(CLK); +prepare_header_valid <= last_prepare_header when rising_edge(CLK); +last_blockcurrent <= blockcurrent when rising_edge(CLK); +myavg <= reg_CONFIG.block_avg(last_blockcurrent) when rising_edge(CLK); + + +PROC_DATA_PROCESSOR: process + variable cnt : integer range 0 to 255 := 0; +begin + wait until rising_edge(CLK); + RDO_write_proc <= '0'; + + if prepare_header_valid = '1' or ram_valid = '0' then + cnt := 0; + end if; + + if reg_CONFIG.baseline_subtract = '1' then + current_baseline <= baseline; + else + current_baseline <= (others => '0'); + end if; + + if ram_valid = '1' and readout_state /= RDO_IDLE then + if cnt = 0 then + RDO_data_proc(19 downto 0) <= std_logic_vector(reg_ram_data_out(19 downto 0) - current_baseline); + RDO_data_proc(23 downto 20) <= std_logic_vector(to_unsigned(DEVICE,4)); + RDO_data_proc(31 downto 24) <= (others => '0'); + else + RDO_data_proc(19 downto 0) <= std_logic_vector(unsigned(RDO_data_proc(19 downto 0)) + reg_ram_data_out(19 downto 0) - current_baseline ); + end if; + if cnt = to_integer(myavg-1) then + cnt := 0; + RDO_write_proc <= not reg_CONFIG.channel_disable; + elsif myavg /= 0 then + cnt := cnt + 1; + end if; + end if; + + if readout_state = RDO_IDLE then + RDO_data_proc <= (others => '0'); + RDO_write_proc <= '0'; + end if; + +end process; + + +------------------------------------------------------------------------------- +-- PSA State Machine +------------------------------------------------------------------------------- + +PROC_PULSE_SHAPE_READOUT : process + variable wordcount : integer range 0 to 256 := 0; + variable readcount : integer range 0 to 255 := 0; + variable time_cnt : integer range 0 to 5 := 0; +begin + wait until rising_edge(CLK); + ram_read_psa <= '0'; + ram_rd_move <= '0'; + readout_psa_finished <= '0'; + psa_adcdata <= std_logic_vector(reg_ram_data_out(17 downto 0)); + psa_clear <= '0'; + psa_enable <= '1'; + RDO_write_psa <= '0'; + RDO_data_psa <= (others => '0'); + + if reg_CONFIG.baseline_subtract = '1' then + psa_current_baseline <= baseline(17 downto 0); + else + psa_current_baseline <= (others => '0'); + end if; + + case psa_state is + when PSA_IDLE => + readcount := to_integer(reg_CONFIG.block_avg(0)); + wordcount := to_integer(reg_CONFIG.block_sums(0)); + psa_pointer <= 64; + psa_clear <= '1'; + if state = PSA_READOUT then + psa_state <= PSA_START_CHANNEL; + end if; + when PSA_START_CHANNEL => + ram_read_psa <= '1'; + readcount := readcount - 1; + psa_clear <= '1'; + psa_state <= PSA_WAIT_RAM; + when PSA_WAIT_RAM => + ram_read_psa <= '1'; + readcount := readcount - 1; + psa_clear <= '1'; + psa_state <= PSA_WAIT_RAM2; + when PSA_WAIT_RAM2 => + ram_read_psa <= '1'; + psa_pointer <= 0; + psa_clear <= '1'; + psa_state <= PSA_CALC; + when PSA_CALC => + if readcount = 1 then + psa_pointer <= psa_pointer + 1; + psa_state <= PSA_WAITWRITE; + else + ram_read_psa <= '1'; + psa_pointer <= psa_pointer + 1; + readcount := readcount - 1; + end if; + when PSA_WAITWRITE => + time_cnt := 4; + psa_pointer <= psa_pointer + 1; + psa_state <= PSA_WAITWRITE2; + + when PSA_WAITWRITE2 => + psa_pointer <= 64; + time_cnt := time_cnt -1; + if time_cnt = 0 then + psa_state <= PSA_DOWRITE; + end if; + when PSA_DOWRITE => + RDO_write_psa <= '1'; + RDO_data_psa(19 downto 0) <= psa_output(to_integer(reg_CONFIG.block_scale(0))+19 downto to_integer(reg_CONFIG.block_scale(0))); + RDO_data_psa(23 downto 20) <= std_logic_vector(to_unsigned(DEVICE,4)); + RDO_data_psa(27 downto 24) <= x"0"; + RDO_data_psa(31 downto 28) <= x"3"; + if wordcount > 1 then + wordcount := wordcount - 1; + readcount := to_integer(reg_CONFIG.block_avg(0)); + psa_state <= PSA_START_CHANNEL; + ram_rd_move <= '1'; + ram_rd_move_value <= ("00" & reg_CONFIG.block_avg(0)) - 1; + else + psa_state <= PSA_FINISH; + end if; + + when PSA_FINISH => + readout_psa_finished <= '1'; + psa_state <= PSA_WAIT_AFTER; + + when PSA_WAIT_AFTER => + psa_state <= PSA_IDLE; + + + end case; +end process; + + +------------------------------------------------------------------------------- +-- Data Output +------------------------------------------------------------------------------- + +ram_read <= ram_read_rdo or ram_read_psa; +READOUT_TX.data_write <= RDO_write_main or RDO_write_proc or RDO_write_psa when rising_edge(CLK); +READOUT_TX.data <= RDO_data_main or RDO_data_proc or RDO_data_psa when rising_edge(CLK); + + + +------------------------------------------------------------------------------- +-- Status Information +------------------------------------------------------------------------------- +statebits <= x"00" when state = IDLE else + x"01" when state = RELEASE_DIRECT else + x"02" when state = WAIT_FOR_END else + x"03" when state = CHECK_STATUS_TRIGGER else + x"04" when state = START else + x"05" when state = READOUT else + x"06" when state = DO_RELEASE else + x"07" when state = SEND_STATUS else + x"FF"; + +rdostatebits <= x"0" when readout_state = RDO_IDLE else + x"1" when readout_state = READ_CHANNEL else + x"2" when readout_state = NEXT_BLOCK else + x"4" when readout_state = RDO_DONE else + x"5" when readout_state = RDO_WAIT_AFTER else + x"F"; + + +end architecture; diff --git a/adc/trb5sc_adc.lpf b/adc/trb5sc_adc.lpf index b2047a0..41e91a5 100644 --- a/adc/trb5sc_adc.lpf +++ b/adc/trb5sc_adc.lpf @@ -14,6 +14,8 @@ FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs1.THE_SERDES/serdes_sync_0_inst/clk_tx FREQUENCY NET "med2int_0.clk_full" 200 MHz; # FREQUENCY NET THE_MEDIA_INTERFACE/clk_rx_full 200 MHz; +FREQUENCY NET "THE_ADDON/THE_INPUT_A/clk_data" 175.000000 MHz ; +FREQUENCY NET "CLK_A_c" 350.000000 MHz ; BLOCK PATH TO PORT "LED*"; BLOCK PATH TO PORT "PROGRAMN"; @@ -38,3 +40,8 @@ REGION "MEDIA" "R81C44D" 13 25; LOCATE UGROUP "THE_MEDIA_INTERFACE/media_interface_group" REGION "MEDIA" ; +BLOCK PATH FROM CELL "THE_ADDON/basic_control_strobe*"; +BLOCK PATH FROM CELL "THE_ADDON/config*"; +BLOCK PATH FROM CLKNET "clk_sys" TO CLKNET "THE_ADDON/THE_INPUT_A/clk_data"; +BLOCK PATH FROM CLKNET "THE_ADDON/THE_INPUT_A/clk_data" TO CLKNET "clk_sys"; + diff --git a/adc/trb5sc_adc.prj b/adc/trb5sc_adc.prj index f1510b0..40df45b 100644 --- a/adc/trb5sc_adc.prj +++ b/adc/trb5sc_adc.prj @@ -131,6 +131,8 @@ add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_rx_reset_RS.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_tx_reset_RS.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd" @@ -140,15 +142,12 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync.vhd" ######################################### #channel 0, backplane -#add_file -vhdl -lib work "../../dirich/cores/serdes_sync_0.vhd" -#add_file -verilog -lib work "../../dirich/cores/serdes_sync_0_softlogic.v" +#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_0/serdes_sync_0.vhd" #channel 1, SFP -#add_file -vhdl -lib work "../cores/serdes_sync_0/serdes_sync_0.vhd" -#add_file -verilog -lib work "../cores/serdes_sync_0/serdes_sync_0_softlogic.v" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_1/serdes_sync_0.vhd" ########################################## -add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_1/serdes_sync_0.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs2.vhd" add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0_softlogic.v" @@ -263,9 +262,14 @@ add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_2kx9x18_wcnt.vh add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_4kx18x9_wcnt.vhd" - - - +add_file -vhdl -lib work "./source/adc_package.vhd" +add_file -vhdl -lib work "./cores/fifo_cdt_70x16/fifo_cdt_70x16.vhd" +add_file -vhdl -lib work "./cores/mulaccsub3/mulaccsub3.vhd" +add_file -vhdl -lib work "./cores/adc_pll/adc_pll.vhd" +add_file -vhdl -lib work "./cores/input_4ch/input_4ch_edited.vhd" +add_file -vhdl -lib work "./source/adc_input.vhd" +add_file -vhdl -lib work "./source/adc_processor.vhd" +add_file -vhdl -lib work "./source/adc_addon.vhd" diff --git a/adc/trb5sc_adc.vhd b/adc/trb5sc_adc.vhd index 8bdd6af..abb2bad 100644 --- a/adc/trb5sc_adc.vhd +++ b/adc/trb5sc_adc.vhd @@ -28,30 +28,31 @@ entity trb5sc_adc is SFP_MOD_0 : in std_logic; --AddOn - -- FE_GPIO : inout std_logic_vector(11 downto 0); - -- FE_CLK : out std_logic_vector( 2 downto 1); - -- FE_DIFF : inout std_logic_vector(63 downto 0); - -- INP : inout std_logic_vector(63 downto 0); - -- LED_ADDON : out std_logic_vector(5 downto 0); - LED_ADDON_SFP_ORANGE : out std_logic_vector(1 downto 0); - LED_ADDON_SFP_GREEN : out std_logic_vector(1 downto 0); - LED_ADDON_RJ : out std_logic_vector(1 downto 0); - SFP_ADDON_TX_DIS : out std_logic_vector(1 downto 0); - SFP_ADDON_LOS : in std_logic_vector(1 downto 0); - - RJ : inout std_logic_vector(3 downto 0); - H1 : inout std_logic_vector(4 downto 0); - H2 : inout std_logic_vector(4 downto 0); - H3 : inout std_logic_vector(4 downto 0); - H4 : inout std_logic_vector(4 downto 0); - H5 : inout std_logic_vector(3 downto 0); - H6 : inout std_logic_vector(4 downto 0); - H7 : inout std_logic_vector(4 downto 0); - - PIN : out std_logic_vector(8 downto 1); - - MIMOSIS_SCL, MIMOSIS_SDA : inout std_logic; - + GPIO : inout std_logic_vector(5 downto 0); + + ADDON_LED : out std_logic_vector(7 downto 1); + ADDON_LED_RJ : out std_logic_vector(1 downto 0); + + SCLK_A : out std_logic; + CSB_A : out std_logic; + SDIO_A : inout std_logic; + FCO_A : in std_logic; + DATA_A : in std_logic_vector(3 downto 0); + DCO_A : in std_logic; + CLK_A : out std_logic; + + CLK_B : out std_logic; + TESTPAT_B : out std_logic; + DCO_B : in std_logic; + DATA_B : in std_logic; + + LEMO_OUT : out std_logic_vector(1 downto 0); + LEMO_OE : out std_logic_vector(1 downto 0); + LEMO_TTL : in std_logic_vector(1 downto 0); + LEMO_NIM : in std_logic_vector(1 downto 0); + ADDON_RJ : in std_logic_vector(3 downto 0); + + --ADC ADC_SCLK : out std_logic; ADC_NCS : out std_logic; @@ -82,7 +83,7 @@ entity trb5sc_adc is --Other Connectors TEST : inout std_logic_vector(14 downto 1); --on v1 only --COMMON_SDA, COMMON_SCL : inout std_logic - HDR_IO : inout std_logic_vector(15 downto 0) --23..16 on v2 only + HDR_IO : inout std_logic_vector(23 downto 0) --23..16 on v2 only ); attribute syn_useioff : boolean; @@ -95,6 +96,8 @@ end entity; architecture arch of trb5sc_adc is + constant ACTIVE_CHANNELS : integer := 2; + attribute syn_keep : boolean; attribute syn_preserve : boolean; @@ -119,7 +122,7 @@ architecture arch of trb5sc_adc is signal readout_rx : READOUT_RX; - signal readout_tx : readout_tx_array_t(0 to 0); + signal readout_tx : readout_tx_array_t(0 to ACTIVE_CHANNELS-1); signal ctrlbus_tx, bussci_tx, bustools_tx, bustc_tx, bus_master_in, busadc_tx, busi2c_tx : CTRLBUS_TX; signal ctrlbus_rx, bussci_rx, bustools_rx, bustc_rx, bus_master_out, busadc_rx, busi2c_rx : CTRLBUS_RX; @@ -138,12 +141,12 @@ architecture arch of trb5sc_adc is signal add_reg : std_logic_vector(31 downto 0); alias led_off : std_logic is add_reg(0); - signal out_data : std_logic_vector(15 downto 0); - signal out_i : std_logic_vector( 7 downto 0); - signal inp_i : std_logic_vector( 7 downto 0); signal gbe_status : std_logic_vector(15 downto 0); + signal adc_trigger_i : std_logic_vector(11 downto 0); + signal clk_350, clk_50, clk_200bypass : std_logic; + begin trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and not IN_SELECT_EXT_CLOCK); @@ -171,7 +174,16 @@ begin DEBUG_OUT => debug_clock_reset ); - + THE_ADC_PLL : entity work.adc_pll + port map( + CLKI => clk_full_osc, + CLKOP => clk_350, + CLKOS => clk_50, + CLKOS2 => open + ); + + CLK_A <= clk_50; + --------------------------------------------------------------------------- -- TrbNet Uplink @@ -179,8 +191,8 @@ begin THE_MEDIA_INTERFACE : entity work.med_ecp5_sfp_sync generic map( - SERDES_NUM => SERDES_NUM, - USE_NEW_ECP5_RESET => 0, + SERDES_NUM => 0, + USE_NEW_ECP5_RESET => 1, IS_SYNC_SLAVE => c_YES ) port map( @@ -234,7 +246,7 @@ begin REGIO_USE_1WIRE_INTERFACE => c_I2C, TIMING_TRIGGER_RAW => c_YES, --Configure data handler - DATA_INTERFACE_NUMBER => 1, + DATA_INTERFACE_NUMBER => ACTIVE_CHANNELS, DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE, DATA_BUFFER_WIDTH => 32, DATA_BUFFER_FULL_THRESH => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE, @@ -335,8 +347,8 @@ begin SPI_CLK_OUT => spi_clk, --Header --HEADER_IO => open, - HEADER_IO(7) => HDR_IO(6), - HEADER_IO(8) => HDR_IO(7), + -- HEADER_IO(7) => HDR_IO(6), + -- HEADER_IO(8) => HDR_IO(7), ADDITIONAL_REG => add_reg, --ADC ADC_CS => ADC_NCS, @@ -344,8 +356,11 @@ begin ADC_MISO => ADC_MISO, ADC_CLK => ADC_SCLK, --Trigger & Monitor - MONITOR_INPUTS => (others => '0'), - TRIG_GEN_INPUTS => (others => '0'), + MONITOR_INPUTS(11 downto 0) => adc_trigger_i, + MONITOR_INPUTS(15 downto 12) => x"0", + TRIG_GEN_INPUTS(11 downto 0) => adc_trigger_i, + TRIG_GEN_INPUTS(15 downto 12) => x"0", + TRIG_GEN_OUTPUTS(1 downto 0) => BACK_GPIO(3 downto 2), TRIG_GEN_OUTPUTS(3 downto 2) => SPARE(1 downto 0), --SED @@ -366,7 +381,38 @@ begin FLASH_WP <= '1'; + SCLK_A <= spi_clk(0); + CSB_A <= spi_cs(0); + SDIO_A <= spi_mosi(0); + spi_miso(0) <= SDIO_A when rising_edge(clk_sys); + +--------------------------------------------------------------------------- +-- ADC ADDON +--------------------------------------------------------------------------- + THE_ADDON : entity work.adc_addon + generic map( + ACTIVE_CHANNELS => ACTIVE_CHANNELS + ) + port map( + CLK => clk_sys, + CLK_ADCRAW => clk_350, + RESET => reset_i, + + FCO_A => FCO_A, + DATA_A => DATA_A, + DCO_A => DCO_A, + + TRIGGER_OUT => adc_trigger_i(ACTIVE_CHANNELS-1 downto 0), + READOUT_RX => readout_rx, + READOUT_TX => readout_tx, + + BUS_RX => busadc_rx, + BUS_TX => busadc_tx + + ); + + --------------------------------------------------------------------------- -- LED --------------------------------------------------------------------------- diff --git a/pinout/trb5sc_adc.lpf b/pinout/trb5sc_adc.lpf index d670366..800f5a1 100644 --- a/pinout/trb5sc_adc.lpf +++ b/pinout/trb5sc_adc.lpf @@ -59,49 +59,49 @@ IOBUF PORT "SFP_MOD_0" IO_TYPE=LVTTL33 PULLMODE=NONE ; ################################################################# # Frontend ################################################################# -LOCATE COMP "CS_1" SITE "A18"; #"FE_GPIO_0" -LOCATE COMP "CS_2" SITE "C18"; #"FE_GPIO_1" -LOCATE COMP "MISO_1" SITE "D18"; #"FE_GPIO_2" -LOCATE COMP "MISO_2" SITE "F18"; #"FE_GPIO_3" -LOCATE COMP "CS_3" SITE "A19"; #"FE_GPIO_4" -LOCATE COMP "CS_4" SITE "B19"; #"FE_GPIO_5" -LOCATE COMP "MISO_3" SITE "C19"; #"FE_GPIO_6" -LOCATE COMP "MISO_4" SITE "D19"; #"FE_GPIO_7" -DEFINE PORT GROUP "MISO_group" "MISO*" ; -IOBUF GROUP "MISO_group" IO_TYPE=LVTTL33; -DEFINE PORT GROUP "CS_group" "CS*" ; -IOBUF GROUP "CS_group" IO_TYPE=LVCMOS25; - - -LOCATE COMP "SFP_ADD_LOS" SITE "E19"; #"FE_GPIO_8" -LOCATE COMP "SFP_ADD_MOD0" SITE "F19"; #"FE_GPIO_9" -LOCATE COMP "SFP_ADD_TX_DIS" SITE "A20"; #"FE_GPIO_10" -LOCATE COMP "SFP_ADD_LED" SITE "C20"; #"FE_GPIO_11" -IOBUF PORT "SFP_ADD_LOS" IO_TYPE=LVTTL33 PULLMODE=NONE ; -IOBUF PORT "SFP_ADD_TX_DIS" IO_TYPE=LVCMOS25 ; -IOBUF PORT "SFP_ADD_MOD0" IO_TYPE=LVTTL33 PULLMODE=NONE ; -IOBUF PORT "SFP_ADD_LED" IO_TYPE=LVCMOS25 ; - -LOCATE COMP "FE_GPIO_0" SITE "A18"; -LOCATE COMP "FE_GPIO_1" SITE "C18"; -LOCATE COMP "FE_GPIO_2" SITE "D18"; -LOCATE COMP "FE_GPIO_3" SITE "F18"; -LOCATE COMP "FE_GPIO_4" SITE "A19"; -LOCATE COMP "FE_GPIO_5" SITE "B19"; -LOCATE COMP "FE_GPIO_6" SITE "C19"; -LOCATE COMP "FE_GPIO_7" SITE "D19"; -LOCATE COMP "FE_GPIO_8" SITE "E19"; -LOCATE COMP "FE_GPIO_9" SITE "F19"; -LOCATE COMP "FE_GPIO_10" SITE "A20"; -LOCATE COMP "FE_GPIO_11" SITE "C20"; -DEFINE PORT GROUP "FE_GPIO_group" "FE_GPIO*" ; -IOBUF GROUP "FE_GPIO_group" IO_TYPE=LVCMOS25 PULLMODE=UP; - - -LOCATE COMP "SCK" SITE "C5";#"FE_CLK_1" -LOCATE COMP "MOSI" SITE "P5";#"FE_CLK_2" -IOBUF PORT "SCK" IO_TYPE=LVDS ; -IOBUF PORT "MOSI" IO_TYPE=LVDS ; +# LOCATE COMP "CS_1" SITE "A18"; #"FE_GPIO_0" +# LOCATE COMP "CS_2" SITE "C18"; #"FE_GPIO_1" +# LOCATE COMP "MISO_1" SITE "D18"; #"FE_GPIO_2" +# LOCATE COMP "MISO_2" SITE "F18"; #"FE_GPIO_3" +# LOCATE COMP "CS_3" SITE "A19"; #"FE_GPIO_4" +# LOCATE COMP "CS_4" SITE "B19"; #"FE_GPIO_5" +# LOCATE COMP "MISO_3" SITE "C19"; #"FE_GPIO_6" +# LOCATE COMP "MISO_4" SITE "D19"; #"FE_GPIO_7" +# DEFINE PORT GROUP "MISO_group" "MISO*" ; +# IOBUF GROUP "MISO_group" IO_TYPE=LVTTL33; +# DEFINE PORT GROUP "CS_group" "CS*" ; +# IOBUF GROUP "CS_group" IO_TYPE=LVCMOS25; + +# +# LOCATE COMP "SFP_ADD_LOS" SITE "E19"; #"FE_GPIO_8" +# LOCATE COMP "SFP_ADD_MOD0" SITE "F19"; #"FE_GPIO_9" +# LOCATE COMP "SFP_ADD_TX_DIS" SITE "A20"; #"FE_GPIO_10" +# LOCATE COMP "SFP_ADD_LED" SITE "C20"; #"FE_GPIO_11" +# IOBUF PORT "SFP_ADD_LOS" IO_TYPE=LVTTL33 PULLMODE=NONE ; +# IOBUF PORT "SFP_ADD_TX_DIS" IO_TYPE=LVCMOS25 ; +# IOBUF PORT "SFP_ADD_MOD0" IO_TYPE=LVTTL33 PULLMODE=NONE ; +# IOBUF PORT "SFP_ADD_LED" IO_TYPE=LVCMOS25 ; + +# LOCATE COMP "FE_GPIO_0" SITE "A18"; +# LOCATE COMP "FE_GPIO_1" SITE "C18"; +# LOCATE COMP "FE_GPIO_2" SITE "D18"; +# LOCATE COMP "FE_GPIO_3" SITE "F18"; +# LOCATE COMP "FE_GPIO_4" SITE "A19"; +# LOCATE COMP "FE_GPIO_5" SITE "B19"; +# LOCATE COMP "FE_GPIO_6" SITE "C19"; +# LOCATE COMP "FE_GPIO_7" SITE "D19"; +# LOCATE COMP "FE_GPIO_8" SITE "E19"; +# LOCATE COMP "FE_GPIO_9" SITE "F19"; +# LOCATE COMP "FE_GPIO_10" SITE "A20"; +# LOCATE COMP "FE_GPIO_11" SITE "C20"; +# DEFINE PORT GROUP "FE_GPIO_group" "FE_GPIO*" ; +# IOBUF GROUP "FE_GPIO_group" IO_TYPE=LVCMOS25 PULLMODE=UP; + + +# LOCATE COMP "SCK" SITE "C5";#"FE_CLK_1" +# LOCATE COMP "MOSI" SITE "P5";#"FE_CLK_2" +# IOBUF PORT "SCK" IO_TYPE=LVDS ; +# IOBUF PORT "MOSI" IO_TYPE=LVDS ; # DEFINE PORT GROUP "FE_CLK_group" "FE_CLK*" ; # IOBUF GROUP "FE_CLK_group" IO_TYPE=LVDS DIFFRESISTOR=100; -- 2.43.0