From bb5bc23b20e60abdfc9d233bf44102c27b5fb264 Mon Sep 17 00:00:00 2001 From: Andreas Neiser Date: Mon, 2 Mar 2015 11:27:06 +0100 Subject: [PATCH] some more registers for slow control signals --- ADC/source/adc_ad9219.vhd | 6 ++++-- ADC/source/adc_handler.vhd | 7 ++++--- ADC/source/adc_processor_cfd.vhd | 7 ++++--- 3 files changed, 12 insertions(+), 8 deletions(-) diff --git a/ADC/source/adc_ad9219.vhd b/ADC/source/adc_ad9219.vhd index 488f7ea..bc251c5 100644 --- a/ADC/source/adc_ad9219.vhd +++ b/ADC/source/adc_ad9219.vhd @@ -42,6 +42,7 @@ architecture adc_ad9219_arch of adc_ad9219 is type states_t is array (0 to NUM_DEVICES - 1) of state_t; signal state : states_t; signal state_q : states_t; + signal state_qq: states_t; type value_it is array (0 to 4) of std_logic_vector(9 downto 0); type value_t is array (0 to NUM_DEVICES - 1) of value_it; @@ -249,6 +250,7 @@ begin proc_collect_data : process begin wait until rising_edge(clk_data); + state_q(i) <= state(i); qq(i) <= q(i); buffer_write(i) <= '0'; case state(i) is @@ -322,10 +324,10 @@ begin proc_debug : process begin wait until rising_edge(clk_rd); - state_q(i) <= state(i); + state_qq(i) <= state_q(i); counter_q(i) <= counter(i); DEBUG(i * 32 + 31 downto i * 32 + 4) <= std_logic_vector(counter_q(i)); - case state_q(i) is + case state_qq(i) is when S1 => DEBUG(i * 32 + 3 downto i * 32 + 0) <= x"1"; when S2 => DEBUG(i * 32 + 3 downto i * 32 + 0) <= x"2"; when S3 => DEBUG(i * 32 + 3 downto i * 32 + 0) <= x"3"; diff --git a/ADC/source/adc_handler.vhd b/ADC/source/adc_handler.vhd index 4abd211..01ca770 100644 --- a/ADC/source/adc_handler.vhd +++ b/ADC/source/adc_handler.vhd @@ -79,7 +79,7 @@ architecture adc_handler_arch of adc_handler is signal adc_clk : std_logic_vector(DEVICES downto 1) := (others => '1'); signal adc_clk_left, adc_clk_right : std_logic := '1'; - signal BUS_RX_adc : CTRLBUS_RX; + signal BUS_RX_adc, BUS_RX_sys : CTRLBUS_RX; signal BUS_TX_adc : CTRLBUS_TX; -- 000 - 0ff configuration @@ -395,7 +395,8 @@ begin config_cfd.BaselineAlwaysOn <= buffer_ctrl_reg(4); BUS_TX <= BUS_TX_adc when rising_edge(CLK); - BUS_RX_adc <= BUS_RX when rising_edge(adc_clk_left); + BUS_RX_sys <= BUS_RX when rising_edge(CLK); + BUS_RX_adc <= BUS_RX_sys when rising_edge(adc_clk_left); PROC_BUS : process begin @@ -411,7 +412,7 @@ begin elsif BUS_RX_adc.read = '1' then if BUS_RX_adc.addr <= x"000f" then BUS_TX_adc.ack <= '1'; - case BUS_RX.addr(3 downto 0) is + case BUS_RX_adc.addr(3 downto 0) is when x"1" => BUS_TX_adc.data <= buffer_ctrl_reg; when others => BUS_TX_adc.ack <= '0'; BUS_TX_adc.unknown <= '1'; diff --git a/ADC/source/adc_processor_cfd.vhd b/ADC/source/adc_processor_cfd.vhd index 6a9202e..ffa7c23 100644 --- a/ADC/source/adc_processor_cfd.vhd +++ b/ADC/source/adc_processor_cfd.vhd @@ -61,7 +61,7 @@ architecture arch of adc_processor_cfd is type state_t is (IDLE, DO_RELEASE, RELEASE_DIRECT, WAIT_FOR_END, CHECK_STATUS_TRIGGER, SEND_STATUS, READOUT, WAIT_BSY, WAIT_RAM, TRIG_DLY); signal state : state_t; - signal statebits : std_logic_vector(7 downto 0); + signal statebits, statebits_adc : std_logic_vector(7 downto 0); signal RDO_data_main : std_logic_vector(31 downto 0) := (others => '0'); signal RDO_write_main : std_logic := '0'; @@ -227,7 +227,8 @@ begin end if; end process; - statebits <= std_logic_vector(to_unsigned(state_t'pos(state), 8)) when rising_edge(CLK_ADC); + statebits <= std_logic_vector(to_unsigned(state_t'pos(state), 8)) when rising_edge(CLK_SYS); + statebits_adc <= statebits when rising_edge(CLK_ADC); PROC_DEBUG_BUFFER : process variable c : integer range 0 to 3; @@ -253,7 +254,7 @@ begin DEBUG_BUFFER_DATA(12) <= '1'; -- ADC_VALID DEBUG_BUFFER_DATA(19 downto 16) <= trigger_gen; when x"6" => - DEBUG_BUFFER_DATA(7 downto 0) <= statebits; + DEBUG_BUFFER_DATA(7 downto 0) <= statebits_adc; when others => null; end case; end if; -- 2.43.0