From bb696bf61a4c4777d9553691b25e7d20b5bf88d0 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Fri, 17 Nov 2017 15:36:12 +0100 Subject: [PATCH] Update CTS timestamp generator with records --- cts/source/timestamp_generator.vhd | 32 ++++++++++---------- cts/trb3_central.vhd | 47 ++++++++++++++---------------- 2 files changed, 37 insertions(+), 42 deletions(-) diff --git a/cts/source/timestamp_generator.vhd b/cts/source/timestamp_generator.vhd index 4383cde..2ddb43f 100644 --- a/cts/source/timestamp_generator.vhd +++ b/cts/source/timestamp_generator.vhd @@ -15,12 +15,9 @@ entity timestamp_generator is TIMER_RESET_IN : in std_logic; --data output for read-out - TRIGGER_IN : in std_logic; - TRIGGER_NUMBER_IN : in std_logic_vector(15 downto 0); - DATA_OUT : out std_logic_vector(31 downto 0); - WRITE_OUT : out std_logic; - FINISHED_OUT : out std_logic; - STATUSBIT_OUT : out std_logic_vector(31 downto 0) + TRIGGER_IN : in std_logic; + BUSRDO_RX : in READOUT_RX; + BUSRDO_TX : out READOUT_TX ); end entity; @@ -76,10 +73,10 @@ clock_tick <= not last_timer_clock_reg and timer_clock_reg when rising_edge(CLK PROC_RDO : process begin wait until rising_edge(CLK); - WRITE_OUT <= '0'; - FINISHED_OUT <= '0'; - STATUSBIT_OUT <= (others => '0'); - DATA_OUT <= x"00000000"; + BUSRDO_TX.data_write <= '0'; + BUSRDO_TX.data_finished <= '0'; + BUSRDO_TX.statusbits <= (others => '0'); + BUSRDO_TX.data <= x"00000000"; case rdostate is when RDO_IDLE => if TRIGGER_IN = '1' and last_TRIGGER_IN = '0' then @@ -87,18 +84,19 @@ clock_tick <= not last_timer_clock_reg and timer_clock_reg when rising_edge(CLK end if; when RDO_WRITE1 => rdostate <= RDO_WRITE2; - DATA_OUT <= x"75" & std_logic_vector(timestamp_counter(47 downto 24)); - WRITE_OUT <= '1'; + BUSRDO_TX.data <= x"75" & std_logic_vector(timestamp_counter(47 downto 24)); + BUSRDO_TX.data_write <= '1'; when RDO_WRITE2 => rdostate <= RDO_WRITE3; - DATA_OUT <= x"75" & std_logic_vector(timestamp_counter(23 downto 0)); - WRITE_OUT <= '1'; + BUSRDO_TX.data <= x"75" & std_logic_vector(timestamp_counter(23 downto 0)); + BUSRDO_TX.data_write <= '1'; when RDO_WRITE3 => rdostate <= RDO_FINISH; - DATA_OUT <= x"75" & std_logic_vector(finetime_counter); - WRITE_OUT <= '1'; + BUSRDO_TX.data <= x"75" & std_logic_vector(finetime_counter); + BUSRDO_TX.data_write <= '1'; when RDO_FINISH => - FINISHED_OUT <= '1'; + BUSRDO_TX.data_finished <= '1'; + BUSRDO_TX.busy_release <= '1'; rdostate <= RDO_IDLE; end case; if RESET_IN = '1' then diff --git a/cts/trb3_central.vhd b/cts/trb3_central.vhd index e0a20b7..d173742 100644 --- a/cts/trb3_central.vhd +++ b/cts/trb3_central.vhd @@ -710,18 +710,18 @@ begin generic map ( EXTERNAL_TRIGGER_ID => ETM_ID, -- fill in trigger logic enumeration id of external trigger logic - TRIGGER_COIN_COUNT => TRIGGER_COIN_COUNT, - TRIGGER_PULSER_COUNT => TRIGGER_PULSER_COUNT, - TRIGGER_RAND_PULSER => TRIGGER_RAND_PULSER, - - TRIGGER_INPUT_COUNT => 0, -- obsolete! now all inputs are routed via an input multiplexer! - TRIGGER_ADDON_COUNT => TRIGGER_ADDON_COUNT, - - PERIPH_TRIGGER_COUNT => PERIPH_TRIGGER_COUNT, +-- TRIGGER_COIN_COUNT => TRIGGER_COIN_COUNT, +-- TRIGGER_PULSER_COUNT => TRIGGER_PULSER_COUNT, +-- TRIGGER_RAND_PULSER => TRIGGER_RAND_PULSER, +-- +-- TRIGGER_INPUT_COUNT => 0, -- obsolete! now all inputs are routed via an input multiplexer! +-- TRIGGER_ADDON_COUNT => TRIGGER_ADDON_COUNT, +-- +-- PERIPH_TRIGGER_COUNT => PERIPH_TRIGGER_COUNT, OUTPUT_MULTIPLEXERS => CTS_OUTPUT_MULTIPLEXERS, - ADDON_LINE_COUNT => CTS_ADDON_LINE_COUNT, +-- ADDON_LINE_COUNT => CTS_ADDON_LINE_COUNT, ADDON_GROUPS => 7, ADDON_GROUP_UPPER => (3, 7, 11, 15, 16, 17, others => 0) ) @@ -998,14 +998,14 @@ end generate; --------------------------------------------------------------------------- -- Clock Handling --------------------------------------------------------------------------- - THE_MAIN_PLL : pll_in200_out100 - port map ( - CLK => CLK_GPLL_LEFT, - RESET => '0', - CLKOP => clk_100_i, - CLKOK => clk_200_i, - LOCK => pll_lock - ); +THE_MAIN_PLL : pll_in200_out100 + port map ( + CLK => CLK_GPLL_LEFT, + RESET => '0', + CLKOP => clk_100_i, + CLKOK => clk_200_i, + LOCK => pll_lock + ); clk_125_i <= CLK_GPLL_RIGHT; @@ -1615,7 +1615,7 @@ end generate; BUS_UNKNOWN_ADDR_IN(3) => busgbereg_tx.unknown, -- CTS - BUS_ADDR_OUT(5*16-1 downto 4*16) => cts_regio_addr, + BUS_ADDR_OUT(4*16+10 downto 4*16) => cts_regio_addr(10 downto 0), BUS_DATA_OUT(5*32-1 downto 4*32) => cts_regio_data_out, BUS_READ_ENABLE_OUT(4) => cts_regio_read, BUS_WRITE_ENABLE_OUT(4) => cts_regio_write, @@ -1729,6 +1729,7 @@ end generate; STAT_DEBUG => open ); +cts_regio_addr(15 downto 11) <= (others => '0'); --------------------------------------------------------------------------- -- SPI / Flash @@ -1971,13 +1972,9 @@ end generate; TIMER_CLOCK_IN => CLK_EXT(3), TIMER_RESET_IN => CLK_EXT(4), - - TRIGGER_IN => cts_rdo_trg_data_valid, - TRIGGER_NUMBER_IN => cts_rdo_trg_number, - DATA_OUT => cts_rdo_additional(INCLUDE_ETM).data, - WRITE_OUT => cts_rdo_additional(INCLUDE_ETM).data_write, - FINISHED_OUT => cts_rdo_additional(INCLUDE_ETM).data_finished, - STATUSBIT_OUT => cts_rdo_additional(INCLUDE_ETM).statusbits + + BUSRDO_RX => cts_rdo_rx, + BUSRDO_TX => cts_rdo_additional(INCLUDE_ETM) ); end generate; -- 2.43.0