From bb8e88c85810b83e33714b8ba54a77ede8081bfb Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Fri, 9 Aug 2024 14:20:13 +0200 Subject: [PATCH] copy of the mimosis project as standalone version --- mimosis_standalone/compile.pl | 1 + mimosis_standalone/config.vhd | 171 ++++ .../config_compile_frankfurt.pl | 25 + mimosis_standalone/par.p2t | 69 ++ mimosis_standalone/trb5sc_mimosis.lpf | 53 ++ mimosis_standalone/trb5sc_mimosis.prj | 302 ++++++ mimosis_standalone/trb5sc_mimosis.vhd | 875 ++++++++++++++++++ 7 files changed, 1496 insertions(+) create mode 120000 mimosis_standalone/compile.pl create mode 100644 mimosis_standalone/config.vhd create mode 100644 mimosis_standalone/config_compile_frankfurt.pl create mode 100644 mimosis_standalone/par.p2t create mode 100644 mimosis_standalone/trb5sc_mimosis.lpf create mode 100644 mimosis_standalone/trb5sc_mimosis.prj create mode 100644 mimosis_standalone/trb5sc_mimosis.vhd diff --git a/mimosis_standalone/compile.pl b/mimosis_standalone/compile.pl new file mode 120000 index 0000000..8a19aa6 --- /dev/null +++ b/mimosis_standalone/compile.pl @@ -0,0 +1 @@ +../../trb3sc/scripts/compile.pl \ No newline at end of file diff --git a/mimosis_standalone/config.vhd b/mimosis_standalone/config.vhd new file mode 100644 index 0000000..ea83682 --- /dev/null +++ b/mimosis_standalone/config.vhd @@ -0,0 +1,171 @@ +library ieee; +USE IEEE.std_logic_1164.ALL; +use ieee.numeric_std.all; +use work.trb_net_std.all; +use work.trb_net16_hub_func.all; + +package config is + + +------------------------------------------------------------------------------ +--Begin of design configuration +------------------------------------------------------------------------------ + + +--set to 0 for backplane serdes, set to 1 for SFP serdes + constant SERDES_NUM : integer := 1; + +--TDC settings + constant FPGA_TYPE : integer := 5; --3: ECP3, 5: ECP5 + constant FPGA_SIZE : string := "85KUM"; +-- constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement +-- constant NUM_TDC_CHANNELS : integer range 1 to 65 := 33; -- number of tdc channels per module +-- constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons +-- constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3 +-- -- 0: single edge only, +-- -- 1: same channel, +-- -- 2: alternating channels, +-- -- 3: same channel with stretcher +-- constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size +-- -- mode: 0, 1, 2, 3, 7 +-- -- size: 32, 64, 96, 128, dyn +-- constant TDC_DATA_FORMAT : integer range 0 to 3 := 0; --type of data format for the TDC +-- -- 0: Single fine time as the sum of the two transitions +-- -- 1: Double fine time, individual transitions +-- -- 13: Debug - fine time + (if 0x3ff full chain) +-- -- 14: Debug - single fine time and the ROM addresses for the two transitions +-- -- 15: Debug - complete carry chain dump + + constant EVENT_BUFFER_SIZE : integer range 9 to 15 := 10; -- size of the event buffer, 2**N + constant EVENT_MAX_SIZE : integer := 500; --maximum event size. Must not exceed EVENT_BUFFER_SIZE/2 + constant USE_GBE : integer := c_YES; + +--Runs with 120 MHz instead of 100 MHz + constant USE_120_MHZ : integer := c_NO; + +--Use sync mode, RX clock for all parts of the FPGA + constant USE_RXCLOCK : integer := c_NO; + +--Address settings + constant INIT_ADDRESS : std_logic_vector := x"F586"; + constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"86"; + + constant INCLUDE_UART : integer := c_NO; + constant INCLUDE_SPI : integer := c_YES; + constant INCLUDE_ADC : integer := c_YES; + constant INCLUDE_I2C : integer := c_NO; + constant INCLUDE_DEBUG_INTERFACE: integer := c_NO; + + --input monitor and trigger generation logic + constant INCLUDE_TRIGGER_LOGIC : integer := c_NO; + constant INCLUDE_STATISTICS : integer := c_NO; + constant TRIG_GEN_INPUT_NUM : integer := 16; + constant TRIG_GEN_OUTPUT_NUM : integer := 4; + constant MONITOR_INPUT_NUM : integer := 16; + + + + constant GEN_BUSY_OUTPUT : integer := c_NO; + + constant TRIGGER_COIN_COUNT : integer := 0; + constant TRIGGER_PULSER_COUNT : integer := 2; + constant TRIGGER_RAND_PULSER : integer := 0; + constant TRIGGER_ADDON_COUNT : integer := 1; + constant PERIPH_TRIGGER_COUNT : integer := 0; + constant ADDON_LINE_COUNT : integer := 1; --36 with Padiwa, 22 with RJ-adapter + constant CTS_OUTPUT_MULTIPLEXERS : integer := 0; +--TODO: +-- constant INCLUDE_MBS_MASTER : integer range c_NO to c_YES := c_NO; +--Which external trigger module (ETM) to use? + constant INCLUDE_ETM : integer range c_NO to c_YES := c_NO; + type ETM_CHOICE_type is (ETM_CHOICE_MBS_VULOM, ETM_CHOICE_MAINZ_A2, ETM_CHOICE_CBMNET, ETM_CHOICE_M26, ETM_CHOICE_R3B); + constant ETM_CHOICE : ETM_CHOICE_type := ETM_CHOICE_MBS_VULOM; + constant ETM_ID : std_logic_vector(7 downto 0); + + constant INCLUDE_TIMESTAMP_GENERATOR : integer := c_NO; + +------------------------------------------------------------------------------ +--End of design configuration +------------------------------------------------------------------------------ + + type hub_ct is array(0 to 16) of integer; + type intlist_t is array(0 to 7) of integer; + + + constant INTERFACE_NUM : integer := 1; + constant IS_UPLINK : hub_ct := (0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0); + constant IS_DOWNLINK : hub_ct := (0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0); + constant IS_UPLINK_ONLY : hub_ct := (0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0); + + +------------------------------------------------------------------------------ +--Select settings by configuration +------------------------------------------------------------------------------ + + constant cts_rdo_additional_ports : integer := 1; --for internal endpoint + constant HW_INFO_BASE : unsigned(31 downto 0) := x"A5000100"; + + constant CLOCK_FREQUENCY_ARR : intlist_t := (100,120, others => 0); + constant MEDIA_FREQUENCY_ARR : intlist_t := (200,240, others => 0); + + --declare constants, filled in body + constant HARDWARE_INFO : std_logic_vector(31 downto 0); + constant CLOCK_FREQUENCY : integer; + constant MEDIA_FREQUENCY : integer; + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0); + constant BROADCAST_BITMASK : std_logic_vector(7 downto 0) := (7 => (not std_logic_vector(to_unsigned(USE_GBE,1))(0)), others => '1'); + +end; + +package body config is +--compute correct configuration mode + + constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector( HW_INFO_BASE ); + constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_120_MHZ); + constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_120_MHZ); + + + + function etm_id_func return std_logic_vector is + variable res : unsigned(7 downto 0); + begin + res := x"00"; + if INCLUDE_ETM=c_YES then + res := x"60"; + res := res + TO_UNSIGNED(ETM_CHOICE_type'pos(ETM_CHOICE), 4); + end if; + return std_logic_vector(res); + end function; + + constant ETM_ID : std_logic_vector(7 downto 0) := etm_id_func; + + + +function generateIncludedFeatures return std_logic_vector is + variable t : std_logic_vector(63 downto 0); + begin + t := (others => '0'); + t(63 downto 56) := std_logic_vector(to_unsigned(2,8)); --table version 1 + +-- t(7 downto 0) := std_logic_vector(to_unsigned(1,8)); +-- t(11 downto 8) := std_logic_vector(to_unsigned(DOUBLE_EDGE_TYPE,4)); +-- t(14 downto 12) := std_logic_vector(to_unsigned(RING_BUFFER_SIZE,3)); +-- t(15) := '1'; --TDC +-- t(17 downto 16) := std_logic_vector(to_unsigned(NUM_TDC_MODULES-1,2)); + t(16 downto 16) := std_logic_vector(to_unsigned(USE_GBE,1)); + t(28 downto 28) := std_logic_vector(to_unsigned(0,1)); + + t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1)); + t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1)); + t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1)); + t(47 downto 47) := std_logic_vector(to_unsigned(INCLUDE_I2C,1)); + t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4)); + t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1)); + t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1)); + t(54 downto 54) := "0";--std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1)); + return t; + end function; + + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures; + +end package body; diff --git a/mimosis_standalone/config_compile_frankfurt.pl b/mimosis_standalone/config_compile_frankfurt.pl new file mode 100644 index 0000000..d941a92 --- /dev/null +++ b/mimosis_standalone/config_compile_frankfurt.pl @@ -0,0 +1,25 @@ +Familyname => 'ECP5UM', +Devicename => 'LFE5UM-85F', +Package => 'CABGA756', +Speedgrade => '8', + + +TOPNAME => "trb5sc_mimosis", +lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; +lm_license_file_for_par => "1710\@jspc29", +lattice_path => '/d/jspc29/lattice/diamond/3.12', +synplify_path => '/d/jspc29/lattice/synplify/V-2023.09-SP1/',#T-2022.09-SP2/', + +nodelist_file => '../nodelist_frankfurt.txt', +pinout_file => 'trb5sc_hdmi', +par_options => '../par.p2t', + + +#Include only necessary lpf files +include_TDC => 0, +include_GBE => 1, + +#Report settings +firefox_open => 0, +twr_number_of_errors => 20, +no_ltxt2ptxt => 1, #if there is no serdes being used diff --git a/mimosis_standalone/par.p2t b/mimosis_standalone/par.p2t new file mode 100644 index 0000000..682a299 --- /dev/null +++ b/mimosis_standalone/par.p2t @@ -0,0 +1,69 @@ +-w +#-y +-l 5 +#-m nodelist.txt # Controlled by the compile.pl script. +#-n 1 # Controlled by the compile.pl script. +-s 10 +-t 14 +-c 2 +-e 2 +-i 10 +#-exp parPlcInLimit=0 +#-exp parPlcInNeighborSize=1 +#General PAR Command Line Options +# -w With this option, any files generated will overwrite existing files +# (e.g., any .par, .pad files). +# -y Adds the Delay Summary Report in the .par file and creates the delay +# file (in .dly format) at the end of the par run. +# +#PAR Placement Command Line Options +# -l Specifies the effort level of the design from 1 (simplest designs) +# to 5 (most complex designs). +# -m Multi-tasking option. Controlled by the compile.pl script. +# -n Sets the number of iterations performed at the effort level +# specified by the -l option. Controlled by the compile.pl script. +# -s Save the number of best results for this run. +# -t Start placement at the specified cost table. Default is 1. +# +#PAR Routing Command Line Options +# -c Run number of cost-based cleanup passes of the router. +# -e Run number of delay-based cleanup passes of the router on +# completely-routed designs only. +# -i Run a maximum number of passes, stopping earlier only if the routing +# goes to 100 percent completion and all constraints are met. +# +#PAR Explorer Command Line Options +# parCDP Enable the congestion-driven placement (CDP) algorithm. CDP is +# compatible with all Lattice FPGA device families; however, most +# benefit has been demonstrated with benchmarks targeted to ECP5, +# LatticeECP2/M, LatticeECP3, and LatticeXP2 device families. +# parCDR Enable the congestion-driven router (CDR) algorithm. +# Congestion-driven options like parCDR and parCDP can improve +# performance given a design with multiple congestion “hotspots.” The +# Layer > Congestion option of the Design Planner Floorplan View can +# help visualize routing congestion. Large congested areas may prevent +# the options from finding a successful solution. +# CDR is compatible with all Lattice FPGA device families however most +# benefit has been demonstrated with benchmarks targeted to ECP5, +# LatticeECP2/M,LatticeECP3, and LatticeXP2 device families. +# paruseNBR NBR Router or Negotiation-based routing option. Supports all +# FPGA device families except LatticeXP and MachXO. +# When turned on, an alternate routing engine from the traditional +# Rip-up-based routing selection (RBR) is used. This involves an +# iterative routing algorithm that routes connections to achieve +# minimum delay cost. It does so by computing the demand on each +# routing resource and applying cost values per node. It will +# complete when an optimal solution is arrived at or the number of +# iterations is reached. +# parPathBased Path-based placement option. Path-based timing driven +# placement will yield better performance and more +# predictable results in many cases. +# parHold Additional hold time correction option. This option +# forces the router to automatically insert extra wires to compensate for the +# hold time violation. +# parHoldLimit This option allows you to set a limit on the number of +# hold time violations to be processed by the auto hold time correction option +# parHold. +# parPlcInLimit Cannot find in the online help +# parPlcInNeighborSize Cannot find in the online help +-exp parHold=ON:parHoldLimit=10000:parCDP=1:parCDR=1:parPathBased=OFF:paruseNBR=1 diff --git a/mimosis_standalone/trb5sc_mimosis.lpf b/mimosis_standalone/trb5sc_mimosis.lpf new file mode 100644 index 0000000..9d59a07 --- /dev/null +++ b/mimosis_standalone/trb5sc_mimosis.lpf @@ -0,0 +1,53 @@ + +################################################################# +# Basic Settings +################################################################# + +FREQUENCY PORT CLK_200 200 MHz; +FREQUENCY PORT CLK_125 125 MHz; +FREQUENCY PORT CLK_EXT 200 MHz; + +FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz; +FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs1.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz; +# FREQUENCY NET "med_stat_debug[11]" 200 MHz; + +# FREQUENCY NET "med2int_0.clk_full" 200 MHz; +# FREQUENCY NET THE_MEDIA_INTERFACE/clk_rx_full 200 MHz; + + +BLOCK PATH TO PORT "LED*"; +BLOCK PATH TO PORT "PROGRAMN"; +BLOCK PATH TO PORT "TEMP_LINE"; +BLOCK PATH FROM PORT "TEMP_LINE"; +BLOCK PATH TO PORT "TEST_LINE*"; + +MULTICYCLE FROM CELL "THE_HUB/THE_HUB/reset_i" 15 ns; + + +#MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/trb_reset_pulse*" 20 ns; +#MULTICYCLE FROM CELL "THE_CLOCK_RESET/clear_n_i" 20 ns; +#MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns; +MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns; + +# MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_SCI_READER/PROC_SCI_CTRL.BUS_TX*" 10 ns; +# MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT*" 10 ns; + +GSR_NET NET "clear_i"; + +# LOCATE COMP "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/DCU0_inst" SITE "DCU0" ; + + +REGION "MEDIA" "R81C44D" 13 25; +LOCATE UGROUP "THE_MEDIA_INTERFACE/media_interface_group" REGION "MEDIA" ; + + +BLOCK NET "THE_MIMOSIS/THE_IN/reset_i"; +BLOCK NET "THE_MIMOSIS/THE_WORDS/reset_i"; +MULTICYCLE FROM CELL "THE_MIMOSIS/THE_IN/PROC_REGS.add_re*" 20 ns; +MULTICYCLE FROM CELL "THE_MIMOSIS/THE_IN/add_re*" 20 ns; +MULTICYCLE FROM CELL "THE_MIMOSIS/THE_WORDS/CONF*" 20 ns; +MULTICYCLE FROM CELL "THE_MIMOSIS/THE_WORDS/PROC_REGS.control_re*" 20 ns; + +BLOCK PATH TO CELL "THE_MIMOSIS/THE_IN/PROC_REGS.BUS_TX.dat*"; +BLOCK PATH TO CELL "THE_MIMOSIS/THE_WORDS/PROC_REGS.BUS_TX.dat*"; + diff --git a/mimosis_standalone/trb5sc_mimosis.prj b/mimosis_standalone/trb5sc_mimosis.prj new file mode 100644 index 0000000..34ed411 --- /dev/null +++ b/mimosis_standalone/trb5sc_mimosis.prj @@ -0,0 +1,302 @@ + +# implementation: "workdir" +impl -add workdir -type fpga + +# device options +set_option -technology ECP5UM +set_option -part LFE5UM_85F +set_option -package BG756C +set_option -speed_grade -8 +set_option -part_companion "" + +# compilation/mapping options +set_option -default_enum_encoding sequential +set_option -symbolic_fsm_compiler 1 +set_option -top_module "trb5sc_mimosis" +set_option -resource_sharing false +set_option -vhdl2008 true + +# map options +set_option -frequency 120 +set_option -fanout_limit 100 +set_option -disable_io_insertion 0 +set_option -retiming 1 +set_option -pipe 1 +set_option -forcegsr false +set_option -fixgatedclocks 3 +set_option -fixgeneratedclocks 3 +set_option -compiler_compatible true +set_option -multi_file_compilation_unit 1 + +set_option -max_parallel_jobs 3 +#set_option -automatic_compile_point 1 +#set_option -continue_on_error 1 +set_option -resolve_multiple_driver 1 + +# simulation options +set_option -write_verilog 0 +set_option -write_vhdl 1 + +# automatic place and route (vendor) options +set_option -write_apr_constraint 0 + +# set result format/file last +project -result_format "edif" +project -result_file "workdir/trb5sc_mimosis.edf" +set_option log_file "workdir/trb5sc_mimosis.srf" +#implementation attributes + +set_option -vlog_std v2001 +set_option -project_relative_includes 1 +impl -active "workdir" + +#################### + +add_file -vhdl -lib work "workdir/lattice-diamond/cae_library/synthesis/vhdl/ecp5um.vhd" + +#Packages +add_file -vhdl -lib work "workdir/version.vhd" +add_file -vhdl -lib work "config.vhd" +add_file -vhdl -lib work "../../trb3/base/trb3_components.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_func.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_protocols.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_components.vhd" + +#Basic Infrastructure +add_file -vhdl -lib work "../../dirich/cores/pll_240_100/pll_240_100.vhd" +add_file -vhdl -lib work "../../dirich/code/clock_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd" +add_file -vhdl -lib work "../../vhdlbasics/ecp5/sedcheck.vhd" + + +#Fifos +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net16_fifo_arch.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16bit_dualport/lattice_ecp5_fifo_16bit_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net_fifo_16bit_bram_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x256_oreg/fifo_36x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x2k_oreg/fifo_18x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_9x2k_oreg/fifo_9x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16x16_dualport/lattice_ecp5_fifo_16x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport/lattice_ecp5_fifo_18x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_36x16_dualport_oreg/lattice_ecp5_fifo_36x16_dualport_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_19x16.vhd" + + +#Flash & Reload, Tools +add_file -vhdl -lib work "../../trbnet/special/slv_register.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" +add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd" +add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd" +add_file -vhdl -lib work "../../trb3sc/code/common_i2c.vhd" +add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" +add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd" +add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd" +add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_19x8_preset.vhd" +add_file -vhdl -lib work "../../trb3sc/code/adc_controller.vhd" + +#SlowControl files +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd" + +#Media interface +# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd" +# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd" +# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_rx_reset_RS.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_tx_reset_RS.vhd" +# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" +# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" +# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd" +# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control.vhd" +# add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync.vhd" + + +######################################### +#channel 0, backplane +#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_0/serdes_sync_0.vhd" + +#channel 1, SFP +# add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_1/serdes_sync_0.vhd" +########################################## + +# add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs.vhd" +# add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs2.vhd" +# add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0_softlogic.v" + + +#TrbNet Endpoint +add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_api_ipu_streaming.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd" +add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd" + +add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_gbe.vhd" +add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd" + +add_file -vhdl -lib work "../../trbnet/special/trb_net_i2cwire.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_gstart.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim.vhd" + +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_gstart2.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb2.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim2.vhd" + +#Hub +add_file -vhdl -lib work "../../trbnet/basics/priority_arbiter.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_streaming_port_sctrl_cts.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_base.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_logic_2.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_ipu_logic.vhd" +add_file -vhdl -lib work "../../trbnet/basics/wide_adder_17x16.vhd" + +add_file -vhdl -lib work "../../trbnet/trb_net16_api_ipu_streaming_internal.vhd" + + + +#GbE +add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/base/gbe_wrapper.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_logic_wrapper.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/base/gbe_med_interface_single.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_multiplexer.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_dummy.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_type_validator.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_receiver.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_receive_control.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_main_control.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_mac_control.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_prioritizer.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_selector.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_protocol_selector.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_trans.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_constr.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_transmit_control2.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_ipu_interface.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_event_constr.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_setup.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/ip_configurator.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_ARP.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Ping.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/gbe_response_constructor_Ping.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_DHCP.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_SCTRL.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_TrbNetData.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_KillPing.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Forward.vhd" +add_file -verilog -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/serdes_gbe_softlogic.v" +# Choose your SerDes location here +#add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/d0ch0/serdes_gbe.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/d0ch1/serdes_gbe.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/d1ch0/serdes_gbe.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/d1ch1/serdes_gbe.vhd" + +#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_8kx9.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_4096x9.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x32.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x32x8.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x72.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9_af.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_32kx16x8_mb2.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_2048x8x16.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_65536x18x9.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/slv_mac_memory.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/ip_mem.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx18x9_wcnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_32kx18x9_wcnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9_af_cnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_8kx9_af_cnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_2kx9x18_wcnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_4kx18x9_wcnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/ram_dp_true_2kx9.vhd" + + +add_file -vhdl -lib work "../../trb3/cts/source/cts_pkg.vhd" +add_file -vhdl -lib work "../../trb3/cts/source/timestamp_generator.vhd" +add_file -vhdl -lib work "../../trb3/cts/source/cts_fifo.vhd" +add_file -vhdl -lib work "../../trb3/cts/source/cts_trg_input.vhd" +add_file -vhdl -lib work "../../trb3/cts/source/cts_trg_coin.vhd" +add_file -vhdl -lib work "../../trb3/cts/source/cts_trg_pseudorand_pulser.vhd" +add_file -vhdl -lib work "../../trb3/cts/source/cts_trigger.vhd" +add_file -vhdl -lib work "../../trb3/cts/source/cts.vhd" + +add_file -vhdl -lib work "../mimosis/cores/mimosis_inp.vhd" +add_file -vhdl -lib work "../mimosis/cores/testout.vhd" +add_file -vhdl -lib work "../mimosis/code/MimosisInput.vhd" +add_file -vhdl -lib work "../mimosis/code/InputStage.vhd" +add_file -vhdl -lib work "../mimosis/code/WordAlign.vhd" +add_file -vhdl -lib work "../mimosis/cores/pll_200_160/pll_200_160.vhd" + + + +add_file -vhdl -lib work "./trb5sc_mimosis.vhd" +#add_file -fpga_constraint "./synplify.fdc" + + + diff --git a/mimosis_standalone/trb5sc_mimosis.vhd b/mimosis_standalone/trb5sc_mimosis.vhd new file mode 100644 index 0000000..a7d2d58 --- /dev/null +++ b/mimosis_standalone/trb5sc_mimosis.vhd @@ -0,0 +1,875 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.version.all; +use work.config.all; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +-- use work.med_sync_define.all; +use work.trb_net16_hub_func.all; +use work.trb_net_gbe_components.all; +use work.cts_pkg.all; + + +entity trb5sc_mimosis is + port( + CLK_200 : in std_logic; + CLK_125 : in std_logic; + CLK_EXT : in std_logic; + + TRIG_IN_RJ45 : in std_logic; --Reference Time + IN_SELECT_EXT_CLOCK : in std_logic; + + SFP_TX_DIS : out std_logic; + SFP_LOS : in std_logic; + SFP_MOD_0 : in std_logic; + + --HDMI AddOn + LED_ADDON_SFP_ORANGE : out std_logic_vector(1 downto 0); + LED_ADDON_SFP_GREEN : out std_logic_vector(1 downto 0); + LED_ADDON_RJ : out std_logic_vector(1 downto 0); + SFP_ADDON_TX_DIS : out std_logic_vector(1 downto 0); + SFP_ADDON_LOS : in std_logic_vector(1 downto 0); + + RJ : inout std_logic_vector(3 downto 0); + H1 : inout std_logic_vector(4 downto 0); + H2 : inout std_logic_vector(4 downto 0); + H3 : inout std_logic_vector(3 downto 0); + H4 : inout std_logic_vector(4 downto 0); + H5 : inout std_logic_vector(3 downto 0); + H6 : inout std_logic_vector(4 downto 0); + H7 : inout std_logic_vector(4 downto 0); + + PIN : out std_logic_vector(8 downto 1); + + MIMOSIS_SCL, MIMOSIS_SDA : inout std_logic; + + + --ADC + ADC_SCLK : out std_logic; + ADC_NCS : out std_logic; + ADC_MOSI : out std_logic; + ADC_MISO : in std_logic; + --Flash, Reload + FLASH_SCLK : out std_logic; + FLASH_NCS : out std_logic; + FLASH_MOSI : out std_logic; + FLASH_MISO : in std_logic; + FLASH_HOLD : out std_logic; + FLASH_WP : out std_logic; + PROGRAMN : out std_logic; + --I2C + I2C_SDA : inout std_logic; + I2C_SCL : inout std_logic; + TMP_ALERT : in std_logic; + + --LED + LED : out std_logic_vector(8 downto 1); + LED_SFP_YELLOW : out std_logic; + LED_SFP_GREEN : out std_logic; + LED_SFP_RED : out std_logic; + LED_RJ_GREEN : out std_logic_vector(1 downto 0); + LED_RJ_RED : out std_logic_vector(1 downto 0); + LED_EXT_CLOCK : out std_logic; + + --Other Connectors + TEST : inout std_logic_vector(14 downto 1); --on v1 only + --COMMON_SDA, COMMON_SCL : inout std_logic + HDR_IO : inout std_logic_vector(23 downto 0) --23..16 on v2 only + ); + + attribute syn_useioff : boolean; + attribute syn_useioff of FLASH_NCS : signal is true; + attribute syn_useioff of FLASH_SCLK : signal is true; + attribute syn_useioff of FLASH_MOSI : signal is true; + attribute syn_useioff of FLASH_MISO : signal is true; + +end entity; + +architecture arch of trb5sc_mimosis is + + attribute syn_keep : boolean; + attribute syn_preserve : boolean; + + signal clk_sys, clk_full, clk_full_osc : std_logic; + signal clk_40, clk_80, clk_160, clk_320 : std_logic; + signal GSR_N : std_logic; + signal reset_i : std_logic; + signal clear_i : std_logic; + signal trigger_in_i : std_logic; + + attribute syn_keep of GSR_N : signal is true; + attribute syn_preserve of GSR_N : signal is true; + + signal debug_clock_reset : std_logic_vector(31 downto 0); + signal external_clock_lock : std_logic := '0'; + signal debug_tools : std_logic_vector(31 downto 0); + + --Media Interface + signal med2int : med2int_array_t(0 to 0); + signal int2med : int2med_array_t(0 to 0); + signal med_stat_debug : std_logic_vector (1*64-1 downto 0); + signal sfp_los_i, sfp_txdis_i, sfp_prsnt_i : std_logic; + signal reboot_from_gbe : std_logic; + signal reset_via_gbe : std_logic; + + + + signal ctrlbus_tx, bustools_tx, buscts_tx, bustc_tx, busgbeip_tx, busgbereg_tx, bus_master_in, busmimosis_tx, busi2c_tx : CTRLBUS_TX; + signal ctrlbus_rx, bustools_rx, buscts_rx, bustc_rx, busgbeip_rx, busgbereg_rx, bus_master_out, busmimosis_rx, busi2c_rx : CTRLBUS_RX; + + signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); + signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); + + signal sed_error_i : std_logic; + signal clock_select : std_logic; + signal bus_master_active : std_logic; + signal flash_ncs_i : std_logic; + signal rdack, wrack : std_logic; + + + signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0); + signal header_io_i : std_logic_vector(10 downto 1); + signal timer : TIMERS; + signal add_reg : std_logic_vector(31 downto 0); + alias led_off : std_logic is add_reg(0); + + signal gbe_status : std_logic_vector(15 downto 0); + + signal clk_350, clk_50, clk_200bypass : std_logic; + + signal monitor_inputs_i : std_logic_vector(MONITOR_INPUT_NUM-1 downto 0); + signal trigger_gen_outputs_i: std_logic_vector(TRIG_GEN_OUTPUT_NUM-1 downto 0); + signal trigger_busy_i : std_logic; + signal cts_trigger_out : std_logic; + + signal gbe_cts_number : std_logic_vector(15 downto 0); + signal gbe_cts_code : std_logic_vector(7 downto 0); + signal gbe_cts_information : std_logic_vector(7 downto 0); + signal gbe_cts_start_readout : std_logic; + signal gbe_cts_readout_type : std_logic_vector(3 downto 0); + signal gbe_cts_readout_finished : std_logic; + signal gbe_cts_status_bits : std_logic_vector(31 downto 0); + signal gbe_fee_data : std_logic_vector(15 downto 0); + signal gbe_fee_dataready : std_logic; + signal gbe_fee_read : std_logic; + signal gbe_fee_status_bits : std_logic_vector(31 downto 0); + signal gbe_fee_busy : std_logic; + + signal gsc_init_data, gsc_reply_data : std_logic_vector(15 downto 0); + signal gsc_init_read, gsc_reply_read : std_logic; + signal gsc_init_dataready, gsc_reply_dataready : std_logic; + signal gsc_init_packet_num, gsc_reply_packet_num : std_logic_vector(2 downto 0); + signal gsc_busy : std_logic; + + signal cts_rdo_trg_status_bits_cts : std_logic_vector(31 downto 0) := (others => '0'); + signal cts_rdo_data : std_logic_vector(31 downto 0); + signal cts_rdo_write : std_logic; + signal cts_rdo_finished : std_logic; + + -- signal cts_ext_trigger : std_logic; + -- signal cts_ext_status : std_logic_vector(31 downto 0) := (others => '0'); + -- signal cts_ext_control : std_logic_vector(31 downto 0); + -- signal cts_ext_debug : std_logic_vector(31 downto 0); + -- signal cts_ext_header : std_logic_vector(1 downto 0) := "00"; + + signal cts_rdo_additional_data : std_logic_vector(32*cts_rdo_additional_ports-1 downto 0); + signal cts_rdo_additional_write : std_logic_vector(cts_rdo_additional_ports-1 downto 0) := (others => '0'); + signal cts_rdo_additional_finished : std_logic_vector(cts_rdo_additional_ports-1 downto 0) := (others => '1'); + signal cts_rdo_trg_status_bits_additional : std_logic_vector(32*cts_rdo_additional_ports-1 downto 0) := (others => '0'); + + signal cts_rdo_additional : readout_tx_array_t(0 to cts_rdo_additional_ports-1); + signal cts_rdo_rx : READOUT_RX; + + + signal cts_addon_triggers_in : std_logic_vector(ADDON_LINE_COUNT-1 downto 0); + signal cts_monitor_out : std_logic_vector(CTS_OUTPUT_MULTIPLEXERS-1 downto 0); + + + signal cts_trg_send : std_logic; + signal cts_trg_type : std_logic_vector(3 downto 0); + signal cts_trg_number : std_logic_vector(15 downto 0); + signal cts_trg_information : std_logic_vector(23 downto 0); + signal cts_trg_code : std_logic_vector(7 downto 0); + signal cts_trg_status_bits : std_logic_vector(31 downto 0); + signal cts_trg_busy : std_logic; + + signal cts_ipu_send : std_logic; + signal cts_ipu_type : std_logic_vector(3 downto 0); + signal cts_ipu_number : std_logic_vector(15 downto 0); + signal cts_ipu_information : std_logic_vector(7 downto 0); + signal cts_ipu_code : std_logic_vector(7 downto 0); + signal cts_ipu_status_bits : std_logic_vector(31 downto 0); + signal cts_ipu_busy : std_logic; + + signal reset_via_gbe_long, reset_via_gbe_timer, last_reset_via_gbe_long, make_reset : std_logic; + + + signal inp_i : std_logic_vector( 7 downto 0); + + signal i2c_reg_0, i2c_reg_1 : std_logic_vector(31 downto 0); + signal i2c_reg_2 : std_logic_vector(31 downto 0); + signal i2c_reg_4, i2c_reg_5 : std_logic_vector(31 downto 0); + signal mimosis_scl_drv, mimosis_sda_drv : std_logic; + signal i2c_go_100, i2c_go : std_logic; + signal i2c_reg_5_40 : std_logic_vector(31 downto 0); + signal counter : unsigned(23 downto 0); + +begin + + -- trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and not IN_SELECT_EXT_CLOCK); + +--------------------------------------------------------------------------- +-- Clock & Reset Handling +--------------------------------------------------------------------------- + THE_CLOCK_RESET : entity work.clock_reset_handler + port map( + CLOCK_IN => CLK_200, + RESET_FROM_NET => make_reset,--med2int(0).stat_op(13), + SEND_RESET_IN => '0', --med2int(0).stat_op(15), + + BUS_RX => bustc_rx, + BUS_TX => bustc_tx, + + RESET_OUT => reset_i, + CLEAR_OUT => clear_i, + GSR_OUT => GSR_N, + + REF_CLK_OUT => clk_full, + SYS_CLK_OUT => clk_sys, + RAW_CLK_OUT => clk_full_osc, + + DEBUG_OUT => debug_clock_reset + ); + + + THE_160_PLL : entity work.pll_200_160 + port map( + CLKI => clk_full_osc, + CLKOP => clk_160, + CLKOS => clk_320, + CLKOS2=> clk_40, + CLKOS3=> clk_80 + ); + + H3(3) <= clk_320; + + -- For IPHC Proxy + -- RJ(0) <= clk_40; + -- For IKF Proxy + H1(4) <= clk_40; + + + proc_make_reset : process begin + wait until rising_edge(clk_sys); + if(reset_via_gbe = '1') then + reset_via_gbe_long <= '1'; + reset_via_gbe_timer <= '1'; + end if; + if timer.tick_us = '1' then + reset_via_gbe_timer <= '0'; + reset_via_gbe_long <= reset_via_gbe_timer; + end if; + last_reset_via_gbe_long <= reset_via_gbe_long; + make_reset <= last_reset_via_gbe_long and not reset_via_gbe_long; + end process; + +--------------------------------------------------------------------------- +-- GbE +--------------------------------------------------------------------------- + GBE : entity work.gbe_wrapper + generic map( + DO_SIMULATION => 0, + INCLUDE_DEBUG => 0, + USE_INTERNAL_TRBNET_DUMMY => 0, + USE_EXTERNAL_TRBNET_DUMMY => 0, + RX_PATH_ENABLE => 1, + FIXED_SIZE_MODE => 1, + INCREMENTAL_MODE => 1, + FIXED_SIZE => 100, + FIXED_DELAY_MODE => 1, + UP_DOWN_MODE => 0, + UP_DOWN_LIMIT => 100, + FIXED_DELAY => 100, + + NUMBER_OF_GBE_LINKS => 1, + LINKS_ACTIVE => "0001", + + LINK_HAS_READOUT => "0001", + LINK_HAS_SLOWCTRL => "0001", + LINK_HAS_DHCP => "0001", + LINK_HAS_ARP => "0001", + LINK_HAS_PING => "0001", + LINK_HAS_FWD => "0000" + ) + + port map( + CLK_SYS_IN => clk_sys, + CLK_125_IN => CLK_125, + RESET => reset_i, + GSR_N => GSR_N, + + TRIGGER_IN => cts_rdo_rx.data_valid, + + SD_PRSNT_N_IN(0) => SFP_MOD_0, + SD_LOS_IN(0) => SFP_LOS, + SD_TXDIS_OUT(0) => SFP_TX_DIS, + + CTS_NUMBER_IN => gbe_cts_number, + CTS_CODE_IN => gbe_cts_code, + CTS_INFORMATION_IN => gbe_cts_information, + CTS_READOUT_TYPE_IN => gbe_cts_readout_type, + CTS_START_READOUT_IN => gbe_cts_start_readout, + CTS_DATA_OUT => open, + CTS_DATAREADY_OUT => open, + CTS_READOUT_FINISHED_OUT => gbe_cts_readout_finished, + CTS_READ_IN => '1', + CTS_LENGTH_OUT => open, + CTS_ERROR_PATTERN_OUT => gbe_cts_status_bits, + + FEE_DATA_IN => gbe_fee_data, + FEE_DATAREADY_IN => gbe_fee_dataready, + FEE_READ_OUT => gbe_fee_read, + FEE_STATUS_BITS_IN => gbe_fee_status_bits, + FEE_BUSY_IN => gbe_fee_busy, + + MC_UNIQUE_ID_IN => timer.uid, + MY_TRBNET_ADDRESS_IN => timer.network_address, + ISSUE_REBOOT_OUT => reboot_from_gbe, + + GSC_CLK_IN => clk_sys, + GSC_INIT_DATAREADY_OUT => gsc_init_dataready, + GSC_INIT_DATA_OUT => gsc_init_data, + GSC_INIT_PACKET_NUM_OUT => gsc_init_packet_num, + GSC_INIT_READ_IN => gsc_init_read, + GSC_REPLY_DATAREADY_IN => gsc_reply_dataready, + GSC_REPLY_DATA_IN => gsc_reply_data, + GSC_REPLY_PACKET_NUM_IN => gsc_reply_packet_num, + GSC_REPLY_READ_OUT => gsc_reply_read, + GSC_BUSY_IN => gsc_busy, + + BUS_IP_RX => busgbeip_rx, + BUS_IP_TX => busgbeip_tx, + BUS_REG_RX => busgbereg_rx, + BUS_REG_TX => busgbereg_tx, + + MAKE_RESET_OUT => reset_via_gbe, + STATUS_OUT => gbe_status, --open, + DEBUG_OUT => open + ); + +--------------------------------------------------------------------------- +-- Hub +--------------------------------------------------------------------------- + THE_HUB : trb_net16_hub_streaming_port_sctrl_cts + generic map( + INIT_ADDRESS => INIT_ADDRESS, + MII_NUMBER => INTERFACE_NUM, + MII_IS_UPLINK => IS_UPLINK, + MII_IS_DOWNLINK => IS_DOWNLINK, + MII_IS_UPLINK_ONLY => IS_UPLINK_ONLY, + HARDWARE_VERSION => HARDWARE_INFO, + INCLUDED_FEATURES => INCLUDED_FEATURES, + INIT_ENDPOINT_ID => x"0001", + BROADCAST_BITMASK => x"7E", + CLOCK_FREQUENCY => 100, + USE_ONEWIRE => c_I2C, + BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR, + RDO_ADDITIONAL_PORT => cts_rdo_additional_ports, + RDO_DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE, + RDO_DATA_BUFFER_FULL_THRESH => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE, + RDO_HEADER_BUFFER_DEPTH => 9, + RDO_HEADER_BUFFER_FULL_THRESH => 2**9-16 + ) + port map ( + CLK => clk_sys, + RESET => reset_i, + CLK_EN => '1', + + -- Media interfacces --------------------------------------------------------------- + MED_DATAREADY_OUT(INTERFACE_NUM*1-1 downto 0) => open, + MED_DATA_OUT(INTERFACE_NUM*16-1 downto 0) => open, + MED_PACKET_NUM_OUT(INTERFACE_NUM*3-1 downto 0) => open, + MED_READ_IN(INTERFACE_NUM*1-1 downto 0) => (others => '0'), + MED_DATAREADY_IN(INTERFACE_NUM*1-1 downto 0) => (others => '0'), + MED_DATA_IN(INTERFACE_NUM*16-1 downto 0) => (others => '0'), + MED_PACKET_NUM_IN(INTERFACE_NUM*3-1 downto 0) => (others => '0'), + MED_READ_OUT(INTERFACE_NUM*1-1 downto 0) => open, + MED_STAT_OP(2 downto 0) => ERROR_NC, + MED_STAT_OP(INTERFACE_NUM*16-1 downto 3) => (others => '0'), + MED_CTRL_OP(INTERFACE_NUM*16-1 downto 0) => open, + + -- Gbe Read-out Path --------------------------------------------------------------- + --Event information coming from CTS for GbE + GBE_CTS_NUMBER_OUT => gbe_cts_number, + GBE_CTS_CODE_OUT => gbe_cts_code, + GBE_CTS_INFORMATION_OUT => gbe_cts_information, + GBE_CTS_READOUT_TYPE_OUT => gbe_cts_readout_type, + GBE_CTS_START_READOUT_OUT => gbe_cts_start_readout, + --Information sent to CTS + GBE_CTS_READOUT_FINISHED_IN => gbe_cts_readout_finished, + GBE_CTS_STATUS_BITS_IN => gbe_cts_status_bits, + -- Data from Frontends + GBE_FEE_DATA_OUT => gbe_fee_data, + GBE_FEE_DATAREADY_OUT => gbe_fee_dataready, + GBE_FEE_READ_IN => gbe_fee_read, + GBE_FEE_STATUS_BITS_OUT => gbe_fee_status_bits, + GBE_FEE_BUSY_OUT => gbe_fee_busy, + + -- CTS Request Sending ------------------------------------------------------------- + --LVL1 trigger + CTS_TRG_SEND_IN => cts_trg_send, + CTS_TRG_TYPE_IN => cts_trg_type, + CTS_TRG_NUMBER_IN => cts_trg_number, + CTS_TRG_INFORMATION_IN => cts_trg_information, + CTS_TRG_RND_CODE_IN => cts_trg_code, + CTS_TRG_STATUS_BITS_OUT => cts_trg_status_bits, + CTS_TRG_BUSY_OUT => cts_trg_busy, + --IPU Channel + CTS_IPU_SEND_IN => cts_ipu_send, + CTS_IPU_TYPE_IN => cts_ipu_type, + CTS_IPU_NUMBER_IN => cts_ipu_number, + CTS_IPU_INFORMATION_IN => cts_ipu_information, + CTS_IPU_RND_CODE_IN => cts_ipu_code, + -- Receiver port + CTS_IPU_STATUS_BITS_OUT => cts_ipu_status_bits, + CTS_IPU_BUSY_OUT => cts_ipu_busy, + + -- CTS Data Readout ---------------------------------------------------------------- + --Trigger to CTS out + RDO_TRIGGER_IN => cts_trigger_out, + RDO_TRG_DATA_VALID_OUT => cts_rdo_rx.data_valid, + RDO_VALID_TIMING_TRG_OUT => cts_rdo_rx.valid_timing_trg, + RDO_VALID_NOTIMING_TRG_OUT => cts_rdo_rx.valid_notiming_trg, + RDO_INVALID_TRG_OUT => cts_rdo_rx.invalid_trg, + RDO_TRG_TYPE_OUT => cts_rdo_rx.trg_type, + RDO_TRG_CODE_OUT => cts_rdo_rx.trg_code, + RDO_TRG_INFORMATION_OUT => cts_rdo_rx.trg_information, + RDO_TRG_NUMBER_OUT => cts_rdo_rx.trg_number, + + --Data from CTS in + RDO_TRG_STATUSBITS_IN => cts_rdo_trg_status_bits_cts, + RDO_DATA_IN => cts_rdo_data, + RDO_DATA_WRITE_IN => cts_rdo_write, + RDO_DATA_FINISHED_IN => cts_rdo_finished, + --Data from additional modules + RDO_ADDITIONAL_STATUSBITS_IN => cts_rdo_trg_status_bits_additional, + RDO_ADDITIONAL_DATA => cts_rdo_additional_data, + RDO_ADDITIONAL_WRITE => cts_rdo_additional_write, + RDO_ADDITIONAL_FINISHED => cts_rdo_additional_finished, + + -- Slow Control -------------------------------------------------------------------- + COMMON_STAT_REGS => open, + COMMON_CTRL_REGS => common_ctrl_reg, + ONEWIRE => open, + ONEWIRE_MONITOR_IN => open, + I2C_SCL => I2C_SCL, + I2C_SDA => I2C_SDA, + MY_ADDRESS_OUT => timer.network_address, + UNIQUE_ID_OUT => timer.uid, + BUS_MASTER_IN => bus_master_in, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + TIMER_TICKS_OUT(0) => timer.tick_us, + TIMER_TICKS_OUT(1) => timer.tick_ms, + TEMPERATURE_OUT => timer.temperature, + EXTERNAL_SEND_RESET => reset_via_gbe, + + REGIO_ADDR_OUT => ctrlbus_rx.addr, + REGIO_READ_ENABLE_OUT => ctrlbus_rx.read, + REGIO_WRITE_ENABLE_OUT => ctrlbus_rx.write, + REGIO_DATA_OUT => ctrlbus_rx.data, + REGIO_DATA_IN => ctrlbus_tx.data, + REGIO_DATAREADY_IN => rdack, + REGIO_NO_MORE_DATA_IN => ctrlbus_tx.nack, + REGIO_WRITE_ACK_IN => wrack, + REGIO_UNKNOWN_ADDR_IN => ctrlbus_tx.unknown, + REGIO_TIMEOUT_OUT => ctrlbus_rx.timeout, + + --Gbe Sctrl Input + GSC_INIT_DATAREADY_IN => gsc_init_dataready, + GSC_INIT_DATA_IN => gsc_init_data, + GSC_INIT_PACKET_NUM_IN => gsc_init_packet_num, + GSC_INIT_READ_OUT => gsc_init_read, + GSC_REPLY_DATAREADY_OUT => gsc_reply_dataready, + GSC_REPLY_DATA_OUT => gsc_reply_data, + GSC_REPLY_PACKET_NUM_OUT => gsc_reply_packet_num, + GSC_REPLY_READ_IN => gsc_reply_read, + GSC_BUSY_OUT => gsc_busy, + + --status and control ports + HUB_STAT_CHANNEL => open, + HUB_STAT_GEN => open, + MPLEX_CTRL => (others => '0'), + MPLEX_STAT => open, + STAT_REGS => open, + STAT_CTRL_REGS => open, + + --Fixed status and control ports + STAT_DEBUG => open, + CTRL_DEBUG => (others => '0') + ); + + + gen_addition_ports : for i in 0 to cts_rdo_additional_ports-1 generate + cts_rdo_additional_data(31 + i*32 downto 32*i) <= cts_rdo_additional(i).data; + cts_rdo_trg_status_bits_additional(31 + i*32 downto 32*i) <= cts_rdo_additional(i).statusbits; + + cts_rdo_additional_write(i) <= cts_rdo_additional(i).data_write; + cts_rdo_additional_finished(i) <= cts_rdo_additional(i).data_finished; + + end generate; + + + rdack <= ctrlbus_tx.ack or ctrlbus_tx.rack; + wrack <= ctrlbus_tx.ack or ctrlbus_tx.wack; + + +--------------------------------------------------------------------------- +-- CTS +--------------------------------------------------------------------------- + THE_CTS : CTS + generic map ( + EXTERNAL_TRIGGER_ID => ETM_ID, -- fill in trigger logic enumeration id of external trigger logic + PLATTFORM => 5, --TRB5sc + OUTPUT_MULTIPLEXERS => CTS_OUTPUT_MULTIPLEXERS, + ADDON_GROUPS => 1, + ADDON_GROUP_UPPER => (0, others => 0) + ) + port map ( + CLK => clk_sys, + RESET => reset_i, + + TRIGGER_BUSY_OUT => trigger_busy_i, + TIME_REFERENCE_OUT => cts_trigger_out, + + ADDON_TRIGGERS_IN => cts_addon_triggers_in, + ADDON_GROUP_ACTIVITY_OUT => open, + ADDON_GROUP_SELECTED_OUT => open, + + EXT_TRIGGER_IN => '0', + EXT_STATUS_IN => (others => '0'), + EXT_CONTROL_OUT => open, + EXT_HEADER_BITS_IN => (others => '0'), + EXT_FORCE_TRIGGER_INFO_IN => (others => '0'), + + PERIPH_TRIGGER_IN => (others => '0'), + + OUTPUT_MULTIPLEXERS_OUT => cts_monitor_out, + + CTS_TRG_SEND_OUT => cts_trg_send, + CTS_TRG_TYPE_OUT => cts_trg_type, + CTS_TRG_NUMBER_OUT => cts_trg_number, + CTS_TRG_INFORMATION_OUT => cts_trg_information, + CTS_TRG_RND_CODE_OUT => cts_trg_code, + CTS_TRG_STATUS_BITS_IN => cts_trg_status_bits, + CTS_TRG_BUSY_IN => cts_trg_busy, + + CTS_IPU_SEND_OUT => cts_ipu_send, + CTS_IPU_TYPE_OUT => cts_ipu_type, + CTS_IPU_NUMBER_OUT => cts_ipu_number, + CTS_IPU_INFORMATION_OUT => cts_ipu_information, + CTS_IPU_RND_CODE_OUT => cts_ipu_code, + CTS_IPU_STATUS_BITS_IN => cts_ipu_status_bits, + CTS_IPU_BUSY_IN => cts_ipu_busy, + + CTS_REGIO_ADDR_IN => buscts_rx.addr, + CTS_REGIO_DATA_IN => buscts_rx.data, + CTS_REGIO_READ_ENABLE_IN => buscts_rx.read, + CTS_REGIO_WRITE_ENABLE_IN => buscts_rx.write, + CTS_REGIO_DATA_OUT => buscts_tx.data, + CTS_REGIO_DATAREADY_OUT => buscts_tx.rack, + CTS_REGIO_WRITE_ACK_OUT => buscts_tx.wack, + CTS_REGIO_UNKNOWN_ADDR_OUT => buscts_tx.unknown, + + LVL1_TRG_DATA_VALID_IN => cts_rdo_rx.data_valid, + LVL1_VALID_TIMING_TRG_IN => cts_rdo_rx.valid_timing_trg, + LVL1_VALID_NOTIMING_TRG_IN => cts_rdo_rx.valid_notiming_trg, + LVL1_INVALID_TRG_IN => cts_rdo_rx.invalid_trg, + + FEE_TRG_STATUSBITS_OUT => cts_rdo_trg_status_bits_cts, + FEE_DATA_OUT => cts_rdo_data, + FEE_DATA_WRITE_OUT => cts_rdo_write, + FEE_DATA_FINISHED_OUT => cts_rdo_finished + ); + + -- cts_addon_triggers_in(11 downto 4) <= HDR_IO(23 downto 16); + -- cts_addon_triggers_in( 3 downto 0) <= trigger_gen_outputs_i; + + buscts_tx.nack <= '0'; + buscts_tx.ack <= '0'; + +--------------------------------------------------------------------------- +-- Bus Handler +--------------------------------------------------------------------------- + THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record + generic map( + PORT_NUMBER => 7, + PORT_ADDRESSES => (0 => x"d000", 1 => x"a000", 2 => x"d300", 3 => x"9000", 4 => x"8100", 5 => x"8300", 6 => x"de00", others => x"0000"), + PORT_ADDR_MASK => (0 => 12, 1 => 11, 2 => 1, 3 => 12, 4 => 8, 5 => 8, 6 => 5, others => 0), + PORT_MASK_ENABLE => 1 + ) + port map( + CLK => clk_sys, + RESET => reset_i, + + REGIO_RX => ctrlbus_rx, + REGIO_TX => ctrlbus_tx, + + BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED + -- BUS_RX(1) => bussci_rx, --SCI Serdes + BUS_RX(1) => buscts_rx, + BUS_RX(2) => bustc_rx, --Clock switch + BUS_RX(3) => busmimosis_rx, + BUS_RX(4) => busgbeip_rx, + BUS_RX(5) => busgbereg_rx, + BUS_RX(6) => busi2c_rx, + + BUS_TX(0) => bustools_tx, + -- BUS_TX(1) => bussci_tx, + BUS_TX(1) => buscts_tx, + BUS_TX(2) => bustc_tx, + BUS_TX(3) => busmimosis_tx, + BUS_TX(4) => busgbeip_tx, + BUS_TX(5) => busgbereg_tx, + BUS_TX(6) => busi2c_tx, + STAT_DEBUG => open + ); + +--------------------------------------------------------------------------- +-- Control Tools +--------------------------------------------------------------------------- + THE_TOOLS : entity work.trb3sc_tools + generic map( + ADC_CMD_1 => x"2c3cb", + ADC_CMD_2 => x"1d5cb", + ADC_CMD_3 => x"1e3cb", + ADC_CMD_4 => x"2f5cb", + ADC_CMD_T => x"1F393", + NUM_COINCIDENCES => 4, + NUM_MULTIPLICITIES => 1 + ) + port map( + CLK => clk_sys, + RESET => reset_i, + + --Flash & Reload + FLASH_CS => flash_ncs_i, + FLASH_CLK => FLASH_SCLK, + FLASH_IN => FLASH_MISO, + FLASH_OUT => FLASH_MOSI, + PROGRAMN => PROGRAMN, + REBOOT_IN => common_ctrl_reg(15) or reboot_from_gbe, + --SPI + SPI_CS_OUT => spi_cs, + SPI_MOSI_OUT => spi_mosi, + SPI_MISO_IN => spi_miso, + SPI_CLK_OUT => spi_clk, + --Header + --HEADER_IO => open, + -- HEADER_IO(7) => HDR_IO(6), + -- HEADER_IO(8) => HDR_IO(7), + ADDITIONAL_REG => add_reg, + --ADC + ADC_CS => ADC_NCS, + ADC_MOSI => ADC_MOSI, + ADC_MISO => ADC_MISO, + ADC_CLK => ADC_SCLK, + --Trigger & Monitor + MONITOR_INPUTS(11 downto 0) => x"000", + MONITOR_INPUTS(15 downto 12) => x"0", + TRIG_GEN_INPUTS(11 downto 0) => x"000", + TRIG_GEN_INPUTS(15 downto 12) => x"0", + + TRIG_GEN_OUTPUTS(3 downto 0) => trigger_gen_outputs_i, + + --SED + SED_ERROR_OUT => sed_error_i, + --Slowcontrol + BUS_RX => bustools_rx, + BUS_TX => bustools_tx, + --Control master for default settings + BUS_MASTER_IN => bus_master_in, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + DEBUG_OUT => debug_tools + ); + + PIN(5) <= '0' when (add_reg(30) = '0') else 'Z'; + + + FLASH_HOLD <= '1'; + FLASH_WP <= '1'; + + +--------------------------------------------------------------------------- +-- I2C +--------------------------------------------------------------------------- + THE_I2C : entity work.i2c_slim2 + port map( + CLOCK => clk_40, + RESET => reset_i, + -- I2C command / setup + I2C_GO_IN => i2c_go, + ACTION_IN => i2c_reg_1(8), -- '0' -> write, '1' -> read + WORD_IN => i2c_reg_1(0), -- '0' -> byte, '1' -> word + DIRECT_IN => i2c_reg_1(4), -- don't send command + I2C_SPEED_IN => i2c_reg_0(5 downto 0), -- speed adjustment (to be defined) + I2C_ADDR_IN => i2c_reg_2(7 downto 0), -- I2C address byte (R/W bit is ignored) + I2C_CMD_IN => i2c_reg_2(15 downto 8), -- I2C command byte (sent after address byte) + I2C_DW_IN => i2c_reg_2(31 downto 16),-- data word for write command + I2C_DR_OUT => i2c_reg_4(15 downto 0), -- data word from read command + STATUS_OUT => i2c_reg_4(23 downto 16), + VALID_OUT => i2c_reg_4(31), + I2C_BUSY_OUT => i2c_reg_4(30), + I2C_DONE_OUT => i2c_reg_4(29), + -- I2C connections + SDA_IN => PIN(4), + SDA_OUT => mimosis_sda_drv, + SCL_IN => PIN(3), + SCL_OUT => mimosis_scl_drv, + -- Debug + BSM_OUT => i2c_reg_4(27 downto 24) + ); + +-- I2C signal open collector driver +-- PIN(4) <= '0' when (mimosis_sda_drv = '0') else 'Z'; +-- PIN(3) <= '0' when (mimosis_scl_drv = '0') else 'Z'; + + PIN(4) <= MIMOSIS_SDA; + PIN(3) <= MIMOSIS_SCL; + MIMOSIS_SDA <= '0' when (mimosis_sda_drv = '0') else 'Z'; + MIMOSIS_SCL <= '0' when (mimosis_scl_drv = '0') else 'Z'; + + H3(1) <= i2c_reg_5_40(0); --MIMOSIS_SYNC + PIN(1) <= i2c_reg_5_40(4); --MIMOSIS_START + PIN(2) <= i2c_reg_5_40(8); --MIMOSIS_RESET + + PROC_I2C_REGS : process + begin + wait until rising_edge(CLK_SYS); + busi2c_tx.ack <= '0'; + busi2c_tx.unknown <= '0'; + busi2c_tx.nack <= '0'; + busi2c_tx.data <= (others => '0'); + i2c_go_100 <= '0'; + + if busi2c_rx.write = '1' then + busi2c_tx.ack <= '1'; + if busi2c_rx.addr(3 downto 0) = x"0" then + i2c_reg_0 <= busi2c_rx.data; + elsif busi2c_rx.addr(3 downto 0) = x"1" then + i2c_reg_1 <= busi2c_rx.data; + elsif busi2c_rx.addr(3 downto 0) = x"2" then + i2c_reg_2 <= busi2c_rx.data; + elsif busi2c_rx.addr(3 downto 0) = x"3" then + i2c_go_100 <= busi2c_rx.data(0); + elsif busi2c_rx.addr(3 downto 0) = x"5" then + i2c_reg_5 <= busi2c_rx.data; + else + busi2c_tx.ack <= '0'; + busi2c_tx.unknown <= '1'; + end if; + elsif busi2c_rx.read = '1' then + busi2c_tx.ack <= '1'; + if busi2c_rx.addr(3 downto 0) = x"0" then + busi2c_tx.data <= i2c_reg_0; + elsif busi2c_rx.addr(3 downto 0) = x"1" then + busi2c_tx.data <= i2c_reg_1; + elsif busi2c_rx.addr(3 downto 0) = x"2" then + busi2c_tx.data <= i2c_reg_2; + elsif busi2c_rx.addr(3 downto 0) = x"3" then + busi2c_tx.data <= (others => '0'); + elsif busi2c_rx.addr(3 downto 0) = x"4" then + busi2c_tx.data <= i2c_reg_4; + elsif busi2c_rx.addr(3 downto 0) = x"5" then + busi2c_tx.data <= i2c_reg_5; + else + busi2c_tx.ack <= '0'; + busi2c_tx.unknown <= '1'; + + end if; + end if; + end process; + + THE_I2C_GO_SYNC : pulse_sync + port map( + CLK_A_IN => clk_sys, + RESET_A_IN => reset_i, + PULSE_A_IN => i2c_go_100, + CLK_B_IN => clk_40, + RESET_B_IN => reset_i, + PULSE_B_OUT => i2c_go + ); + + THE_MIMOSIS_SIGNAL_SYNC : signal_sync + generic map( + WIDTH => 32, + DEPTH => 2 + ) + port map( + RESET => reset_i, + CLK0 => clk_sys, + CLK1 => clk_40, + D_IN => i2c_reg_5, + D_OUT => i2c_reg_5_40 + ); + + + +--------------------------------------------------------------------------- +-- Input stage +--------------------------------------------------------------------------- + THE_MIMOSIS : entity work.MimosisInput + port map( + CLK => clk_160, + CLK_SYS => clk_sys, + RESET => reset_i, + + INPUT => inp_i, + + BUSRDO_RX => cts_rdo_rx, + BUSRDO_TX => cts_rdo_additional(0), + + BUS_RX => busmimosis_rx, + BUS_TX => busmimosis_tx + ); + +-- inp_i <= H2(3 downto 0) & H1(3 downto 0); + inp_i <= H2(3) & H1(3) & H2(2) & H1(2) & H2(1) & H1(1) & H2(0) & H1(0); + + +--------------------------------------------------------------------------- +-- LED +--------------------------------------------------------------------------- + LED_SFP_GREEN <= not (gbe_status(0) and gbe_status(1) and gbe_status(2)); --'0'; + LED_SFP_YELLOW <= gbe_status(8); + LED_SFP_RED <= not (gbe_status(3) or gbe_status(4)); --'0'; + + -- LED_SFP_GREEN <= not med2int(0).stat_op(9); + -- LED_SFP_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)); + -- LED_SFP_YELLOW <= not med2int(0).stat_op(8); + LED <= x"FF"; + LED_RJ_GREEN(1)<= not external_clock_lock or led_off; --on if external clock used + LED_RJ_GREEN(0)<= '1' when led_off = '1' else '0'; --on if SFP is used (next to SFP) + LED_RJ_RED(1) <= external_clock_lock or led_off; --on if internal clock used + LED_RJ_RED(0) <= '1'; --on if backplane is used (next to SFP) + LED_EXT_CLOCK <= IN_SELECT_EXT_CLOCK or led_off; --on if trigger/clock from RJ45 is used + + TEST(13 downto 1) <= (others => '0'); + TEST(14) <= flash_ncs_i; --for v1 boards + + FLASH_NCS <= flash_ncs_i; + +------------------------------------------------------------------------------- +-- No trigger/data endpoint included +------------------------------------------------------------------------------- +-- cts_rdo_additional(0).data_finished <= '1'; +-- cts_rdo_additional(0).data_write <= '0'; +-- cts_rdo_additional(0).busy_release <= '1'; + + +end architecture; -- 2.43.0