From bbd877639692af0edad1f0006fefc63c2545a03e Mon Sep 17 00:00:00 2001
From: hadeshyp <hadeshyp>
Date: Mon, 18 May 2009 16:53:36 +0000
Subject: [PATCH] initial 4

---
 design/tdc_interface_trb.vhd | 981 -----------------------------------
 mdc_oepb.prj                 |  22 +
 mdc_oepb.vhd                 | 420 +++++++--------
 3 files changed, 234 insertions(+), 1189 deletions(-)
 delete mode 100755 design/tdc_interface_trb.vhd

diff --git a/design/tdc_interface_trb.vhd b/design/tdc_interface_trb.vhd
deleted file mode 100755
index ddfbdb7..0000000
--- a/design/tdc_interface_trb.vhd
+++ /dev/null
@@ -1,981 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-use IEEE.NUMERIC_STD.all;
-library UNISIM;
-use UNISIM.VComponents.all;
-entity tdc_interface is
-  port (
-    CLK                               : in  std_logic;
-    TDC_CLK                           : in  std_logic;  -- for input clock should be
-                                        -- through clock buffer
-    RESET                             : in  std_logic;
-    TDC_DATA_IN                       : in  std_logic_vector (31 downto 0);
-    --data from TDC
-    START_TDC_READOUT                 : in  std_logic;
-    --signal from rpc_trb_v2_fpga - trigger has arrived,one pulse (40MHz long)
-    --or 100MHz long  - but make 25 ns from this !!!
-    A_TDC_READY                       : in  std_logic;
-    B_TDC_READY                       : in  std_logic;
-    C_TDC_READY                       : in  std_logic;
-    D_TDC_READY                       : in  std_logic;
-    A_TDC_ERROR     : in  std_logic;
-    B_TDC_ERROR     : in  std_logic;
-    C_TDC_ERROR     : in  std_logic;
-    D_TDC_ERROR     : in  std_logic;
-    A_TDC_POWERUP   : out std_logic;    --turn on TDC -should be one ?!
-    B_TDC_POWERUP   : out std_logic;
-    C_TDC_POWERUP   : out std_logic;
-    D_TDC_POWERUP   : out std_logic;
-    SEND_TDC_TOKEN                    : out std_logic;
-    RECEIVED_TDC_TOKEN                : in  std_logic;
-    GET_TDC_DATA                      : out std_logic;  --Signal to TDC chip
-    TO_MANY_TDC_DATA                  : in  std_logic;
---TDC state mechines had to cut data
---but this should be in FIFO entity and should goes to tdc_interface.vhd (
---to stop writing to fifo just finish read out)
---copyt to internal FIFO
-    TDC_READOUT_COMPLETED             : out std_logic;
-    LVL1_TAG                          : in  std_logic_vector(7 downto 0);
-    LVL1_CODE                         : in  std_logic_vector(3 downto 0);
-    LVL2_TAG                          : in  std_logic_vector(7 downto 0);
-    HOW_MANY_ADD_DATA                 : in  std_logic_vector(7 downto 0);
-    COUNTER_a                         : in  std_logic_vector(31 downto 0);
-    COUNTER_b                         : in  std_logic_vector(31 downto 0);
-    COUNTER_c                         : in  std_logic_vector(31 downto 0);
-    COUNTER_d                         : in  std_logic_vector(31 downto 0);
-    COUNTER_e                         : in  std_logic_vector(31 downto 0);
-    COUNTER_f                         : in  std_logic_vector(31 downto 0);
-    COUNTER_g                         : in  std_logic_vector(31 downto 0);
-    COUNTER_h                         : in  std_logic_vector(31 downto 0);
-    LVL2_TRIGGER                      : in  std_logic;--_vector(1 downto 0);
-    TDC_DATA_OUT                      : out std_logic_vector (31 downto 0);  --data to ETRAX (LVL2)
-    TDC_DATA_VALID                    : out std_logic;  -- The TDC_DATA_OUT can be written
-    ETRAX_IS_READY_TO_READ            : in  std_logic;
-    LVL1_BUSY                    : out std_logic;
-    LVL2_BUSY                   : out std_logic;
-    TDC_REGISTER_00                 : out std_logic_vector(31 downto 0);
-    TDC_REGISTER_01                 : out std_logic_vector(31 downto 0);
-    TDC_REGISTER_02                 : out std_logic_vector(31 downto 0);
-    TDC_REGISTER_03                 : out std_logic_vector(31 downto 0);
-    TDC_REGISTER_04                 : out std_logic_vector(31 downto 0);
-    TDC_REGISTER_05                 : in  std_logic_vector(31 downto 0);
-    BUNCH_RESET              : out std_logic;
-    EVENT_RESET              : out std_logic;
-    READ_ADRESS_END_UP       : out  std_logic;  --here
-    DELAY_TRIGGER            : in std_logic_vector(7 downto 0);
-    TDC_START                : out std_logic;
-    TRIGGER_WITHOUT_HADES    : in std_logic;
-    TRIGGER_WITH_GEN_EN      : in std_logic;
-    TRIGGER_WITH_GEN         : in std_logic;
-    FIFO_RESET_ERR           : out std_logic
-    );
-end tdc_interface;
-architecture tdc_interface of tdc_interface is
-  component edge_to_pulse
-    port (
-      clock                           : in  std_logic;
-      en_clk                          : in  std_logic;
-      signal_in                       : in  std_logic;
-      pulse                           : out std_logic);
-  end component;
-  component up_down_counter_16_bit
-    port (
-      QOUT                            : out std_logic_vector(15 downto 0);
-      UP                              : in  std_logic;
-      DOWN                            : in  std_logic;
-      CLK                             : in  std_logic;
-      CLR                             : in  std_logic
-      );
-    end component;
-    component BUFG
-      port(
-        O: out std_ulogic;
-        I: in std_ulogic
-        );
-    end component;
-    component simpleupcounter_8bit
-      port (
-        QOUT : out std_logic_vector(7 downto 0);
-        UP   : in  std_logic;
-        CLK  : in  std_logic;
-        CLR  : in  std_logic);
-    end component;
-  component lvl1_buffer
-    port (
-      din           : IN  std_logic_VECTOR(31 downto 0);
-      rd_clk        : IN  std_logic;
-      rd_en         : IN  std_logic;
-      rst           : IN  std_logic;
-      wr_clk        : IN  std_logic;
-      wr_en         : IN  std_logic;
-      dout          : OUT std_logic_VECTOR(31 downto 0);
-      empty         : OUT std_logic;
-      full          : OUT std_logic;
-      rd_data_count : OUT std_logic_VECTOR(9 downto 0));
-  end component;
-  component lvl1_fifo
-    port (
-      clk        : IN  std_logic;
-      din        : IN  std_logic_VECTOR(31 downto 0);
-      rd_en      : IN  std_logic;
-      rst        : IN  std_logic;
-      wr_en      : IN  std_logic;
-      data_count : OUT std_logic_VECTOR(13 downto 0);
-      dout       : OUT std_logic_VECTOR(31 downto 0);
-      empty      : OUT std_logic;
-      full       : OUT std_logic);
-  end component;
-  component fifo16kW_through--virtex_13kW_fifo
-    port (
-      din           : IN  std_logic_VECTOR(31 downto 0);
-      rd_clk        : IN  std_logic;
-      rd_en         : IN  std_logic;
-      rst           : IN  std_logic;
-      wr_clk        : IN  std_logic;
-      wr_en         : IN  std_logic;
-      almost_empty  : OUT std_logic;
-      almost_full   : OUT std_logic;
-      dout          : OUT std_logic_VECTOR(31 downto 0);
-      empty         : OUT std_logic;
-      full          : OUT std_logic;
-      rd_data_count : OUT std_logic_VECTOR(13 downto 0);
-      wr_data_count : OUT std_logic_VECTOR(13 downto 0));
-  end component;
-  signal tdc_ready                  : std_logic;
-  signal counter_a_i                : std_logic_vector(31 downto 0);
-  signal counter_b_i                : std_logic_vector(31 downto 0);
-  signal counter_c_i                : std_logic_vector(31 downto 0);
-  signal counter_d_i                : std_logic_vector(31 downto 0);
-  signal counter_e_i                : std_logic_vector(31 downto 0);
-  signal counter_f_i                : std_logic_vector(31 downto 0);
-  signal counter_g_i                : std_logic_vector(31 downto 0);
-  signal counter_h_i                : std_logic_vector(31 downto 0);
-  signal add_data_counter           : std_logic_vector(7 downto 0):=(others => '0');
-  signal add_data_pulse             : std_logic;
-  signal first_header               : std_logic_vector(31 downto 0):=(others => '0');
-  signal second_header              : std_logic_vector(31 downto 0):=(others => '0');
-  signal words_in_event             : std_logic_vector(15 downto 0):=(others => '0');
-  signal tdc_data_valid_i           : std_logic;
-  signal how_many_words_in_event : std_logic_vector(16 downto 0);
-  signal delay_up : std_logic;
-  signal delay_clr : std_logic;
-  signal delay_qout : std_logic_vector(7 downto 0);
-  signal lvl1_trigger_pulse_start : std_logic;
-  signal lvl1_trigger_pulse_delay : std_logic;
-  signal fifo_reset_err_i : std_logic;
-  type DELAY_FSM_TRIGG is
-    (IDLE ,DELAY_1,DELAY_2);
-  signal delay_fsm_currentstate, delay_fsm_nextstate: DELAY_FSM_TRIGG;
-  type LVL1_START_FSM is
-      (IDLE, SEND_LVL1_TRIGG_1, SEND_LVL1_TRIGG_2, SEND_LVL1_TRIGG_3, SEND_LVL1_TRIGG_4, WAIT_FOR_TOKEN, SAVE_ADD_DATA_1, SAVE_ADD_DATA_2, SAVE_ADD_DATA_3, SAVE_ADD_DATA_4, SEND_LVL2_TRIGG);
-  signal LVL1_START_fsm_currentstate, LVL1_START_fsm_nextstate : LVL1_START_FSM;
-  type LVL2_START_FSM is
-    (IDLE, READOUT_WORD1, READOUT_WORD2 ,READOUT_WORD3 ,SAVE_EVENT_SIZE ,SEND_DATA1, LAST_WORD);
-  signal LVL2_START_fsm_currentstate, LVL2_START_fsm_nextstate : LVL2_START_FSM;
-  signal lvl1_busy_i : std_logic;
-  signal lvl1_busy_ff : std_logic;
-  signal lvl1_memory_busy_i : std_logic;
-  signal lvl2_busy_i : std_logic;
-  signal lvl1_trigger_pulse : std_logic;
-  signal lvl1_tdc_trigg_i : std_logic;
-  signal lvl1_tdc_trigg_ff : std_logic;
-  
-  signal trigger_register_00_i : std_logic_vector(5 downto 0);
-  signal lvl2_busy_end_pulse : std_logic;
-  signal not_tdc_data_valid_i : std_logic;
-
-  signal not_tdc_clk : std_logic;
-  signal test_counter_0 : std_logic_vector(7 downto 0);
-  signal test_counter_1 : std_logic_vector(7 downto 0);
-  signal test_counter_2 : std_logic_vector(7 downto 0);
-  signal test_counter_3 : std_logic_vector(7 downto 0);
-  signal add_data_i : std_logic_vector(31 downto 0);
-  signal lvl1_fifo_out : std_logic_vector(31 downto 0);
-  signal lvl1_fifo_in : std_logic_vector(31 downto 0);
-  signal lvl1_fifo_counter : std_logic_vector(13 downto 0);
-  signal lvl1_fifo_empty : std_logic;
-  signal lvl1_fifo_full : std_logic;
-  signal lvl1_fifo_wr_en : std_logic;
-  signal lvl1_fifo_rd_en : std_logic;
-  signal lvl1_buffer_out : std_logic_vector(31 downto 0);
-  signal lvl1_buffer_in : std_logic_vector(31 downto 0);
-  signal lvl1_buffer_counter : std_logic_vector(13 downto 0);
-  signal lvl1_buffer_empty : std_logic;
-  signal lvl1_buffer_full : std_logic;
-  signal lvl1_buffer_wr_en : std_logic;
-  signal lvl1_buffer_rd_en : std_logic;
-  signal lvl1_or_lvl2_is_busy : std_logic;
-  signal trigger_with_gen_pulse : std_logic;
-  signal lvl1_tag_minus1 : std_logic_vector(7 downto 0);
-  signal lvl2_debug : std_logic_vector(2 downto 0);
-  signal tdc_start_i : std_logic;
-  signal lvl2_busy_start_pulse : std_logic;
-  
-  signal lvl1_tdc_trigg_i_fsm : std_logic;
-  signal lvl1_fifo_wr_en_fsm : std_logic;
-  signal lvl1_fifo_in_fsm : std_logic_vector(31 downto 0);
-  signal lvl1_buffer_rd_en_fsm : std_logic;
-  signal lvl1_busy_i_fsm : std_logic;
-  signal lvl1_fifo_rd_en_fsm : std_logic;
-  signal tdc_data_valid_i_fsm : std_logic;
-  signal lvl1_data_counter : std_logic_vector(15 downto 0):=(others => '0');
-  signal trigger_counter : std_logic_vector(7 downto 0);
-  signal lvl1_code_i : std_logic_vector(3 downto 0);
-  signal tdc_ready_a_i : std_logic;
-  signal tdc_ready_b_i : std_logic;
-  signal tdc_ready_c_i : std_logic;
-  signal tdc_ready_d_i : std_logic;
-  signal lvl1_fifo_rd_en_empty_pulse : std_logic;
-  signal lvl1_fifo_empty_not : std_logic;
-  signal lvl1_fifo_busy_counter : std_logic_vector(31 downto 0);
-  signal tdc_data_clocked : std_logic_vector(31 downto 0);
-begin
-   READ_ADRESS_END_UP <=   lvl2_busy_end_pulse;  --here
-   TDC_REGISTER : process (CLK, RESET)
-   begin 
-     if rising_edge(CLK) then 
-         TDC_REGISTER_00(0) <= A_TDC_ERROR;
-         TDC_REGISTER_00(1) <= B_TDC_ERROR;
-         TDC_REGISTER_00(2) <= C_TDC_ERROR;
-         TDC_REGISTER_00(3) <= D_TDC_ERROR;
-         TDC_REGISTER_00(13 downto 4) <= lvl1_fifo_counter(9 downto 0);
-         TDC_REGISTER_00(14) <= lvl1_busy_i;
-         TDC_REGISTER_00(15) <= lvl1_memory_busy_i;--lvl1_or_lvl2_is_busy;--lvl1_memory_busy_i;
-         TDC_REGISTER_00(30) <= lvl1_fifo_wr_en;
-         TDC_REGISTER_00(31) <= lvl2_busy_i;
-         TDC_REGISTER_00(29 downto 16) <= lvl1_fifo_busy_counter(13 downto 0);
-         TDC_REGISTER_01(26 downto 0) <=  lvl2_debug & trigger_register_00_i(5 downto 2) & "00" & trigger_register_00_i(1 downto 0)& how_many_words_in_event(15 downto 0);
-         TDC_REGISTER_01(27) <= lvl1_buffer_wr_en;
-         TDC_REGISTER_01(28) <= tdc_ready;
-         TDC_REGISTER_01(29) <= lvl1_buffer_rd_en;
-         TDC_REGISTER_01(30) <= lvl1_buffer_empty;
-         TDC_REGISTER_01(31) <= '0';
-         TDC_REGISTER_02(31 downto 0) <= lvl1_fifo_out;--LVL2_TAG(3 downto 0) & lvl1_buffer_out(27 downto 0);--lvl1_fifo_out;
---         TDC_REGISTER_02(31 downto 0) <= LVL2_TAG & lvl1_buffer_out(23 downto 0);--lvl1_fifo_out;
-     --    TDC_REGISTER_03(31 downto 0) <= lvl1_fifo_out;
-         TDC_REGISTER_03(31 downto 0) <= x"0"& LVL1_CODE & LVL1_TAG & x"0" & lvl1_code_i & lvl1_tag_minus1;
-         TDC_REGISTER_04(31 downto 0) <= test_counter_3 & test_counter_2 & test_counter_1 & test_counter_0;
-     end if;
-   end process TDC_REGISTER;
-   A_TDC_POWERUP  <=  '1';
-   B_TDC_POWERUP  <=  '1';
-   C_TDC_POWERUP  <=  '1';
-   D_TDC_POWERUP  <=  '1';
-
---    SYNCH_TDC_SIGNALS: process (TDC_CLK, RESET)
---     begin 
---       if rising_edge(TDC_CLK) then 
---         if RESET = '1' then
---           tdc_ready_a_i <= '0';
---           tdc_ready_b_i <= '0';
---           tdc_ready_c_i <= '0';
---           tdc_ready_d_i <= '0';
---           tdc_ready   <= '0';
---         else
---           tdc_ready_a_i <= A_TDC_READY;
---           tdc_ready_b_i <= B_TDC_READY;
---           tdc_ready_c_i <= C_TDC_READY;
---           tdc_ready_d_i <= D_TDC_READY;
---           tdc_ready   <= tdc_ready_a_i or tdc_ready_b_i or tdc_ready_c_i or tdc_ready_d_i;
---         end if;
---       end if;
---     end process SYNCH_TDC_SIGNALS;
-
-   tdc_ready       <= A_TDC_READY or B_TDC_READY or C_TDC_READY or D_TDC_READY;       
-
-   GET_TDC_DATA                 <= '1';
-   SEND_BUNCH_RESET: process (TDC_CLK, RESET)
-   begin
-     if rising_edge(TDC_CLK) then
-       if RESET = '1' then
-         BUNCH_RESET <= '1';
-         EVENT_RESET <= '1';
-       else
-         EVENT_RESET <= '0';
-         BUNCH_RESET <= RECEIVED_TDC_TOKEN; 
-       end if;
-     end if;
-   end process SEND_BUNCH_RESET;
-  -----------------------------------------------------------------------------
-  ----------------------------------------------------------------------------
-  -- LVL1 logic 
-  -----------------------------------------------------------------------------
-  -----------------------------------------------------------------------------
-REGISTER_DATA_IN: process (TDC_CLK, RESET)
-begin  -- process REGISTER_DATA_IN
-  if rising_edge(TDC_CLK) then  -- rising clock edge
-    if RESET = '1' then                   -- asynchronous reset (active low)
-
-      lvl1_buffer_in <= x"abababab";
-      lvl1_buffer_wr_en <= '0';
---      tdc_data_clocked <= x"abababab"
-    else
-      lvl1_buffer_in <= TDC_DATA_IN;
-      lvl1_buffer_wr_en <= tdc_ready;
---      tdc_data_clocked TDC_DATA_IN
-    end if;
-  end if;
-end process REGISTER_DATA_IN;
-    LVL1_BUFF: fifo16kW_through--virtex_13kW_fifo
-     port map (
-         din           => lvl1_buffer_in,--TDC_DATA_IN,
-         rd_clk        => CLK,
-         rd_en         => lvl1_buffer_rd_en,
-         rst           => RESET ,
-         wr_clk        => TDC_CLK,
-         wr_en         => lvl1_buffer_wr_en,
-         almost_empty  => open,--almost_empty_i,
-         almost_full   => open,--almost_full_i,
-         dout          => lvl1_buffer_out,
-         empty         => lvl1_buffer_empty,
-         full          => lvl1_buffer_full,
-         rd_data_count => lvl1_buffer_counter,
-         wr_data_count => open--wr_data_count_i
-         );
-   LVL2_BUFF: fifo16kW_through--virtex_13kW_fifo
-     port map (
-         din           => lvl1_fifo_in,
-         rd_clk        => CLK,
-         rd_en         => lvl1_fifo_rd_en,
-         rst           => RESET,
-         wr_clk        => CLK,
-         wr_en         => lvl1_fifo_wr_en,
-         almost_empty  => open,--almost_empty_i,
-         almost_full   => open,--almost_full_i,
-         dout          => lvl1_fifo_out,
-         empty         => lvl1_fifo_empty,
-         full          => lvl1_fifo_full,
-         rd_data_count => lvl1_fifo_counter,
-         wr_data_count => open--wr_data_count_i
-         );
- 
-   TDC_DATA_OUT <= lvl1_fifo_out;
-
-
---    LVL1_BUFF: lvl1_buffer
---      port map (
---          din           => TDC_DATA_IN,
---          rd_clk        => CLK,
---          rd_en         => lvl1_buffer_rd_en,
---          rst           => RESET,
---          wr_clk        => TDC_CLK,
---          wr_en         => lvl1_buffer_wr_en,
---          dout          => lvl1_buffer_out,
---          empty         => lvl1_buffer_empty,
---          full          => lvl1_buffer_full,
---          rd_data_count => lvl1_buffer_counter);
-
- 
---    LVL1_FIFO_LVL2: lvl1_fifo
---      port map (
---          clk        => CLK,
---          din        => lvl1_fifo_in,
---          rd_en      => lvl1_fifo_rd_en,
---          rst        => RESET,
---          wr_en      => lvl1_fifo_wr_en,
---          data_count => lvl1_fifo_counter,
---          dout       => lvl1_fifo_out,
---          empty      => lvl1_fifo_empty,
---          full       => lvl1_fifo_full);
-
-   START_TRIGGER_PULSER : edge_to_pulse
-     port map (
-       clock     => CLK,
-       en_clk    => '1',
-       signal_in => START_TDC_READOUT,
-       pulse     => lvl1_trigger_pulse);
---   lvl1_trigger_pulse <= START_TDC_READOUT;
-   
-   DELAY_COUNTER     : simpleupcounter_8bit
-     port map (
-       CLK       => CLK,
-       UP        => delay_up,
-       CLR       => delay_clr,
-       QOUT      => delay_qout
-       );
-   DELAY_FSM_CLOCK   : process (CLK, RESET)
-   begin 
-    if rising_edge(CLK) then
-      if RESET = '1' then
-        delay_fsm_currentstate   <= IDLE;
-      else
-        delay_fsm_currentstate   <= delay_fsm_nextstate;
-      end if;
-    end if;
-  end process DELAY_FSM_CLOCK;
-  -- purpose: delay trigger whitch is sending to TDC 
-  TO_DELAY_TRIGG : process (delay_fsm_currentstate,lvl1_trigger_pulse,delay_qout,DELAY_TRIGGER)
-  begin  
-    case (delay_fsm_currentstate) is
-      when IDLE    =>
-        trigger_register_00_i(1 downto 0) <= "01";
-        lvl1_trigger_pulse_delay <= '0';
-        delay_clr                <= '1';
-        delay_up                 <= '0';
-        if lvl1_trigger_pulse = '1' and DELAY_TRIGGER /= x"00" then
-          delay_fsm_nextstate    <= DELAY_1;
-        else
-          delay_fsm_nextstate    <= IDLE;
-        end if;
-      when DELAY_1 =>
-        trigger_register_00_i(1 downto 0)    <= "10";
-        lvl1_trigger_pulse_delay <= '0';
-        delay_clr                <= '0';
-        delay_up                 <= '1';
-        if delay_qout = DELAY_TRIGGER(7 downto 0) then
-          delay_fsm_nextstate    <= DELAY_2;
-        else
-          delay_fsm_nextstate    <= DELAY_1;
-        end if;
-      when DELAY_2 =>
-        trigger_register_00_i(1 downto 0)    <= "11";
-        lvl1_trigger_pulse_delay <= '1';
-        delay_clr                <= '1';
-        delay_up                 <= '0';
-        delay_fsm_nextstate      <= IDLE;
-      when others  =>
-        trigger_register_00_i(1 downto 0)    <= "00";
-        lvl1_trigger_pulse_delay <= '0';
-        delay_clr                <= '1';
-        delay_up                 <= '0';
-        delay_fsm_nextstate      <= IDLE;
-    end case;
-  end process TO_DELAY_TRIGG;
-  lvl1_trigger_pulse_start <= lvl1_trigger_pulse when DELAY_TRIGGER = x"00" else lvl1_trigger_pulse_delay;
-   LVL1_START         : process (CLK, RESET)
-  begin 
-    if rising_edge(CLK)  then 
-      if RESET = '1' then 
-        LVL1_START_fsm_currentstate <= IDLE;
-        lvl1_tdc_trigg_i  <= '0';
-      lvl1_fifo_wr_en <= '0';
-      lvl1_fifo_in <= lvl1_buffer_out;
-      lvl1_buffer_rd_en <= '0';
-      lvl1_busy_i <= '0';
-      lvl1_tdc_trigg_i         <= '0';
-      else 
-        LVL1_START_fsm_currentstate <= LVL1_START_fsm_nextstate;
-        lvl1_tdc_trigg_i  <= lvl1_tdc_trigg_i_fsm;
-      lvl1_fifo_wr_en <= lvl1_fifo_wr_en_fsm;
-      lvl1_fifo_in <= lvl1_fifo_in_fsm ;
-      lvl1_buffer_rd_en <= lvl1_buffer_rd_en_fsm;
-      lvl1_busy_i <= lvl1_busy_i_fsm;
-      lvl1_tdc_trigg_i         <= lvl1_tdc_trigg_i_fsm;
-      end if;
-    end if;
-  end process LVL1_START;
- 
-  TRIGGER_WITHOUT_HADES_PULSER : edge_to_pulse
-    port map (
-      clock     => CLK,
-      en_clk    => '1',
-      signal_in => TRIGGER_WITH_GEN,
-      pulse     => trigger_with_gen_pulse);
-  LVL1_START_FSM_PROC : process (LVL1_START_fsm_currentstate,RECEIVED_TDC_TOKEN, trigger_with_gen_pulse, lvl1_trigger_pulse_start, add_data_counter, lvl1_data_counter, lvl1_or_lvl2_is_busy, how_many_add_data, lvl1_code, lvl1_buffer_empty, trigger_with_gen_en, add_data_i, second_header, first_header, lvl1_buffer_out)
-  begin
-    lvl1_tdc_trigg_i_fsm  <= '0';
-    lvl1_fifo_wr_en_fsm <= '0';
-    lvl1_fifo_in_fsm <= lvl1_buffer_out;
-    lvl1_buffer_rd_en_fsm <= '0';
-    lvl1_busy_i_fsm <= '0';
-    lvl1_tdc_trigg_i_fsm         <= '0';
-    LVL1_START_fsm_nextstate   <= IDLE;
- 
-    case (LVL1_START_fsm_currentstate) is
-      when IDLE         =>
-        trigger_register_00_i(5 downto 2) <= x"1";
-        lvl1_fifo_wr_en_fsm <= '0';
-        lvl1_fifo_in_fsm <= first_header;
-        lvl1_buffer_rd_en_fsm <= '0';
-        lvl1_tdc_trigg_i_fsm         <= '0';
-        lvl1_busy_i_fsm <= '0';
-        if (lvl1_trigger_pulse_start = '1'and LVL1_CODE /= x"d") or (TRIGGER_WITH_GEN_EN ='1' and trigger_with_gen_pulse = '1' and lvl1_busy_i = '0' and lvl2_busy_i = '0') then
-          LVL1_START_fsm_nextstate <= SEND_LVL1_TRIGG_1;
-        else
-          LVL1_START_fsm_nextstate <= IDLE;
-        end if;
-        
-      when SEND_LVL1_TRIGG_1 =>       
-        trigger_register_00_i(5 downto 2) <= x"2";
-        lvl1_tdc_trigg_i_fsm         <= '1';  --start TDC readout
-        lvl1_fifo_wr_en_fsm <= '0';
-        lvl1_fifo_in_fsm <= first_header;
-        lvl1_buffer_rd_en_fsm <= '0';
-        lvl1_busy_i_fsm <= '1';
-        LVL1_START_fsm_nextstate   <= SEND_LVL1_TRIGG_2;
-
-      when SEND_LVL1_TRIGG_2 =>
-        trigger_register_00_i(5 downto 2) <= x"3";
-        lvl1_tdc_trigg_i_fsm         <= '1';
-        lvl1_fifo_wr_en_fsm <= '0';
-        lvl1_fifo_in_fsm <= first_header;
-        lvl1_buffer_rd_en_fsm <= '0';
-        lvl1_busy_i_fsm <= '1';
-        LVL1_START_fsm_nextstate   <= SEND_LVL1_TRIGG_3;
-      when SEND_LVL1_TRIGG_3 =>
-        trigger_register_00_i(5 downto 2) <= x"4";
-        lvl1_tdc_trigg_i_fsm         <= '1';
-        lvl1_fifo_wr_en_fsm <= '0';
-        lvl1_fifo_in_fsm <= first_header;
-        lvl1_buffer_rd_en_fsm <= '0';
-        lvl1_busy_i_fsm <= '1';
-        LVL1_START_fsm_nextstate   <= SEND_LVL1_TRIGG_4;
-      when SEND_LVL1_TRIGG_4 =>
-        trigger_register_00_i(5 downto 2) <= x"5";
-        lvl1_tdc_trigg_i_fsm         <= '0';
-        lvl1_fifo_wr_en_fsm <= '0';
-        lvl1_fifo_in_fsm <= first_header;
-        lvl1_buffer_rd_en_fsm <= '0';
-        lvl1_busy_i_fsm <= '1';
-        LVL1_START_fsm_nextstate   <= WAIT_FOR_TOKEN;
-      when WAIT_FOR_TOKEN =>
-        trigger_register_00_i(5 downto 2) <= x"6";
-        lvl1_tdc_trigg_i_fsm         <= '0';
-        lvl1_fifo_wr_en_fsm <= '0';
-        lvl1_fifo_in_fsm <= first_header;
-        lvl1_buffer_rd_en_fsm <= '0';
-        lvl1_busy_i_fsm <= '1';
-        if  RECEIVED_TDC_TOKEN = '1' then
-          LVL1_START_fsm_nextstate   <= SAVE_ADD_DATA_1;
-        else
-          LVL1_START_fsm_nextstate   <= WAIT_FOR_TOKEN;
-        end if;
---       when SET_SIGNALS => 
---         trigger_register_00_i(5 downto 2) <= x"7";
---         lvl1_tdc_trigg_i_fsm         <= '0';
---         lvl1_fifo_in_fsm <= first_header;
---         lvl1_fifo_wr_en_fsm <= '1';
---         lvl1_buffer_rd_en_fsm <= '0';
---         lvl1_busy_i_fsm <= '1';
---         LVL1_START_fsm_nextstate   <= SAVE_ADD_DATA_1;
-      when SAVE_ADD_DATA_1 =>
-        trigger_register_00_i(5 downto 2) <= x"7";
-        lvl1_tdc_trigg_i_fsm         <= '0';
-        lvl1_fifo_in_fsm <= first_header;
-        lvl1_fifo_wr_en_fsm <= '1';
-        lvl1_buffer_rd_en_fsm <= '0';
-        lvl1_busy_i_fsm <= '1';
-        LVL1_START_fsm_nextstate   <= SAVE_ADD_DATA_2;
-
-      when SAVE_ADD_DATA_2 =>
-        trigger_register_00_i(5 downto 2) <= x"8";
-        lvl1_tdc_trigg_i_fsm         <= '0';
-        lvl1_fifo_in_fsm <= second_header;
-        lvl1_fifo_wr_en_fsm <= '1';
-        lvl1_buffer_rd_en_fsm <= '1';
-        lvl1_busy_i_fsm <= '1';
-        if HOW_MANY_ADD_DATA = x"00" then
-          LVL1_START_fsm_nextstate   <= SAVE_ADD_DATA_4;
-        else
-          LVL1_START_fsm_nextstate   <= SAVE_ADD_DATA_3;
-        end if;
-
-        -----------------------------------------------------------------------
-        -- 
-        -----------------------------------------------------------------------
-      when SAVE_ADD_DATA_3 =>
-        trigger_register_00_i(5 downto 2) <= x"9";
-        lvl1_tdc_trigg_i_fsm   <= '0';
-        lvl1_fifo_in_fsm <= add_data_i;
-        lvl1_fifo_wr_en_fsm <= '1';
-        lvl1_buffer_rd_en_fsm <= '0';
-        lvl1_busy_i_fsm <= '1';
-        if add_data_counter = x"0f" then
-          LVL1_START_fsm_nextstate   <= SAVE_ADD_DATA_4;
-        else
-          LVL1_START_fsm_nextstate   <= SAVE_ADD_DATA_3;
-        end if;
-      when SAVE_ADD_DATA_4 =>
-        trigger_register_00_i(5 downto 2) <= x"a";
-        lvl1_tdc_trigg_i_fsm <= '0';
-        lvl1_fifo_wr_en_fsm <= '1';
-        lvl1_fifo_in_fsm <= lvl1_buffer_out;
-        lvl1_buffer_rd_en_fsm <= '1';
-        lvl1_busy_i_fsm <= '1';
---        if lvl1_buffer_empty = '1' then  --here !!! correct this !!!
-        if lvl1_data_counter = x"0000" then  
-          LVL1_START_fsm_nextstate   <= SEND_LVL2_TRIGG;
-        else
-          LVL1_START_fsm_nextstate   <= SAVE_ADD_DATA_4;
-        end if;
-      when SEND_LVL2_TRIGG  =>
-        trigger_register_00_i(5 downto 2) <= x"c";  
-        lvl1_tdc_trigg_i_fsm  <= '0';
-        lvl1_fifo_wr_en_fsm <= '0';
-        lvl1_fifo_in_fsm <= lvl1_buffer_out;
-        lvl1_buffer_rd_en_fsm <= '0';
-        lvl1_busy_i_fsm <= '1';
-        lvl1_tdc_trigg_i_fsm         <= '0';
-        LVL1_START_fsm_nextstate   <= IDLE;
-      when others =>
-        trigger_register_00_i(5 downto 2) <= x"d";  
-        lvl1_tdc_trigg_i_fsm  <= '0';
-        lvl1_fifo_wr_en_fsm <= '0';
-        lvl1_fifo_in_fsm <= lvl1_buffer_out;
-        lvl1_buffer_rd_en_fsm <= '0';
-        lvl1_busy_i_fsm <= '1';
-        lvl1_tdc_trigg_i_fsm         <= '0';
-        LVL1_START_fsm_nextstate   <= IDLE;
-       end case;
-  end process LVL1_START_FSM_PROC;
-  SAVE_NUMBER_OF_LVL1_WORDS: process (CLK, RESET)
-  begin 
-    if rising_edge(CLK) then
-      if RESET = '1' then     
-         lvl1_data_counter <= (others => '0');
-      elsif LVL1_START_fsm_currentstate = SAVE_ADD_DATA_2 then
-        lvl1_data_counter <= words_in_event - 3 - HOW_MANY_ADD_DATA;
-      elsif LVL1_START_fsm_currentstate = SAVE_ADD_DATA_4 and lvl1_data_counter > 0 then
-        lvl1_data_counter <= lvl1_data_counter - 1;
-      else
-        lvl1_data_counter <= lvl1_data_counter;
-      end if;
-    end if;
-  end process SAVE_NUMBER_OF_LVL1_WORDS;
---   not_tdc_clk <= TDC_CLK;
-   TDC_TRIGGER_PULSER : edge_to_pulse
-     port map (
-       clock     =>  TDC_CLK,
-       en_clk    => '1',
-       signal_in => lvl1_tdc_trigg_i,
-       pulse     => tdc_start_i);
-  TDC_START <= tdc_start_i;--lvl1_tdc_trigg_ff;--tdc_start_i;
-  SEND_TOKEN: process (TDC_CLK, RESET)
-  begin 
-    if rising_edge(TDC_CLK) then 
-      if RESET = '1' then         
-        SEND_TDC_TOKEN <= '0';
-      else
-        SEND_TDC_TOKEN <= tdc_start_i;
-      end if;
-    end if;
-  end process SEND_TOKEN;
-  SAVE_DATA : process (CLK, RESET,lvl1_tdc_trigg_i)
-  begin
-    if rising_edge(CLK) then
-      if RESET = '1' then
-        counter_a_i <= (others => '0');
-        counter_b_i <= (others => '0');
-        counter_c_i <= (others => '0');
-        counter_d_i <= (others => '0');
-        counter_e_i <= (others => '0');
-        counter_f_i <= (others => '0');
-        counter_g_i <= (others => '0');
-        counter_h_i <= (others => '0');
-      elsif lvl1_tdc_trigg_i = '1' then  
-        counter_a_i <= COUNTER_a;
-        counter_b_i <= COUNTER_b;
-        counter_c_i <= COUNTER_c;
-        counter_d_i <= COUNTER_d;
-        counter_e_i <= COUNTER_e;
-        counter_f_i <= COUNTER_f;
-        counter_g_i <= COUNTER_g;
-        counter_h_i <= COUNTER_h;
-      end if;
-    end if;
-  end process SAVE_DATA;
-   CHOOSE_DATA              : process (CLK, RESET, add_data_counter)
-  begin
-    if rising_edge(CLK) then
-      if RESET = '1' then
-        add_data_i <= x"00000000";
-      else
-        case add_data_counter(3 downto 0) is
-          when "0000" => add_data_i <= counter_a_i;
-          when "0001" => add_data_i <= counter_b_i;
-          when "0010" => add_data_i <= counter_c_i;
-          when "0011" => add_data_i <= counter_d_i;
-          when "0100" => add_data_i <= counter_e_i;
-          when "0101" => add_data_i <= counter_f_i;
-          when "0110" => add_data_i <= counter_g_i;
-          when "0111" => add_data_i <= counter_h_i;
-          when others  => add_data_i <= x"deadface";
-        end case;
-      end if;
-    end if;  
-  end process CHOOSE_DATA;
-  add_data_pulse <= '1' when SAVE_ADD_DATA_3 = LVL1_START_fsm_nextstate else '0';
-  not_tdc_clk <= TDC_CLK;
-  ADD_DATA_COUNTER_CONTROL : process (CLK,RESET,lvl1_tdc_trigg_i,add_data_pulse)
-  begin
-    if rising_edge(CLK) then
-      if RESET = '1' or lvl1_tdc_trigg_i = '1' then
-        add_data_counter <= x"1" & HOW_MANY_ADD_DATA(3 downto 0) - 1;
-      elsif add_data_pulse = '1' then
-        add_data_counter <= add_data_counter - 1;
-      end if;
-    end if;
-  end process ADD_DATA_COUNTER_CONTROL;
-   COUNT_WORDS_IN_EVENT : process (TDC_CLK, RESET, tdc_ready, lvl1_tdc_trigg_i)
-   begin
-     if rising_edge(TDC_CLK) then
-       if RESET = '1' or tdc_start_i = '1' then
-         words_in_event <= x"0002" + HOW_MANY_ADD_DATA;
-       elsif tdc_ready = '1' then
-         words_in_event <= words_in_event + 1;
-       end if;
-     end if;
-   end process COUNT_WORDS_IN_EVENT;
-   TRIGGER_COUNTER_PROC : process (CLK, RESET, LVL1_START_fsm_currentstate)
-   begin
-     if rising_edge(CLK) then 
-       if RESET = '1' then      
-         trigger_counter <= x"ff";
-       elsif LVL1_START_fsm_currentstate = SEND_LVL1_TRIGG_1 then
-         trigger_counter <= trigger_counter + 1;
-       else
-         trigger_counter <= trigger_counter;
-       end if;
-     end if;
-   end process TRIGGER_COUNTER_PROC;
- --  words_in_event <= x"0001" + HOW_MANY_ADD_DATA + 2 + lvl1_buffer_counter;
-   lvl1_tag_minus1 <= trigger_counter when TRIGGER_WITH_GEN_EN = '1' else LVL1_TAG - 1;
-   lvl1_code_i <= x"1" when  TRIGGER_WITH_GEN_EN = '1'else LVL1_CODE;
---   first_header  <= x"0" & LVL1_CODE & lvl1_tag_minus1 &  words_in_event;
---   second_header <= x"030000" & HOW_MANY_ADD_DATA;
-   first_header  <= x"0" & lvl1_code_i & lvl1_tag_minus1 &  words_in_event;
-   second_header <= TDC_REGISTER_05(15 downto 8) & x"0000" & HOW_MANY_ADD_DATA;
-  -----------------------------------------------------------------------------
-  ----------------------------------------------------------------------------
-  -- LVL2 logic (only CLK domain)
-  -----------------------------------------------------------------------------
-  -----------------------------------------------------------------------------
-   lvl1_fifo_empty_not <= not lvl1_fifo_empty;
-    FIFO_RD_PULSER : edge_to_pulse
-     port map (
-       clock     => CLK,
-       en_clk    => '1',
-       signal_in => lvl1_fifo_empty_not,
-       pulse     => lvl1_fifo_rd_en_empty_pulse);
-   LVL2_START         : process (CLK, RESET)
-   begin 
-     if rising_edge(CLK)  then 
-       if RESET = '1' then 
-         LVL2_START_fsm_currentstate <= IDLE;
-         lvl1_fifo_rd_en <= '0';
-         tdc_data_valid_i <= '0';
-       else
-         lvl1_fifo_rd_en <= lvl1_fifo_rd_en_fsm;
-         tdc_data_valid_i <= tdc_data_valid_i_fsm;
-         LVL2_START_fsm_currentstate <= LVL2_START_fsm_nextstate;
-       end if;
-     end if;
-   end process LVL2_START;
-   START_LVL2_FSM: process (LVL2_TRIGGER,LVL2_START_fsm_currentstate, LVL1_START_fsm_currentstate, how_many_words_in_event, lvl1_fifo_out, etrax_is_ready_to_read, lvl1_fifo_rd_en_empty_pulse)
-   begin
-     lvl2_busy_i <= '1';
-     lvl2_debug (2 downto 0) <= "000";
-     lvl1_fifo_rd_en_fsm <= '0';
-     tdc_data_valid_i_fsm <= '0';
-     LVL2_START_fsm_nextstate <= IDLE;
-     case (LVL2_START_fsm_currentstate) is
-       when IDLE =>
-         lvl2_busy_i <= '0';
-         lvl2_debug (2 downto 0) <= "001";
-         lvl1_fifo_rd_en_fsm <= '0';--lvl1_fifo_rd_en_empty_pulse;--'0';
-         tdc_data_valid_i_fsm <= '0';
---         if LVL1_START_fsm_currentstate = SEND_LVL2_TRIGG then
-         if LVL2_TRIGGER = '1' or (TRIGGER_WITH_GEN_EN ='1' and LVL1_START_fsm_currentstate = SEND_LVL2_TRIGG ) then
-             LVL2_START_fsm_nextstate <= SAVE_EVENT_SIZE;
-         else
-            LVL2_START_fsm_nextstate <= IDLE;
-         end if;
-         when  READOUT_WORD1 =>
-           lvl2_busy_i <= '1';
-           lvl2_debug (2 downto 0) <= "010";
-           lvl1_fifo_rd_en_fsm <= '0';
-           tdc_data_valid_i_fsm <= '0';
-          if lvl1_fifo_out(31 downto 24) /=  x"01" then
---          if lvl1_fifo_out(31 downto 28) = x"0"  then
-             LVL2_START_fsm_nextstate <= READOUT_WORD2;
-           else
-            LVL2_START_fsm_nextstate <= SAVE_EVENT_SIZE;
-          end if;
-
-       when  READOUT_WORD2 =>
-           lvl2_busy_i <= '1';
-           lvl2_debug (2 downto 0) <= "011";
-           lvl1_fifo_rd_en_fsm <= '1';
-           tdc_data_valid_i_fsm <= '0';
-           LVL2_START_fsm_nextstate <= READOUT_WORD3;
-           
-         when  READOUT_WORD3 =>
-           lvl2_busy_i <= '1';
-           lvl2_debug (2 downto 0) <= "011";
-           lvl1_fifo_rd_en_fsm <= '0';
-           tdc_data_valid_i_fsm <= '0';
-        if lvl1_fifo_out(31 downto 24) /=  x"01" then
-             LVL2_START_fsm_nextstate <= READOUT_WORD2;
-           else
-            LVL2_START_fsm_nextstate <= SAVE_EVENT_SIZE;
-          end if;
-
-       when SAVE_EVENT_SIZE =>
-         lvl2_busy_i <= '1';
-         lvl2_debug (2 downto 0) <= "100";
-         lvl1_fifo_rd_en_fsm <= '0';
-         tdc_data_valid_i_fsm <= '0';
-         LVL2_START_fsm_nextstate <= SEND_DATA1;
-         
-       when  SEND_DATA1 =>
-         lvl2_busy_i <= '1';
-         lvl2_debug (2 downto 0) <= "101";
-         lvl1_fifo_rd_en_fsm <= ETRAX_IS_READY_TO_READ;
-         tdc_data_valid_i_fsm <= '1';
---         if how_many_words_in_event(15 downto 0) = x"0000" then
-         if how_many_words_in_event(15 downto 0) = x"0000" then
-           LVL2_START_fsm_nextstate <= IDLE;
-         else
-           LVL2_START_fsm_nextstate <= SEND_DATA1;
-         end if;
-        when LAST_WORD =>
-         lvl2_busy_i <= '1';
-         lvl2_debug (2 downto 0) <= "110";
-         lvl1_fifo_rd_en_fsm <= '0';
-         tdc_data_valid_i_fsm <= '1';
-         if  ETRAX_IS_READY_TO_READ = '1' then
-           LVL2_START_fsm_nextstate <= IDLE;
-         else
-           LVL2_START_fsm_nextstate <= LAST_WORD;
-         end if;
-       
-       when others =>
-         lvl2_busy_i <= '1';
-         LVL2_START_fsm_nextstate <= IDLE;
-     end case;
-   end process START_LVL2_FSM;
-   COUNT_DOWN_READOUT: process (CLK, RESET,how_many_words_in_event)
-   begin
-     if rising_edge(CLK) then
-       if RESET = '1' then     
-         how_many_words_in_event <= (others => '0');
-       elsif LVL2_START_fsm_currentstate = SAVE_EVENT_SIZE then
-         how_many_words_in_event <= '1' & lvl1_fifo_out(15 downto 0);
-       elsif how_many_words_in_event > x"0ffff" and ETRAX_IS_READY_TO_READ = '1' then -- or READ_ADRESS_END_UP='1')then
-         how_many_words_in_event <= how_many_words_in_event - 1;
-       end if;
-     end if;
-   end process COUNT_DOWN_READOUT;
---   SYNCH_DATA_VALID: process (CLK, RESET)
---   begin  
---     if rising_edge(CLK) then --correct this !!!!!!!!!!!!!!!!(falling?)
---       if RESET = '1' then    
---         TDC_DATA_VALID <= '0';
---       else
---         TDC_DATA_VALID <= tdc_data_valid_i;
---       end if;
---     end if;
---   end process SYNCH_DATA_VALID;
-   TDC_DATA_VALID <= tdc_data_valid_i_fsm;  
-  not_tdc_data_valid_i <= not tdc_data_valid_i;
-  LVL2_BUSY_END_PULSER   : edge_to_pulse
-    port map (
-      clock     => CLK,
-      en_clk    => '1',
-      signal_in => not_tdc_data_valid_i,
-      pulse     => lvl2_busy_end_pulse);
---   LVL2_BUSY_SET: process (CLK, RESET)
---   begin 
---     if rising_edge(CLK) then 
---       if RESET = '1' or lvl2_busy_end_pulse = '1'then           
---         lvl2_busy_i <= '0';
---       elsif LVL2_START_fsm_currentstate  /= IDLE then
---         lvl2_busy_i <= '1';
---       end if;
---     end if;
---   end process LVL2_BUSY_SET;
-  LVL2_BUSY_START_PULSER   : edge_to_pulse
-    port map (
-      clock     => CLK,
-      en_clk    => '1',
-      signal_in => lvl2_busy_i,
-      pulse     => lvl2_busy_start_pulse); 
-
-                                        --set
-                                        --to
-                                        --max
-                                        --value
-                                        --!!!!!!! and cut data funktion should
-                                        --be implemented - with busy or max
-                                        --size or last event ? or both
-  LVL1_OR_LVL2_BUSY: process (CLK, RESET, lvl1_busy_i, lvl2_busy_end_pulse)
-  begin  
-    if rising_edge(CLK) then 
-      if RESET = '1' then    
-        lvl1_or_lvl2_is_busy <= '0';
-      elsif lvl1_busy_i = '1'  then
-        lvl1_or_lvl2_is_busy <= '1';
-      elsif lvl2_busy_end_pulse = '1' then  
-        lvl1_or_lvl2_is_busy <= '0';
-      end if;
-    end if;
-  end process LVL1_OR_LVL2_BUSY;
-
-  LVL2_BUSY <= lvl2_busy_i;
-  TDC_READOUT_COMPLETED <= lvl2_busy_end_pulse;
-  -----------------------------------------------------------------------------
-  -- end writing to fifo when TDC_LVL1_BUSY and read all data and send finish signal
-  -----------------------------------------------------------------------------
-  TEST_COUNTER_a     : simpleupcounter_8bit
-     port map (
-       CLK       => TDC_CLK,
-       UP        => tdc_start_i,
-       CLR       => RESET,
-       QOUT      => test_counter_0
-       );
-  TEST_COUNTER_b     : simpleupcounter_8bit
-     port map (
-       CLK       => TDC_CLK,
-       UP        => RECEIVED_TDC_TOKEN,
-       CLR       => RESET,
-       QOUT      => test_counter_1
-       );
-  TEST_COUNTER_c     : simpleupcounter_8bit
-     port map (
-       CLK       => CLK,
-       UP        => lvl2_busy_start_pulse,--lvl2_trigger_pulse,
-       CLR       => RESET,
-       QOUT      => test_counter_2
-       );
-  TEST_COUNTER_d     : simpleupcounter_8bit
-     port map (
-       CLK       => CLK,
-       UP        => lvl2_busy_end_pulse,
-       CLR       => RESET,
-       QOUT      => test_counter_3
-       );
-  SET_BUFFER_BUSY: process (CLK, RESET)
-  begin  -- process SET_BUFFER_BUSY
-    if rising_edge(CLK) then
-      if RESET = '1' or (test_counter_3 = test_counter_1 and lvl1_memory_busy_i = '1') then --or test_counter_3 = test_counter_1 then                 -- asynchronous reset (active low)
-        lvl1_fifo_busy_counter <= (others => '0');
-      elsif lvl1_fifo_rd_en = '1' and  lvl1_fifo_wr_en = '0' and lvl1_fifo_busy_counter > 0 then
-        lvl1_fifo_busy_counter <= lvl1_fifo_busy_counter -1;
-      elsif lvl1_fifo_rd_en = '0' and  lvl1_fifo_wr_en = '1' then
-        lvl1_fifo_busy_counter <= lvl1_fifo_busy_counter +1;
-      elsif lvl1_fifo_rd_en = '1' and  lvl1_fifo_wr_en = '1' then
-        lvl1_fifo_busy_counter <= lvl1_fifo_busy_counter;
-      else
-        lvl1_fifo_busy_counter <= lvl1_fifo_busy_counter;
-      end if;
-    end if;
-  end process SET_BUFFER_BUSY;
-   fifo_reset_err_i <= '1' when test_counter_3 = test_counter_1 and lvl1_memory_busy_i = '1' else '0';
-   --  lvl1_memory_busy_i <= '1' when lvl1_fifo_counter(13) = '1' else '0';
-   lvl1_memory_busy_i <= '1' when lvl1_fifo_busy_counter(13) = '1' and lvl1_fifo_busy_counter(12) = '1'else '0';   
-  REGITERING_SIGNALS: process (CLK, RESET)
-  begin 
-    if rising_edge(CLK) then  -- rising clock edge
-      if RESET = '1' then  
-        LVL1_BUSY <= '0';
-      else
-        LVL1_BUSY <= lvl1_busy_i or lvl1_memory_busy_i;--lvl1_or_lvl2_is_busy;--lvl1_busy_i or lvl1_memory_busy_i;--lvl1_or_lvl2_is_busy;--lvl1_busy_i;  --here
-      end if;
-    end if;
-  end process REGITERING_SIGNALS;
-end tdc_interface;
-
-
-
diff --git a/mdc_oepb.prj b/mdc_oepb.prj
index cde1dba..7149e73 100644
--- a/mdc_oepb.prj
+++ b/mdc_oepb.prj
@@ -45,7 +45,29 @@ add_file -vhdl -lib work "../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualpo
 add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_med_ecp_fot.vhd"
 add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd"
 add_file -vhdl -lib work "../trbnet/media_interfaces/ecp2m_fot/serdes_fot_0.vhd"
+
+add_file -vhdl -lib work "design/common_stop_generator.vhd"
+add_file -vhdl -lib work "design/counter_12bit.vhd"
+add_file -vhdl -lib work "design/counter_4bit.vhd"
+add_file -vhdl -lib work "design/counter_8bit.vhd"
+add_file -vhdl -lib work "design/edge_to_pulse.vhd"
+add_file -vhdl -lib work "design/fifo_8192depth_36width_dual_thresh.vhd"
+add_file -vhdl -lib work "design/fifo_fall_through_512depth_52width.vhd"
+add_file -vhdl -lib work "design/initialization_RAM.vhd"
+add_file -vhdl -lib work "design/load_mode_line.vhd"
+add_file -vhdl -lib work "design/load_ROC1_tdc_setup.vhd"
+add_file -vhdl -lib work "design/mdc_addon_daq_bus_0.vhd"
+add_file -vhdl -lib work "design/mode_line_multiplexer.vhd"
+add_file -vhdl -lib work "design/pulse_to_constant.vhd"
+add_file -vhdl -lib work "design/send_token_to_mb.vhd"
+add_file -vhdl -lib work "design/tdc_readout_and_trb_interface.vhd"
+add_file -vhdl -lib work "design/tdc_readout.vhd"
+add_file -vhdl -lib work "design/trigger_begrun_state.vhd"
+add_file -vhdl -lib work "design/trigger_distributor.vhd"
+add_file -vhdl -lib work "design/trigger_handle_tld.vhd"
+
 add_file -vhdl -lib work "version.vhd"
+add_file -vhdl -lib work "design/mdc_oepb_pack.vhd"
 add_file -vhdl -lib work "mdc_oepb.vhd"
 
 
diff --git a/mdc_oepb.vhd b/mdc_oepb.vhd
index f2b0a55..1a09428 100644
--- a/mdc_oepb.vhd
+++ b/mdc_oepb.vhd
@@ -4,6 +4,7 @@ USE IEEE.numeric_std.ALL;
 
 library work;
 use work.trb_net_std.all;
+use work.mdc_oepb_pack.all;
 use work.version.all;
 
 entity mdc_oepb is
@@ -29,215 +30,28 @@ entity mdc_oepb is
       ADC_SDI       : out std_logic;
       ADC_SDO       : in  std_logic;
       ADC_CONVST    : out std_logic;
-      --Debugging
-      TAD       : out std_logic_vector(8 downto 0);  --TAD 8 downto 0
-      LB        : out std_logic_vector(7 downto 0)  --REN, DRE, ENB, DRB, ENR, DRA, ADI1, ADI0
+      --MB
+      --MRES  : out   std_logic;                     --global reset
+      TAOD  : inout std_logic;             --address or data
+      TACK  : in    std_logic;             --MB address
+      CMS   : out   std_logic;             --common stop
+      TDST  : inout std_logic;             --data strobe
+      GDE   : out std_logic;                --global disable
+      RDYI  : out std_logic;              --ready TO first motherboard token out to MB (on AddOn RDM)
+      TRDYO : in  std_logic;              --ready FROM first motherboard token in (respect OEP old RDO)
+      TRSV  : in std_logic;             --this is 11 bit of dataword (on AddOn A_RESERV)
+      --mode lines
+      MODD  : out std_logic;               -- TDC working mode
+      RES   : out std_logic;               -- TDC working mode
+      TOK   : out std_logic;               -- TDC working mode
+      WRM   : out std_logic;                -- TDC working mode
+      TAD   : inout std_logic_vector(8 downto 0)  --TAD 8 downto 0
       );
 end entity;
 
 
 architecture mdc_oepb_arch of mdc_oepb is
 
-  component pll_in25_out100 is
-    port (
-      CLK: in std_logic;
-      CLKOP: out std_logic;
-      LOCK: out std_logic
-      );
-  end component;
-
-  component trb_net16_med_ecp_fot is
-    port(
-      CLK    : in std_logic;
-      CLK_25 : in std_logic;
-      CLK_EN : in std_logic;
-      RESET  : in std_logic;
-
-      --Internal Connection
-      MED_DATA_IN        : in  std_logic_vector(c_DATA_WIDTH-1 downto 0);
-      MED_PACKET_NUM_IN  : in  std_logic_vector(c_NUM_WIDTH-1 downto 0);
-      MED_DATAREADY_IN   : in  std_logic;
-      MED_READ_OUT       : out std_logic;
-      MED_DATA_OUT       : out std_logic_vector(c_DATA_WIDTH-1 downto 0);
-      MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);
-      MED_DATAREADY_OUT  : out std_logic;
-      MED_READ_IN        : in  std_logic;
-
-      --SFP Connection
-      TXP : out std_logic;
-      TXN : out std_logic;
-      RXP : in  std_logic;
-      RXN : in  std_logic;
-      SD  : in  std_logic;
-
-      -- Status and control port
-      STAT_OP            : out  std_logic_vector (15 downto 0);
-      CTRL_OP            : in  std_logic_vector (15 downto 0);
-      STAT_DEBUG         : out  std_logic_vector (63 downto 0);
-      CTRL_DEBUG         : in  std_logic_vector (63 downto 0)
-      );
-  end component;
-
-  component adc_ltc2308_readout is
-    generic(
-      CLOCK_FREQUENCY : integer := 100 --MHz
-      );
-    port(
-      CLK    : in std_logic;
-      RESET  : in std_logic;
-      CLK_EN : in std_logic;
-
-      ADC_SCK       : out std_logic;
-      ADC_SDI       : out std_logic;
-      ADC_SDO       : in  std_logic;
-      ADC_CONVST    : out std_logic;
-
-      DAT_ADDR_IN          : in  std_logic_vector(5 downto 0);
-      DAT_READ_EN_IN       : in  std_logic;
-      DAT_WRITE_EN_IN      : in  std_logic;
-      DAT_DATA_OUT         : out std_logic_vector(31 downto 0);
-      DAT_DATA_IN          : in  std_logic_vector(31 downto 0);
-      DAT_DATAREADY_OUT    : out std_logic;
-      DAT_NO_MORE_DATA_OUT : out std_logic;
-      DAT_WRITE_ACK_OUT    : out std_logic;
-      DAT_UNKNOWN_ADDR_OUT : out std_logic;
-      DAT_TIMEOUT_IN       : in  std_logic;
-
-      STAT_VOLTAGES_OUT    : out std_logic_vector(31 downto 0)
-      );
-  end component;
-
-  component trb_net16_endpoint_hades_full is
-    generic (
-      USE_CHANNEL                  : channel_config_t := (c_YES,c_YES,c_NO,c_YES);
-      IBUF_DEPTH                   : channel_config_t := (6,6,6,6);
-      FIFO_TO_INT_DEPTH            : channel_config_t := (6,6,6,6);
-      FIFO_TO_APL_DEPTH            : channel_config_t := (6,6,6,6);
-      IBUF_SECURE_MODE             : channel_config_t := (c_YES,c_YES,c_YES,c_YES);
-      API_SECURE_MODE_TO_APL       : channel_config_t := (c_YES,c_YES,c_YES,c_YES);
-      API_SECURE_MODE_TO_INT       : channel_config_t := (c_YES,c_YES,c_YES,c_YES);
-      OBUF_DATA_COUNT_WIDTH        : integer range 0 to 7 := std_DATA_COUNT_WIDTH;
-      INIT_CAN_SEND_DATA           : channel_config_t := (c_YES,c_YES,c_YES,c_NO);
-      REPLY_CAN_SEND_DATA          : channel_config_t := (c_YES,c_YES,c_YES,c_YES);
-      REPLY_CAN_RECEIVE_DATA       : channel_config_t := (c_YES,c_yES,c_yeS,c_NO);
-      USE_CHECKSUM                 : channel_config_t := (c_NO,c_YES,c_YES,c_YES);
-      APL_WRITE_ALL_WORDS          : channel_config_t := (c_NO,c_NO,c_NO,c_NO);
-      BROADCAST_BITMASK            : std_logic_vector(7 downto 0) := x"FF";
-      REGIO_NUM_STAT_REGS      : integer range 0 to 6 := 3; --log2 of number of status registers
-      REGIO_NUM_CTRL_REGS      : integer range 0 to 6 := 3; --log2 of number of ctrl registers
-      --standard values for output registers
-      REGIO_INIT_CTRL_REGS     : std_logic_vector(2**(3)*32-1 downto 0) := (others => '0');
-      --set to 0 for unused ctrl registers to save resources
-      REGIO_USED_CTRL_REGS     : std_logic_vector(2**(3)-1 downto 0)    := "00000001";
-      --set to 0 for each unused bit in a register
-      REGIO_USED_CTRL_BITMASK  : std_logic_vector(2**(3)*32-1 downto 0) := (others => '1');
-      REGIO_USE_DAT_PORT       : integer range 0 to 1 := c_YES;  --internal data port
-      REGIO_INIT_ADDRESS       : std_logic_vector(15 downto 0) := x"F100";
-      REGIO_INIT_UNIQUE_ID     : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876";
-      REGIO_INIT_BOARD_INFO    : std_logic_vector(31 downto 0) := x"1111_2222";
-      REGIO_INIT_ENDPOINT_ID   : std_logic_vector(15 downto 0) := x"0001";
-      REGIO_COMPILE_TIME       : std_logic_vector(31 downto 0) := x"00000000";
-      REGIO_COMPILE_VERSION    : std_logic_vector(15 downto 0) := x"0001";
-      REGIO_HARDWARE_VERSION   : std_logic_vector(31 downto 0) := x"12345678";
-      REGIO_USE_1WIRE_INTERFACE: integer := c_YES
-      );
-
-    port(
-      --  Misc
-      CLK    : in std_logic;
-      RESET  : in std_logic;
-      CLK_EN : in std_logic;
-
-      --  Media direction port
-      MED_DATAREADY_OUT  : out std_logic;
-      MED_DATA_OUT       : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
-      MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
-      MED_READ_IN        : in  std_logic;
-
-      MED_DATAREADY_IN   : in  std_logic;
-      MED_DATA_IN        : in  std_logic_vector (c_DATA_WIDTH-1 downto 0);
-      MED_PACKET_NUM_IN  : in  std_logic_vector (c_NUM_WIDTH-1 downto 0);
-      MED_READ_OUT       : out std_logic;
-
-      MED_STAT_OP_IN     : in  std_logic_vector(15 downto 0);
-      MED_CTRL_OP_OUT    : out std_logic_vector(15 downto 0);
-
-      -- LVL1 trigger APL
-      LVL1_TRG_TYPE_OUT      : out std_logic_vector(3 downto 0);
-      LVL1_TRG_RECEIVED_OUT  : out std_logic;
-      LVL1_TRG_NUMBER_OUT    : out std_logic_vector(15 downto 0);
-      LVL1_TRG_CODE_OUT      : out std_logic_vector(7 downto 0);
-      LVL1_TRG_INFORMATION_OUT : out std_logic_vector(7 downto 0);
-      LVL1_ERROR_PATTERN_IN  : in  std_logic_vector(31 downto 0) := x"00000000";
-      LVL1_TRG_RELEASE_IN    : in  std_logic := '0';
-
-
-      --Data Port
-      IPU_NUMBER_OUT       : out std_logic_vector (15 downto 0);
-      IPU_INFORMATION_OUT  : out std_logic_vector (7 downto 0);
-      --start strobe
-      IPU_START_READOUT_OUT: out std_logic;
-      --detector data, equipped with DHDR
-      IPU_DATA_IN          : in  std_logic_vector (31 downto 0);
-      IPU_DATAREADY_IN     : in  std_logic;
-      --no more data, end transfer, send TRM
-      IPU_READOUT_FINISHED_IN : in  std_logic;
-      --will be low every second cycle due to 32bit -> 16bit conversion
-      IPU_READ_OUT         : out std_logic;
-      IPU_LENGTH_IN        : in  std_logic_vector (15 downto 0);
-      IPU_ERROR_PATTERN_IN : in  std_logic_vector (31 downto 0);
-      -- Slow Control Data Port
-      REGIO_COMMON_STAT_REG_IN  : in  std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
-      REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0);
-      REGIO_REGISTERS_IN        : in  std_logic_vector(32*2**(REGIO_NUM_STAT_REGS)-1 downto 0) := (others => '0');
-      REGIO_REGISTERS_OUT       : out std_logic_vector(32*2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
-      --following ports only used when using internal data port
-      REGIO_ADDR_OUT            : out std_logic_vector(16-1 downto 0);
-      REGIO_READ_ENABLE_OUT     : out std_logic;
-      REGIO_WRITE_ENABLE_OUT    : out std_logic;
-      REGIO_DATA_OUT            : out std_logic_vector(32-1 downto 0);
-      REGIO_DATA_IN             : in  std_logic_vector(32-1 downto 0) := (others => '0');
-      REGIO_DATAREADY_IN        : in  std_logic := '0';
-      REGIO_NO_MORE_DATA_IN     : in  std_logic := '0';
-      REGIO_WRITE_ACK_IN        : in  std_logic := '0';
-      REGIO_UNKNOWN_ADDR_IN     : in  std_logic := '0';
-      REGIO_TIMEOUT_OUT         : out std_logic;
-      --IDRAM is used if no 1-wire interface, onewire used otherwise
-      REGIO_IDRAM_DATA_IN       : in  std_logic_vector(15 downto 0) := (others => '0');
-      REGIO_IDRAM_DATA_OUT      : out std_logic_vector(15 downto 0);
-      REGIO_IDRAM_ADDR_IN       : in  std_logic_vector(2 downto 0) := "000";
-      REGIO_IDRAM_WR_IN         : in  std_logic := '0';
-      REGIO_ONEWIRE_INOUT       : inout std_logic;
-      REGIO_ONEWIRE_MONITOR_IN  : in  std_logic;
-      REGIO_ONEWIRE_MONITOR_OUT : out std_logic;
-
-      STAT_DEBUG_IPU            : out std_logic_vector (31 downto 0);
-      STAT_DEBUG_1              : out std_logic_vector (31 downto 0);
-      STAT_DEBUG_2              : out std_logic_vector (31 downto 0);
-      MED_STAT_OP               : out std_logic_vector (15 downto 0);
-      CTRL_MPLEX                : in  std_logic_vector (31 downto 0);
-      IOBUF_CTRL_GEN            : in  std_logic_vector (4*32-1 downto 0);
-      STAT_ONEWIRE              : out std_logic_vector (31 downto 0);
-      STAT_ADDR_DEBUG           : out std_logic_vector (15 downto 0)
-      );
-  end component;
-
-  component ram_dp is
-    generic(
-      depth : integer := 3;
-      width : integer := 16
-      );
-    port(
-      CLK   : in  std_logic;
-      wr1   : in  std_logic;
-      a1    : in  std_logic_vector(depth-1 downto 0);
-      dout1 : out std_logic_vector(width-1 downto 0);
-      din1  : in  std_logic_vector(width-1 downto 0);
-      a2    : in  std_logic_vector(depth-1 downto 0);
-      dout2 : out std_logic_vector(width-1 downto 0)
-      );
-  end component;
-
   signal CLK_100        : std_logic;
   signal pll_locked     : std_logic;
   signal test_counter   : unsigned(25 downto 0);
@@ -315,6 +129,17 @@ architecture mdc_oepb_arch of mdc_oepb is
   signal thresh_mem_read : std_logic;
   signal thresh_mem_addr : std_logic_vector(6 downto 0);
 
+  signal token_to_mux_out_i : std_logic;
+  signal init_all_buses_i   : std_logic_vector(3 downto 0);
+  signal roc1_written_i     : std_logic;
+  signal a_add_configuration_i : std_logic_vector(8 downto 0);
+  signal a_add_data_i          : std_logic_vector(8 downto 0);
+  signal a_dst_configuration_i : std_logic;
+  signal a_aod_configuration_i : std_logic;
+  signal a_dst_data_i       : std_logic;
+  signal a_aod_data_i       : std_logic;
+  signal pulse_trdyo_i      : std_logic;
+  signal debug_trigger_distributor_i : std_logic_vector(31 downto 0);
 
 begin
 ---------------------------------------------------------------------
@@ -440,8 +265,8 @@ begin
 ---------------------------------------------------------------------
 -- LVL1 handler
 ---------------------------------------------------------------------
-  LVL1_ERROR_PATTERN_IN   <= (others => '0');
-  LVL1_TRG_RELEASE_IN     <= '1';
+--   LVL1_ERROR_PATTERN_IN   <= (others => '0');
+--   LVL1_TRG_RELEASE_IN     <= '1';
 
 ---------------------------------------------------------------------
 -- IPU Data channel handler
@@ -642,13 +467,192 @@ THE_ADDRESS_DEC_REG_PROC: process( CLK_100 )
       CTRL_DEBUG    => MED_CTRL_DEBUG
       );
 
+---------------------------------------------------------------------
+-- Transport trigger to FEE
+---------------------------------------------------------------------
+ THE_TRIG_DISTR : trigger_distributor
+    port map (
+        CLK                => CLK_100,
+        RESET              => reset,
+        INTERNAL_RESET_IN  => '0',
+        A_RDO_IN           => token_to_mux_out_i,
+        TRIGGER_IN         => LVL1_TRG_RECEIVED_OUT,
+        TRIGGER_TYPE_IN    => '0',
+        INIT_ALL_BUSES_OUT => init_all_buses_i,
+        ROC1_WRITTEN_IN    => roc1_written_i,
+        TOKEN_TO_TRB_OUT   => open,
+        CAL_TRIGGER_REGISTER_IN => (others => '0'),
+        DEBUG_REGISTER_OUT => debug_trigger_distributor_i,
+        LED_CNT_1_OUT      => open,--D(4),
+        LED_CNT_2_OUT      => open,--D(2),
+        LED_ERROR_OUT      => open,
+        LED_GOOD_OUT       => open
+        );
+
+---------------------------------------------------------------------
+-- FEE Readout
+---------------------------------------------------------------------
+  THE_MDC_OEP_READOUT : mdc_addon_daq_bus_0
+    --generic map (bus_number => bus_number)
+    port map (
+      CLK                          => CLK_100,
+      --A_ADD                        => tad_data_i,--TAD,
+      RESET                        => reset,
+      A_ADS_0                      => '0',
+      A_ADS_1                      => '0',
+      A_ADS_2                      => '0',
+      --A_AOD                        => aod_i,--TAOD,
+      A_ACK                        => TACK,
+      A_CMS                        => CMS,
+      --A_DST                        => dst_i,--TDST,
+      A_RDM                        => RDYI,  --out
+      A_GDE                        => GDE,
+      A_RDO                        => TRDYO,--in
+      A_RESERV                     => TRSV,
+      A_DRA                        => open,
+      A_DRB_1                      => open,
+      A_DRB_2                      => open,
+      A_DRE                        => open,
+      A_ENB_1                      => open,
+      A_ENB_2                      => open,
+      A_ENR_1                      => open,
+      A_ENR_2                      => open,
+      A_FET_ENABLE                 => open,
+      A_REN                        => open,
+      A_MOD                        => MODD,
+      A_RES                        => RES,
+      A_TOK                        => TOK,
+      A_WRM                        => WRM,
+      TOKEN_TO_MUX_OUT             => token_to_mux_out_i,
+      TRIGGER_TYPE_IN              => init_all_buses_i,
+      LA                           => open,
+      D                            => open,
+      A_RDO_OUT                    => open,
+      ROC1_WRITTEN_OUT             => roc1_written_i,
+      BUS_NUMBER_IN                => x"1",
+      BUS_CHAIN_IN                 => x"1",
+
+      ACKNOWLEDGE_TRB_INTERFACE_IN => x"1",
+      INIT_TRB_INTERFACE_OUT       => open,
+      DATA_OUT                     => open,
+      READ_FIFO_IN                 => '0',
+      DEBUG_REGISTER_TRB_INTERFACE => (others => '0'),
+
+      RAM_ADDRESS_IN               => (others => '0'),
+      RAM_DATA_IN                  => (others => '0'),
+      RAM_DATA_OUT                 => open,
+      RAM_READ_ENABLE_IN           => '0',
+      RAM_WRITE_ENABLE_IN          => '0',
+
+      A_ADD_CONFIGURATION_OUT => a_add_configuration_i,
+      A_DST_CONFIGURATION_OUT => a_dst_configuration_i,
+      A_AOD_CONFIGURATION_OUT => a_aod_configuration_i,
+
+      A_ADD_DATA_IN => a_add_data_i,
+      A_DST_DATA_IN => a_dst_data_i,
+      A_AOD_DATA_IN => a_aod_data_i,
+
+      DEBUG_REGISTER_0_BUS_0       => open,
+      DEBUG_REGISTER_1_BUS_0       => open,
+      DEBUG_REGISTER_2_BUS_0       => open,
+      DEBUG_REGISTER_3_BUS_0       => open,
+      DEBUG_REGISTER_4_BUS_0       => open,
+      DEBUG_REGISTER_5_BUS_0       => open,
+      DEBUG_REGISTER_6_BUS_0       => open,
+      DEBUG_REGISTER_7_BUS_0       => open,
+
+      LVL1_TRG_TYPE_IN     => LVL1_TRG_TYPE_OUT,
+      LVL1_TRG_RECEIVED_IN => LVL1_TRG_RECEIVED_OUT,
+      LVL1_TRG_NUMBER_IN   => LVL1_TRG_NUMBER_OUT,
+      LVL1_TRG_CODE_IN     => LVL1_TRG_CODE_OUT,
+      LVL1_TRG_INFORMATION_IN => LVL1_TRG_INFORMATION_OUT,
+      LVL1_ERROR_PATTERN_OUT => LVL1_ERROR_PATTERN_IN,
+      LVL1_TRG_RELEASE_OUT  => LVL1_TRG_RELEASE_IN,
+
+      --Data Port
+      IPU_NUMBER_IN        => IPU_NUMBER_OUT,
+      IPU_INFORMATION_IN   => IPU_INFORMATION_OUT,
+      --start strobe
+      IPU_START_READOUT_IN => IPU_START_READOUT_OUT,
+      --detector data, equipped with DHDR
+--       IPU_DATA_OUT         => IPU_DATA_IN,
+--       IPU_DATAREADY_OUT    => IPU_DATAREADY_IN,
+--       --no more data, end transfer, send TRM
+--       IPU_READOUT_FINISHED_OUT => IPU_READOUT_FINISHED_IN,
+--       --will be low every second cycle due to 32bit -> 16bit conversion
+--       IPU_LENGTH_OUT       => IPU_LENGTH_IN,
+--       IPU_ERROR_PATTERN_OUT=> IPU_ERROR_PATTERN_IN.
+      IPU_READ_IN          => IPU_READ_OUT
+      );
+
+-------------------------------------------------------------------------------
+-- DATA MULTIPLEXER for INOUT DST, AOD,TAD
+-------------------------------------------------------------------------------
+  process(debug_trigger_distributor_i(3 downto 0),TAD,TAOD, TDST,
+         a_add_configuration_i, a_aod_configuration_i,a_dst_configuration_i)
+    begin
+    --DATA TACKING
+      if (debug_trigger_distributor_i(3 downto 0) = x"1" or
+          debug_trigger_distributor_i(3 downto 0) = x"2" or
+          debug_trigger_distributor_i(3 downto 0) = x"3" or
+          debug_trigger_distributor_i(3 downto 0) = x"4") then
+
+        a_add_data_i <= TAD;
+        a_aod_data_i <= TAOD;
+        a_dst_data_i <= TDST;
+        TAOD <= 'Z';
+        TDST <= 'Z';
+        TAD <= (others => 'Z');
+    --     D(3) <= (a_add_data_i(0) and a_add_data_i(1) and
+    --             a_add_data_i(2) and a_add_data_i(3) and
+    --             a_add_data_i(4) and a_add_data_i(5) and
+    --             a_add_data_i(6) and a_add_data_i(7) and
+    --             a_add_data_i(8));
+    -------------------------------------------------------------------------------
+    -- -
+    -------------------------------------------------------------------------------
+      elsif(debug_trigger_distributor_i(3 downto 0) = x"5" or
+            debug_trigger_distributor_i(3 downto 0) = x"6" or
+            debug_trigger_distributor_i(3 downto 0) = x"7") then
+
+    --CONFIGURATION
+        TAOD <= a_aod_configuration_i;
+        TDST <= a_dst_configuration_i;
+        TAD <= a_add_configuration_i;
+
+        a_add_data_i <= (others => '0');
+        a_aod_data_i <= '0';
+        a_dst_data_i <= '0';
+    --    D(3) <= '0';
+    -------------------------------------------------------------------------------
+    -- -
+    -------------------------------------------------------------------------------
+
+      else
+    --DATA TACKING
+        a_add_data_i <= TAD;
+        a_aod_data_i <= TAOD;
+        a_dst_data_i <= TDST;
+        TAOD <= 'Z';
+        TDST <= 'Z';
+        TAD <= (others => 'Z');
+    --     D(3) <= (a_add_data_i(0) and a_add_data_i(1) and
+    --              a_add_data_i(2) and a_add_data_i(3) and
+    --              a_add_data_i(4) and a_add_data_i(5) and
+    --              a_add_data_i(6) and a_add_data_i(7) and
+    --              a_add_data_i(8));
+      end if;
+    end process;
+
+
+
 ---------------------------------------------------------------------
 -- Outputs     to Logic Analyzer
 ---------------------------------------------------------------------
 --   TAD(7 downto 0) <= med_dataready_in & MED_PACKET_NUM_IN & med_data_in(3 downto 0);
-   TAD(7 downto 0) <= MED_STAT_DEBUG(48 downto 41);
-   TAD(8) <= CLK;
-   LB(7 downto 0) <= MED_STAT_DEBUG(40) & MED_STAT_DEBUG(38 downto 32);
+--    TAD(7 downto 0) <= MED_STAT_DEBUG(48 downto 41);
+--    TAD(8) <= CLK;
+--    LB(7 downto 0) <= MED_STAT_DEBUG(40) & MED_STAT_DEBUG(38 downto 32);
 
 
 
-- 
2.43.0