From bc4c78f86ed4cd9d75a96e000db54418bcd59e5c Mon Sep 17 00:00:00 2001
From: hades <hades>
Date: Tue, 9 May 2000 12:33:44 +0000
Subject: [PATCH] *** empty log message ***

---
 hadaq/makeenv    |  10 +++++
 hadaq/param.tcl  |   1 +
 hadaq/tof_defs.h | 112 +++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 123 insertions(+)
 create mode 100644 hadaq/tof_defs.h

diff --git a/hadaq/makeenv b/hadaq/makeenv
index 7f3d47b..c90ba28 100644
--- a/hadaq/makeenv
+++ b/hadaq/makeenv
@@ -36,6 +36,13 @@ then
 	export LOADLIBES="-L$HOME/lib/$SYSTYPE -lhadesstd -llatm -llvme -ltk -L/usr/X11R6/lib -lX11 -ltcl -lm -ldl"
 	export INCLUDES="-I$HOME/include"
 	export DEFINES="-UNDEBUG -DHADESSTD_NEXITSTAT -DHADESSTD_NGETOPT -DNOATM"
+elif test $HADAQ_CONF = "LINUX_E128"
+then
+	export CC="gcc"
+	export RPCGEN="rpcgen"
+	export LOADLIBES="-L$HOME/lib/$SYSTYPE -lhadesstd -llatm -llvme"
+	export INCLUDES="-I$HOME/include"
+	export DEFINES="-UNDEBUG -DLVME_SOFTSWAP -DHADESSTD_NEXITSTAT -DHADESSTD_NGETOPT -DNOATM"
 elif test $HADAQ_CONF = "LYNXOS"
 then
 	export CC="gcc"
@@ -58,6 +65,9 @@ then
 elif test $HW_CONF = "SEB"
 then
 	export HW_OBJS="hwtof.o hwv775.o hwv878.o hwv488.o hwdtu.o hwsis3801.o"
+elif test $HW_CONF = "TOF"
+then
+	export HW_OBJS="hwtof.o hwtip.o"
 elif test $HW_CONF = "RICH"
 then
 	export HW_OBJS="hwrich.o hwrace.o rc.o"
diff --git a/hadaq/param.tcl b/hadaq/param.tcl
index 6998f06..1c2d209 100644
--- a/hadaq/param.tcl
+++ b/hadaq/param.tcl
@@ -1,6 +1,7 @@
 set soft(size) 1024
 
 set dtu(cardbase) 0x44500000
+set tip0(cardbase) 0x10000000
 
 set tdc0(cardbase) 0x22000000
 set tdc0(threshold00) 0
diff --git a/hadaq/tof_defs.h b/hadaq/tof_defs.h
new file mode 100644
index 0000000..88d7d28
--- /dev/null
+++ b/hadaq/tof_defs.h
@@ -0,0 +1,112 @@
+/****	Headerfile for TOF-RTU registers */
+/****	E.Lins 13-Jan-2000 */
+
+
+/* Onboard components base addresses... */
+
+#define MEMBASE		0x01000000
+
+#define SCV64BASE	0x01400000
+#define DISPBASE	0x01500000
+#define STATUSBASE	0x01600000
+
+#define SHARC1BASE	0x00000000
+#define SHARC2BASE	0x00200000
+#define SHARC3BASE	0x00400000
+#define SHARC4BASE	0x00600000
+#define SHARC5BASE	0x00800000
+#define SHARC6BASE	0x00a00000
+
+
+/* registers in external memory */
+
+#define EXT_DAQ         0x010fffe0
+#define EXT_STATUS      0x010ffff0
+#define EXT_MISC1       0x010ffff4
+#define EXT_MISC2       0x010ffff8
+
+/* define some bits of the internal status register       */
+
+#define LVL1_PIPE_FULL     0x00000001U
+#define LVL2_PIPE1_FULL    0x00000002U
+#define LVL2_PIPE2_FULL    0x00000004U
+#define LVL2_PIPE          0x00000008U
+
+#define LVL1_BUSY          0x00000010U
+#define LVL2_BUSY          0x00000020U
+
+#define LVL2_DAQ1_BSY      0x00000100U
+#define LVL2_DAQ2_BSY      0x00000200U
+
+/* bits in the daq register */
+
+#define LVL2_DAQ1_RQ       0x00000001U
+#define LVL2_DAQ2_RQ       0x00000002U
+#define LVL2_DAQ1_GR       0x00000004U
+#define LVL2_DAQ2_GR       0x00000008U
+
+
+/* TUNDRA internal registers */
+
+#define DMALAR          0x00
+#define DMAVAR          0x04
+#define DMATC           0x08
+#define DCSR            0x0c
+#define VMEBAR          0x10
+#define RXDATA          0x14
+#define RXADDR          0x18
+#define RXCTL           0x1c
+#define BUSSEL          0x20
+#define IVECT           0x24
+#define APBR            0x28
+#define TXDATA          0x2c
+#define TXADDR          0x30
+#define TXCTL           0x34
+#define LMFIFO          0x38
+#define MODE            0x3c
+#define SA64BAR         0x40
+#define MA64BAR         0x44
+#define LAG             0x48
+#define DMAVTC          0x4c
+
+#define STAT0           0x80
+#define STAT1           0x84
+#define GENCTL          0x88
+#define VINT            0x8c
+#define VREQ            0x90
+#define VARB            0x94
+#define ID              0x98
+#define CTL2            0x9c
+#define I7S             0xa0
+#define LIS             0xa4
+#define I7E             0xa8
+#define LIE             0xac
+#define VIE             0xb0
+#define IC10            0xb4
+#define IC32            0xb8
+#define IC54            0xbc
+#define MISC            0xc0
+#define DLCT            0xc4
+#define DLST1           0xc8
+#define DLST2           0xcc
+#define DLST3           0xd0
+#define MBOX0           0xd4
+#define MBOX1           0xd8
+#define MBOX2           0xdc
+#define MBOX3           0xe0
+
+/* DISPLAY registers */
+
+#define DIGIT1		0x0c
+#define DIGIT2		0x08
+#define DIGIT3		0x04
+#define DIGIT4		0x00
+
+/* Trigger Codes */
+
+#define T_NORMAL	0x01
+#define T_BEGIN		0x02
+#define T_END		0x03
+#define T_CALIB		0x04
+#define T_SPILLON	0x05
+#define T_SPILLOFF	0x06
-- 
2.43.0