From bc9819822e2855cc662435915ce66c45b6f072d9 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Tue, 1 Jun 2021 18:39:19 +0200 Subject: [PATCH] add register 0x44 - default and broadcast addresses --- basics/rom_16x8.vhd | 48 +------------------------------------------ oldfiles/rom_16x8.vhd | 47 ++++++++++++++++++++++++++++++++++++++++++ trb_net16_regIO.vhd | 21 +++++++++++++------ 3 files changed, 63 insertions(+), 53 deletions(-) mode change 100644 => 120000 basics/rom_16x8.vhd create mode 100644 oldfiles/rom_16x8.vhd diff --git a/basics/rom_16x8.vhd b/basics/rom_16x8.vhd deleted file mode 100644 index f664fe8..0000000 --- a/basics/rom_16x8.vhd +++ /dev/null @@ -1,47 +0,0 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.std_logic_ARITH.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -library work; -use work.trb_net_std.all; - -entity rom_16x8 is - generic( - INIT0 : std_logic_vector(15 downto 0) := x"12A0"; - INIT1 : std_logic_vector(15 downto 0) := x"23b1"; - INIT2 : std_logic_vector(15 downto 0) := x"34c2"; - INIT3 : std_logic_vector(15 downto 0) := x"49d3"; - INIT4 : std_logic_vector(15 downto 0) := x"56e5"; - INIT5 : std_logic_vector(15 downto 0) := x"67d5"; - INIT6 : std_logic_vector(15 downto 0) := x"7818"; - INIT7 : std_logic_vector(15 downto 0) := x"8927" - ); - port( - CLK : in std_logic; - a : in std_logic_vector(2 downto 0); - dout : out std_logic_vector(15 downto 0) - ); -end entity; - -architecture rom_16x8_arch of rom_16x8 is - type ram_t is array(0 to 7) of std_logic_vector(15 downto 0); - SIGNAL rom : ram_t := (INIT0, INIT1, INIT2, INIT3, INIT4, INIT5, INIT6, INIT7); -begin - rom(0) <= INIT0; - rom(1) <= INIT1; - rom(2) <= INIT2; - rom(3) <= INIT3; - rom(4) <= INIT4; - rom(5) <= INIT5; - rom(6) <= INIT6; - rom(7) <= INIT7; - - process(CLK) - begin - if rising_edge(CLK) then - dout <= rom(conv_integer(a)); - end if; - end process; - -end architecture; \ No newline at end of file diff --git a/basics/rom_16x8.vhd b/basics/rom_16x8.vhd new file mode 120000 index 0000000..af43972 --- /dev/null +++ b/basics/rom_16x8.vhd @@ -0,0 +1 @@ +rom_16x16.vhd \ No newline at end of file diff --git a/oldfiles/rom_16x8.vhd b/oldfiles/rom_16x8.vhd new file mode 100644 index 0000000..f664fe8 --- /dev/null +++ b/oldfiles/rom_16x8.vhd @@ -0,0 +1,47 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.std_logic_ARITH.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; + +entity rom_16x8 is + generic( + INIT0 : std_logic_vector(15 downto 0) := x"12A0"; + INIT1 : std_logic_vector(15 downto 0) := x"23b1"; + INIT2 : std_logic_vector(15 downto 0) := x"34c2"; + INIT3 : std_logic_vector(15 downto 0) := x"49d3"; + INIT4 : std_logic_vector(15 downto 0) := x"56e5"; + INIT5 : std_logic_vector(15 downto 0) := x"67d5"; + INIT6 : std_logic_vector(15 downto 0) := x"7818"; + INIT7 : std_logic_vector(15 downto 0) := x"8927" + ); + port( + CLK : in std_logic; + a : in std_logic_vector(2 downto 0); + dout : out std_logic_vector(15 downto 0) + ); +end entity; + +architecture rom_16x8_arch of rom_16x8 is + type ram_t is array(0 to 7) of std_logic_vector(15 downto 0); + SIGNAL rom : ram_t := (INIT0, INIT1, INIT2, INIT3, INIT4, INIT5, INIT6, INIT7); +begin + rom(0) <= INIT0; + rom(1) <= INIT1; + rom(2) <= INIT2; + rom(3) <= INIT3; + rom(4) <= INIT4; + rom(5) <= INIT5; + rom(6) <= INIT6; + rom(7) <= INIT7; + + process(CLK) + begin + if rising_edge(CLK) then + dout <= rom(conv_integer(a)); + end if; + end process; + +end architecture; \ No newline at end of file diff --git a/trb_net16_regIO.vhd b/trb_net16_regIO.vhd index 92ec025..1655fbd 100644 --- a/trb_net16_regIO.vhd +++ b/trb_net16_regIO.vhd @@ -6,6 +6,7 @@ library work; use work.trb_net_std.all; use work.trb_net_components.all; use work.version.all; +use work.config.all; @@ -152,7 +153,7 @@ architecture trb_net16_regIO_arch of trb_net16_regIO is signal ADR_REJECTED : std_logic; signal ADR_DONT_UNDERSTAND : std_logic; signal buf_API_ERROR_PATTERN_OUT : std_logic_vector(31 downto 0); - signal rom_read_addr,buf_rom_read_addr : std_logic_vector(2 downto 0); + signal rom_read_addr,buf_rom_read_addr : std_logic_vector(3 downto 0); signal rom_read_dout : std_logic_vector(15 downto 0); signal length, next_length : std_logic_vector(15 downto 0); signal dont_understand, next_dont_understand : std_logic; @@ -351,7 +352,7 @@ begin when ONE_READ => --wait for register address if API_TYP_IN = TYPE_DAT and API_PACKET_NUM_IN = c_F0 and API_DATAREADY_IN = '1' then next_address <= API_DATA_IN; - rom_read_addr <= API_DATA_IN(1 downto 0) & '1'; + rom_read_addr <= API_DATA_IN(2 downto 0) & '1'; if or_all(API_DATA_IN(c_REGIO_ADDRESS_WIDTH-1 downto 8)) = '1' then --data port address if USE_DAT_PORT = c_YES then next_DAT_READ_ENABLE_OUT <= '1'; @@ -448,7 +449,7 @@ begin next_API_DATA_OUT <= buf_COMMON_CTRL_REG_OUT(regnum_cCTRL*c_REGIO_REG_WIDTH+31 downto regnum_cCTRL*c_REGIO_REG_WIDTH+16); when x"4" => next_API_DATA_OUT <= rom_read_dout; - rom_read_addr <= address(1 downto 0) & '0'; + rom_read_addr <= address(2 downto 0) & '0'; when x"5" => case address(0) is when '0' => @@ -674,7 +675,7 @@ begin saved_operation <= "0000"; saved_Reg_high <= (others => '0'); saved_Reg_low <= (others => '0'); - buf_rom_read_addr <= "000"; + buf_rom_read_addr <= "0000"; length <= (others => '0'); dont_understand <= '0'; addr_counter_enable <= '0'; @@ -927,7 +928,7 @@ begin --------------------------------------------------------------------- -- ROM with board information --------------------------------------------------------------------- - board_rom : rom_16x8 + board_rom : entity work.rom_16x16 generic map( INIT0 => COMPILE_TIME_LIB(15 downto 0), INIT1 => COMPILE_TIME_LIB(31 downto 16), @@ -936,7 +937,15 @@ begin INIT4 => HARDWARE_VERSION(15 downto 0), INIT5 => HARDWARE_VERSION(31 downto 16), INIT6 => INCLUDED_FEATURES(47 downto 32), - INIT7 => INCLUDED_FEATURES(63 downto 48) + INIT7 => INCLUDED_FEATURES(63 downto 48), + INIT8 => x"00" & BROADCAST_SPECIAL_ADDR, + INIT9 => INIT_ADDRESS, + INITA => x"0000", + INITB => x"0000", + INITC => x"0000", + INITD => x"0000", + INITE => x"0000", + INITF => x"0000" ) port map( CLK => CLK, -- 2.43.0