From bccdca472e264f121ed7024f09a3276796a68673 Mon Sep 17 00:00:00 2001 From: hadaq Date: Thu, 23 Jul 2009 15:50:51 +0000 Subject: [PATCH] Fixed memory leak in trbcmd added version . --- libtrbnet/Makefile | 2 +- libtrbnet/port.c | 6 +-- libtrbnet/port.h | 6 ++- libtrbnet/trbcmd.c | 22 ++++++--- libtrbnet/trberror.c | 5 +- libtrbnet/trberror.h | 1 + libtrbnet/trbnet.c | 109 +++++++++++++++++++++++++++++++++++++++---- libtrbnet/trbnet.h | 3 +- 8 files changed, 129 insertions(+), 25 deletions(-) diff --git a/libtrbnet/Makefile b/libtrbnet/Makefile index 30545c4..ffc70ea 100644 --- a/libtrbnet/Makefile +++ b/libtrbnet/Makefile @@ -82,4 +82,4 @@ trberror.o: trberror.h trberror.c trbnet.o: trbnet.h trbnet.c trberror.h fs_fpga_int_mem.h port.h -trbcmd.o: trbcmd.c trbnet.h port.h trberror.h fs_fpga_int_mem.h +trbcmd.o: trbcmd.c trbnet.h trberror.h fs_fpga_int_mem.h diff --git a/libtrbnet/port.c b/libtrbnet/port.c index 4740ff7..575553f 100644 --- a/libtrbnet/port.c +++ b/libtrbnet/port.c @@ -35,7 +35,7 @@ volatile uint32_t* GPIOE_OUT_OFFSET = NULL; volatile uint32_t* GPIOE_IN_OFFSET = NULL; volatile uint32_t* GPIOE_OE_OFFSET = NULL; -int init_ports() +int port_init_ports() { int memfd; uint32_t *mem = NULL; @@ -84,11 +84,11 @@ int init_ports() *(GPIOB_OE_OFFSET) = GPIOB_OE_PINS; /* write portC[17-0] */ *(GPIOC_OE_OFFSET) = GPIOC_OE_PINS; - + return 0; } -void close_ports() +void port_close_ports() { *(GPIOB_OE_OFFSET) = 0x0; *(GPIOC_OE_OFFSET) = 0x0; diff --git a/libtrbnet/port.h b/libtrbnet/port.h index efb321a..d4350f2 100644 --- a/libtrbnet/port.h +++ b/libtrbnet/port.h @@ -25,14 +25,16 @@ extern volatile uint32_t* GPIOE_OUT_OFFSET; extern volatile uint32_t* GPIOE_IN_OFFSET; extern volatile uint32_t* GPIOE_OE_OFFSET; +extern sigset_t GPIOE_BLOCKSET; + #define GPIO_PA 0x00 #define GPIO_PB 0x20 / sizeof(uint32_t) #define GPIO_PC 0x30 / sizeof(uint32_t) #define GPIO_PD 0x40 / sizeof(uint32_t) #define GPIO_PE 0x50 / sizeof(uint32_t) -int init_ports(); -void close_ports(); +int port_init_ports(); +void port_close_ports(); static inline void close_ports_special(uint32_t portBOE, uint32_t portCOE) { diff --git a/libtrbnet/trbcmd.c b/libtrbnet/trbcmd.c index e7706df..5a430c6 100644 --- a/libtrbnet/trbcmd.c +++ b/libtrbnet/trbcmd.c @@ -1,3 +1,4 @@ +static char rcsId[]=""; #define _GNU_SOURCE #include #include @@ -15,6 +16,8 @@ #define HEXMODE 0 #endif +#define VERSION_NUMBER "2.00 20090723" + static int hexMode = HEXMODE; /* ------ MAIN ---------------------------------------------------------- */ @@ -34,6 +37,7 @@ void usage(const char *progName) printf(" -l lazy-mode: skip most consistency-checks of packages\n"); printf(" -H hex-mode: all following arguments will be interpreted " "as hexadecimal-numbers\n"); + printf(" -V Version number\n"); printf("\nCommands:\n"); printf(" r -> read register\n"); printf(" w -> write register\n"); @@ -67,6 +71,7 @@ int main(int argc, char ** argv) char scriptFileName[256] = ""; char cmd[CMD_MAX_NUM][CMD_SIZE]; char *cmdLine = NULL; + size_t cmdLineLen = 0; unsigned int cmdLen = 0; uint16_t trb_address = 0; uint16_t reg_address = 0; @@ -78,7 +83,7 @@ int main(int argc, char ** argv) trb_lazy = 0; /* Parse Arguments */ - while ((opt = getopt(argc, argv, "+hf:n:d:DlH")) != -1) { + while ((opt = getopt(argc, argv, "+hf:n:d:DlHV")) != -1) { switch (opt) { case '?': usage(basename(argv[0])); @@ -104,6 +109,10 @@ int main(int argc, char ** argv) case 'H': hexMode = 1; break; + case 'V': + printf("trbcmd %s\n", VERSION_NUMBER); + exit(EXIT_SUCCESS); + break; default: break; } @@ -145,7 +154,7 @@ int main(int argc, char ** argv) } else { /* Get next command from file */ char *c = NULL; - size_t len = 0; + unsigned int i; lineCtr++; @@ -154,7 +163,8 @@ int main(int argc, char ** argv) cmd[i][0] = '\0'; } - if ((scriptStatus = getline(&cmdLine, &len, scriptFile)) == -1) { + if ((scriptStatus = + getline(&cmdLine, &cmdLineLen, scriptFile)) == -1) { if (feof(scriptFile) != 0) { /* EOF reached */ rewind(scriptFile); @@ -165,7 +175,7 @@ int main(int argc, char ** argv) exit(EXIT_FAILURE); } } - + /* Remove newline and comments */ if ((c = strchr(cmdLine, '\n')) != NULL) { *c = '\0'; @@ -186,9 +196,8 @@ int main(int argc, char ** argv) /* Empty Line */ continue; } - printf("#Line %d: %s\n", lineCtr, cmdLine); } - + if (strncmp(cmd[0], "w", CMD_SIZE) == 0) { /*******************************************/ @@ -752,7 +761,6 @@ int main(int argc, char ** argv) } exit(EXIT_FAILURE); } - } /* End script-file-loop */ } /* End repeat-loop */ diff --git a/libtrbnet/trberror.c b/libtrbnet/trberror.c index 0a79e91..57a680b 100644 --- a/libtrbnet/trberror.c +++ b/libtrbnet/trberror.c @@ -49,10 +49,11 @@ const char* trb_strerror(int errno) "DMA not available (check whether module 'can_module.ko' is loaded)", "DMA-Timeout", "ReadMem invalid size", - "Invalid data-length give by Header" + "Invalid data-length give by Header", + "FIFO Incomplete, missing", }; - if (errno < 23) { + if (errno < 24) { return errorstring[errno]; } else { return "Unknown Errno"; diff --git a/libtrbnet/trberror.h b/libtrbnet/trberror.h index 9852160..35ed32b 100644 --- a/libtrbnet/trberror.h +++ b/libtrbnet/trberror.h @@ -27,6 +27,7 @@ typedef enum { TRB_DMA_TIMEOUT = 20, TRB_READMEM_INVALID_SIZE = 21, TRB_HDR_DLEN = 22, + TRB_FIFO_INCOMPLETE } TRB_ERROR; diff --git a/libtrbnet/trbnet.c b/libtrbnet/trbnet.c index 77ccc4f..1580f1f 100644 --- a/libtrbnet/trbnet.c +++ b/libtrbnet/trbnet.c @@ -1,6 +1,8 @@ #include #include +#include #include +#include #include #include "trbnet.h" @@ -120,9 +122,12 @@ #define MAX_TIME_OUT 1500000 #define DATA_BUFFER_SIZE 8192 - /* ---------------------------------------------------------------------- */ +static sigset_t blockSet; /* Used for blocking Signals SIGINT and SIGTERM */ +static sigset_t blockSetOld; +static int signalsBlocked = 0; + unsigned int trb_debug = 0; unsigned int trb_lazy = 0; unsigned int trb_dma = 0; @@ -615,7 +620,7 @@ static int trb_fifo_read(uint8_t channel, case HEADER_DAT: for (i = 0; (i < 2) && (dataCtr < len); i++) { if (dataCtr < dsize) { - data[dataCtr++] = i == 0 + data[dataCtr++] = (i == 0) ? (((uint32_t)package.F0 << 16) | ((uint32_t)package.F1)) : (((uint32_t)package.F2 << 16) | @@ -727,7 +732,7 @@ static int trb_fifo_read(uint8_t channel, if (timeout >= MAX_TIME_OUT) { trb_fifo_flush(channel); - trb_errno = TRB_FIFO_TIMEOUT; + trb_errno = TRB_FIFO_INCOMPLETE; return -1; } } @@ -772,8 +777,44 @@ static int trb_fifo_read(uint8_t channel, return dataCtr; } +static void blockSignals() +{ + signalsBlocked++; + if (signalsBlocked > 1) return; + sigprocmask(SIG_BLOCK, &blockSet, &blockSetOld); +} + +static void unblockSignals() +{ + signalsBlocked--; + if (signalsBlocked > 0) return; + sigprocmask(SIG_SETMASK, &blockSetOld, NULL); +} + /* ----- Global Functions ----------------------------------------------- */ +/* Intit FPGA Interface */ +int init_ports() +{ + /* Set signal mask for blocking */ + sigemptyset(&blockSet); + sigaddset(&blockSet, SIGINT); + sigaddset(&blockSet, SIGTERM); + sigemptyset(&blockSetOld); + + if (port_init_ports() != 0) { + /* Set trberrno ?? */ + return -1; + } + + return 0; +} + +void close_ports() +{ + port_close_ports(); +} + int trb_fifo_flush(uint8_t channel) { uint32_t tmp; @@ -791,6 +832,8 @@ int trb_fifo_flush(uint8_t channel) if (trb_debug > 1) { fprintf(stderr, "Flushing FIFO of channel# %d\n", channel); } + + blockSignals(); fifoAddress = CHANNEL_N_RECEIVER_DATA | ((channel * 2 + 1) << 4); do { @@ -802,6 +845,8 @@ int trb_fifo_flush(uint8_t channel) } } while ((tmp & MASK_FIFO_VALID) != 0); + unblockSignals(); + return 0; } @@ -823,7 +868,9 @@ int trb_register_read(uint16_t trb_address, if (trb_debug > 0) { fprintf(stderr, "Init_Transfer done.\n"); } - + + blockSignals(); + /* Build up package and start transfer */ write32_to_FPGA(CHANNEL_3_TARGET_ADDRESS, trb_address); write32_to_FPGA(CHANNEL_3_SENDER_ERROR, 0x00000000); @@ -840,6 +887,8 @@ int trb_register_read(uint16_t trb_address, status = trb_fifo_read(3, FIFO_MODE_REG_READ, data, dsize); + unblockSignals(); + if ((status > 0) && (status % 2 != 0)) { trb_errno = TRB_INVALID_PKG_NUMBER; return -1; @@ -880,6 +929,8 @@ int trb_register_read_mem(uint16_t trb_address, fprintf(stderr, "Init_Tranfer done.\n"); } + blockSignals(); + /* Build up package and start transfer */ write32_to_FPGA(CHANNEL_3_TARGET_ADDRESS, trb_address); write32_to_FPGA(CHANNEL_3_SENDER_ERROR, 0x00000000); @@ -896,6 +947,8 @@ int trb_register_read_mem(uint16_t trb_address, status = trb_fifo_read(3, FIFO_MODE_REG_READ_MEM, data, dsize); + unblockSignals(); + if (status == -1) return status; /* Check size */ @@ -918,6 +971,8 @@ int trb_register_write(uint16_t trb_address, uint16_t reg_address, uint32_t value) { + int status; + trb_errno = TRB_NONE; /* Init transfer */ @@ -930,6 +985,8 @@ int trb_register_write(uint16_t trb_address, fprintf(stderr, "Init_Transfer done.\n"); } + blockSignals(); + /* Build up package */ write32_to_FPGA(CHANNEL_3_TARGET_ADDRESS, trb_address); write32_to_FPGA(CHANNEL_3_SENDER_ERROR, 0x00000000); @@ -944,7 +1001,11 @@ int trb_register_write(uint16_t trb_address, fprintf(stderr, "CMD_REGISTER_WRITE started.\n"); } - return trb_fifo_read(3, FIFO_MODE_REG_WRITE, NULL, 0); + status = trb_fifo_read(3, FIFO_MODE_REG_WRITE, NULL, 0); + + unblockSignals(); + + return status; } int trb_register_write_mem(uint16_t trb_address, @@ -955,6 +1016,7 @@ int trb_register_write_mem(uint16_t trb_address, { uint16_t config; uint16_t i; + int status; trb_errno = TRB_NONE; @@ -976,6 +1038,8 @@ int trb_register_write_mem(uint16_t trb_address, fprintf(stderr, "Init_Transfer done.\n"); } + blockSignals(); + /* Build up package */ write32_to_FPGA(CHANNEL_3_TARGET_ADDRESS, trb_address); write32_to_FPGA(CHANNEL_3_SENDER_ERROR, 0x00000000); @@ -996,7 +1060,11 @@ int trb_register_write_mem(uint16_t trb_address, fprintf(stderr, "CMD_REGISTER_WRITE_MEM started.\n"); } - return trb_fifo_read(3, FIFO_MODE_REG_WRITE, NULL, 0); + status = trb_fifo_read(3, FIFO_MODE_REG_WRITE, NULL, 0); + + unblockSignals(); + + return status; } int trb_read_uid(uint16_t trb_address, @@ -1017,6 +1085,8 @@ int trb_read_uid(uint16_t trb_address, fprintf(stderr, "Init_Transfer done.\n"); } + blockSignals(); + /* Build up package and start transfer */ write32_to_FPGA(CHANNEL_3_TARGET_ADDRESS, trb_address); write32_to_FPGA(CHANNEL_3_SENDER_ERROR, 0x00000000); @@ -1033,6 +1103,8 @@ int trb_read_uid(uint16_t trb_address, status = trb_fifo_read(3, FIFO_MODE_UID, (uint32_t*)uidBuffer, dsize); + unblockSignals(); + if ((status > 0) && (status % 4 != 0)) { trb_errno = TRB_INVALID_PKG_NUMBER; return -1; @@ -1066,6 +1138,8 @@ int trb_set_address(uint64_t uid, fprintf(stderr, "Init_Transfer done.\n"); } + blockSignals(); + /* Build up package and start transfer */ write32_to_FPGA(CHANNEL_3_TARGET_ADDRESS, 0xffff); /* always broadcast */ write32_to_FPGA(CHANNEL_3_SENDER_ERROR, 0x00000000); @@ -1085,8 +1159,10 @@ int trb_set_address(uint64_t uid, } status = trb_fifo_read(3, FIFO_MODE_SET_ADDRESS, NULL, 0); + + unblockSignals(); + if (status == -1) return -1; - if (status != 2) { trb_errno = TRB_ENDPOINT_NOT_REACHED; return -1; @@ -1118,6 +1194,8 @@ int trb_ipu_data_read(uint8_t type, fprintf(stderr, "Init_Transfer done.\n"); } + blockSignals(); + /* Prepare IPU channel */ write32_to_FPGA(CHANNEL_1_SENDER_ERROR, (((uint32_t)trg_info << 24) | ((uint32_t)trg_random << 16) | @@ -1133,6 +1211,8 @@ int trb_ipu_data_read(uint8_t type, status = trb_fifo_read(1, FIFO_MODE_IPU_DATA, data, dsize); + unblockSignals(); + return status; } @@ -1156,6 +1236,8 @@ int trb_send_trigger(uint8_t type, fprintf(stderr, "Init_Transfer done.\n"); } + blockSignals(); + /* Prepare trigger channel */ write32_to_FPGA(CHANNEL_0_SENDER_ERROR, (((uint32_t)trg_info << 24) | ((uint32_t)trg_random << 16) | @@ -1172,6 +1254,9 @@ int trb_send_trigger(uint8_t type, /* Check for replay packets (trigger) */ status = trb_fifo_read(0, FIFO_MODE_NONE, NULL, 0); + + unblockSignals(); + if (status == -1) return -1; return 0; @@ -1202,6 +1287,8 @@ int trb_send_trigger_rich(uint8_t trg_input, fprintf(stderr, "Init_Transfer done.\n"); } + blockSignals(); + /* Prepare trigger channel */ write32_to_FPGA(CHANNEL_0_SENDER_ERROR, (((uint32_t)trg_info << 24) | ((uint32_t)trg_random << 16) | @@ -1212,8 +1299,8 @@ int trb_send_trigger_rich(uint8_t trg_input, write32_to_FPGA(CHANNEL_3_TARGET_ADDRESS, 0x0000fffb); /* RICH Subnet only */ write32_to_FPGA(CHANNEL_3_SENDER_ERROR, 0x00000000); write32_to_FPGA(CHANNEL_3_SENDER_DATA, (0x8080 | (uint32_t)trg_input)); - write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x0000dead); /*fake data is */ - write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x0000beef); /* discarded at ADCM */ + write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x0000dead); /* fake data is */ + write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x0000beef); /* discarded at ADCM */ write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000); /* Send both fake trigger and LVL1 information */ @@ -1229,11 +1316,15 @@ int trb_send_trigger_rich(uint8_t trg_input, status = trb_fifo_read(3, FIFO_MODE_NONE, NULL, 0); if (status == -1) { trb_fifo_flush(0); + unblockSignals(); return -1; } /* Check for replay packets (trigger) */ status = trb_fifo_read(0, FIFO_MODE_NONE, NULL, 0); + + unblockSignals(); + if (status == -1) return -1; return 0; diff --git a/libtrbnet/trbnet.h b/libtrbnet/trbnet.h index fdef48f..78d1814 100644 --- a/libtrbnet/trbnet.h +++ b/libtrbnet/trbnet.h @@ -2,7 +2,6 @@ #define TRBNET_H #include -#include extern unsigned int trb_debug; extern unsigned int trb_lazy; @@ -10,6 +9,8 @@ extern unsigned int trb_dma; /* ---------------------------------------------------------------------- */ +int init_ports(); + int trb_fifo_flush(uint8_t channel); int trb_register_read(uint16_t trb_address, -- 2.43.0