From bd403499d7389f8ad431dcecd96711c5fc7f48cf Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Thu, 15 Dec 2022 12:14:59 +0100 Subject: [PATCH] add flash register settings for hub --- hub/config_compile_frankfurt.pl | 4 ++-- hub/trb3sc_hub.vhd | 16 ++++++++++------ 2 files changed, 12 insertions(+), 8 deletions(-) diff --git a/hub/config_compile_frankfurt.pl b/hub/config_compile_frankfurt.pl index 6ed0532..e6790b2 100644 --- a/hub/config_compile_frankfurt.pl +++ b/hub/config_compile_frankfurt.pl @@ -1,8 +1,8 @@ TOPNAME => "trb3sc_hub", lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; lm_license_file_for_par => "1710\@jspc29", -lattice_path => '/d/jspc29/lattice/diamond/3.11_x64', -synplify_path => '/d/jspc29/lattice/synplify/R-2020.09-SP1', +lattice_path => '/d/jspc29/lattice/diamond/3.12', +synplify_path => '/d/jspc29/lattice/synplify/S-2021.09-SP2', #synplify_path => '/d/jspc29/lattice/synplify/L-2016.09-1/', #synplify_command => "/d/jspc29/lattice/diamond/3.5_x64/bin/lin64/synpwrap -fg -options", #synplify_command => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp", diff --git a/hub/trb3sc_hub.vhd b/hub/trb3sc_hub.vhd index 969ff5d..7d1108d 100644 --- a/hub/trb3sc_hub.vhd +++ b/hub/trb3sc_hub.vhd @@ -108,7 +108,7 @@ architecture trb3sc_arch of trb3sc_hub is signal med_stat_debug : std_logic_vector (1*64-1 downto 0); signal ctrlbus_rx, bussci1_rx, bussci2_rx, bussci3_rx, bussci4_rx, bustools_rx, - bustc_rx, busgbeip_rx, busgbereg_rx, bus_master_out, handlerbus_rx : CTRLBUS_RX; + bustc_rx, busgbeip_rx, busgbereg_rx, bus_master_out : CTRLBUS_RX; signal ctrlbus_tx, bussci1_tx, bussci2_tx, bussci3_tx, bussci4_tx, bustools_tx, bustc_tx, busgbeip_tx, busgbereg_tx, bus_master_in : CTRLBUS_TX; @@ -620,7 +620,9 @@ gen_hub_with_gbe : if INCLUDE_GBE = c_YES generate BUS_RX => ctrlbus_rx, BUS_TX => ctrlbus_tx, TIMER => timer, - + BUS_MASTER_IN => bus_master_in, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, --Gbe Sctrl Input GSC_INIT_DATAREADY_IN => gsc_init_dataready, GSC_INIT_DATA_IN => gsc_init_data, @@ -697,7 +699,9 @@ gen_hub_no_gbe : if INCLUDE_GBE = c_NO generate REGIO_WRITE_ACK_IN => wrack, REGIO_UNKNOWN_ADDR_IN => ctrlbus_tx.unknown, REGIO_TIMEOUT_OUT => ctrlbus_rx.timeout, - + BUS_MASTER_IN => bus_master_in, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, ONEWIRE => TEMPSENS, ONEWIRE_MONITOR_OUT => open, --Status ports (for debugging) @@ -738,7 +742,7 @@ end generate; CLK => clk_sys, RESET => reset_i, - REGIO_RX => handlerbus_rx, + REGIO_RX => ctrlbus_rx, REGIO_TX => ctrlbus_tx, BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED @@ -760,7 +764,7 @@ end generate; STAT_DEBUG => open ); - handlerbus_rx <= ctrlbus_rx when bus_master_active = '0' else bus_master_out; + --handlerbus_rx <= ctrlbus_rx;-- when bus_master_active = '0' else bus_master_out; --------------------------------------------------------------------------- -- Control Tools @@ -801,7 +805,7 @@ end generate; BUS_RX => bustools_rx, BUS_TX => bustools_tx, --Control master for default settings - BUS_MASTER_IN => ctrlbus_tx, + BUS_MASTER_IN => bus_master_in, BUS_MASTER_OUT => bus_master_out, BUS_MASTER_ACTIVE => bus_master_active, DEBUG_OUT => open -- 2.43.0