From bd95cfb8c81bded5cf2498762257593f02301c14 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Wed, 20 Nov 2013 19:38:33 +0100 Subject: [PATCH] first final padiwa_amps design --- base/padiwa_amps.lpf | 56 +++++++++++++++++++++--------------------- padiwa/padiwa_amps.vhd | 32 +++++++++++++++++------- 2 files changed, 51 insertions(+), 37 deletions(-) diff --git a/base/padiwa_amps.lpf b/base/padiwa_amps.lpf index 03c7667..3de9338 100644 --- a/base/padiwa_amps.lpf +++ b/base/padiwa_amps.lpf @@ -104,20 +104,20 @@ DEFINE PORT GROUP "LED_group" "LED*" ; IOBUF GROUP "LED_group" IO_TYPE=LVCMOS33 DRIVE=4 SLEWRATE=SLOW; -LOCATE COMP "TEST_LINE0" SITE "F14"; -LOCATE COMP "TEST_LINE1" SITE "F16"; -LOCATE COMP "TEST_LINE2" SITE "F15"; -LOCATE COMP "TEST_LINE3" SITE "E16"; -LOCATE COMP "TEST_LINE4" SITE "E15"; -LOCATE COMP "TEST_LINE5" SITE "D16"; -LOCATE COMP "TEST_LINE6" SITE "D15"; -LOCATE COMP "TEST_LINE7" SITE "C16"; -LOCATE COMP "TEST_LINE8" SITE "C15"; -LOCATE COMP "TEST_LINE9" SITE "B16"; -LOCATE COMP "TEST_LINE10" SITE "E14"; -LOCATE COMP "TEST_LINE11" SITE "D14"; -LOCATE COMP "TEST_LINE12" SITE "F13"; -LOCATE COMP "TEST_LINE13" SITE "G12"; +LOCATE COMP "TEST_LINE_0" SITE "F14"; +LOCATE COMP "TEST_LINE_1" SITE "F16"; +LOCATE COMP "TEST_LINE_2" SITE "F15"; +LOCATE COMP "TEST_LINE_3" SITE "E16"; +LOCATE COMP "TEST_LINE_4" SITE "E15"; +LOCATE COMP "TEST_LINE_5" SITE "D16"; +LOCATE COMP "TEST_LINE_6" SITE "D15"; +LOCATE COMP "TEST_LINE_7" SITE "C16"; +LOCATE COMP "TEST_LINE_8" SITE "C15"; +LOCATE COMP "TEST_LINE_9" SITE "B16"; +LOCATE COMP "TEST_LINE_10" SITE "E14"; +LOCATE COMP "TEST_LINE_11" SITE "D14"; +LOCATE COMP "TEST_LINE_12" SITE "F13"; +LOCATE COMP "TEST_LINE_13" SITE "G12"; DEFINE PORT GROUP "TEST_group" "TEST*" ; IOBUF GROUP "TEST_group" IO_TYPE=LVCMOS33 DRIVE=8; @@ -141,20 +141,20 @@ IOBUF PORT "SPARE_LVDS" IO_TYPE=LVDS25; LOCATE COMP "DELAY_C_IN_8" SITE "G14"; #"DL_BR_08_C_0" LOCATE COMP "DELAY_C_OUT_8" SITE "G15"; #"DL_BR_08_C_1" -LOCATE COMP "DELAY_C_IN_7" SITE "L14"; #"DL_BR_10_C_0" -LOCATE COMP "DELAY_C_OUT_7" SITE "L16"; #"DL_BR_10_C_1" -LOCATE COMP "DELAY_C_IN_6" SITE "L15"; #"DL_BR_13_C_0" -LOCATE COMP "DELAY_C_OUT_6" SITE "M16"; #"DL_BR_13_C_1" -LOCATE COMP "DELAY_C_IN_5" SITE "N15"; #"DL_BR_15_C_0" -LOCATE COMP "DELAY_C_OUT_5" SITE "P16"; #"DL_BR_15_C_1" -LOCATE COMP "DELAY_C_IN_4" SITE "N14"; #"DL_BR_16_C_0" -LOCATE COMP "DELAY_C_OUT_4" SITE "N16"; #"DL_BR_16_C_1" -LOCATE COMP "DELAY_C_IN_3" SITE "P15"; #"DL_BR_18_C_2" -LOCATE COMP "DELAY_C_OUT_3" SITE "R16"; #"DL_BR_18_C_3" -LOCATE COMP "DELAY_C_IN_2" SITE "J14"; #"DL_BR_19_C_0" -LOCATE COMP "DELAY_C_OUT_2" SITE "J16"; #"DL_BR_19_C_1" -LOCATE COMP "DELAY_C_IN_1" SITE "J15"; #"DL_BR_20_C_0" -LOCATE COMP "DELAY_C_OUT_1" SITE "K16"; #"DL_BR_20_C_1" +LOCATE COMP "DELAY_C_IN_7" SITE "J14"; #"DL_BR_10_C_0" +LOCATE COMP "DELAY_C_OUT_7" SITE "J16"; #"DL_BR_10_C_1" +LOCATE COMP "DELAY_C_IN_6" SITE "J15"; #"DL_BR_13_C_0" +LOCATE COMP "DELAY_C_OUT_6" SITE "K16"; #"DL_BR_13_C_1" +LOCATE COMP "DELAY_C_IN_5" SITE "L14"; #"DL_BR_15_C_0" +LOCATE COMP "DELAY_C_OUT_5" SITE "L16"; #"DL_BR_15_C_1" +LOCATE COMP "DELAY_C_IN_4" SITE "L15"; #"DL_BR_16_C_0" +LOCATE COMP "DELAY_C_OUT_4" SITE "M16"; #"DL_BR_16_C_1" +LOCATE COMP "DELAY_C_IN_3" SITE "N15"; #"DL_BR_18_C_2" +LOCATE COMP "DELAY_C_OUT_3" SITE "P16"; #"DL_BR_18_C_3" +LOCATE COMP "DELAY_C_IN_2" SITE "N14"; #"DL_BR_19_C_0" +LOCATE COMP "DELAY_C_OUT_2" SITE "N16"; #"DL_BR_19_C_1" +LOCATE COMP "DELAY_C_IN_1" SITE "P15"; #"DL_BR_20_C_0" +LOCATE COMP "DELAY_C_OUT_1" SITE "R16"; #"DL_BR_20_C_1" DEFINE PORT GROUP "DELAY_C_OUT_group" "DELAY_C_OUT*" ; IOBUF GROUP "DELAY_C_OUT_group" IO_TYPE=LVCMOS33 DRIVE=24 PULLMODE=DOWN; diff --git a/padiwa/padiwa_amps.vhd b/padiwa/padiwa_amps.vhd index 9b602b3..3b81203 100644 --- a/padiwa/padiwa_amps.vhd +++ b/padiwa/padiwa_amps.vhd @@ -179,8 +179,8 @@ signal ram : ram_t; signal pwm_i : std_logic_vector(32 downto 1); signal INP_i : std_logic_vector(15 downto 0); -signal fast_input : std_logic_vector(7 downto 0); -signal slow_input : std_logic_vector(7 downto 0); +signal fast_input : std_logic_vector(8 downto 1); +signal slow_input : std_logic_vector(8 downto 1); signal spi_reg00_i : std_logic_vector(15 downto 0); signal spi_reg10_i : std_logic_vector(15 downto 0); signal spi_reg20_i : std_logic_vector(15 downto 0); @@ -215,7 +215,11 @@ signal inp_invert : std_logic_vector(15 downto 0); signal input_enable : std_logic_vector(15 downto 0); signal inp_status : std_logic_vector(15 downto 0); signal led_status : std_logic_vector(8 downto 0) := "100000000"; -signal discharge_disable : std_logic_vector(7 downto 0); +signal discharge_disable : std_logic_vector(8 downto 1); +signal discharge_highz : std_logic_vector(8 downto 1); +signal discharge_override : std_logic_vector(8 downto 1); +signal delay_invert : std_logic_vector(8 downto 1); + signal timer : unsigned(18 downto 0) := (others => '0'); signal last_inp : std_logic_vector(15 downto 0) := (others => '0'); @@ -558,7 +562,10 @@ THE_IO_REG_WRITE : process begin when x"4" => inp_invert <= spi_data_i; when x"5" => inp_stretch <= spi_data_i; when x"6" => comp_setting <= spi_data_i; - when x"7" => discharge_disable <= spi_data_i(7 downto 0); + when x"7" => discharge_disable <= spi_data_i(7 downto 0); + when x"8" => discharge_override <= spi_data_i(7 downto 0); + when x"9" => discharge_highz <= spi_data_i(7 downto 0); + when x"a" => delay_invert <= spi_data_i(7 downto 0); when others => null; end case; end if; @@ -582,12 +589,19 @@ end generate; --------------------------------------------------------------------------- -- Delay generation --------------------------------------------------------------------------- -DELAY_C_OUT <= fast_input; -DISCHARGE <= DELAY_C_IN and fast_input and not discharge_disable; -fast_input <= INP_i(14) & INP_i(12) & INP_i(10) & INP_i(8) & INP_i(6) & INP_i(4) & INP_i(2) & INP_i(0); -slow_input <= INP_i(15) & INP_i(13) & INP_i(11) & INP_i(9) & INP_i(7) & INP_i(5) & INP_i(3) & INP_i(1); +gen_discharge : for i in 1 to 8 generate +DISCHARGE(i) <= 'Z' when discharge_highz(i) = '1' else + (DELAY_C_IN(i) and slow_input(i)) when discharge_disable(i) = '0' else + discharge_override(i) when discharge_disable(i) = '1'; + +DELAY_C_OUT(i) <= slow_input(i) xor delay_invert(i); +end generate; + +fast_input <= inp_gated(14) & inp_gated(12) & inp_gated(10) & inp_gated(8) & inp_gated(6) & inp_gated(4) & inp_gated(2) & inp_gated(0); +slow_input <= inp_gated(15) & inp_gated(13) & inp_gated(11) & inp_gated(9) & inp_gated(7) & inp_gated(5) & inp_gated(3) & inp_gated(1); + --------------------------------------------------------------------------- -- LED blinking when activity on inputs @@ -641,7 +655,7 @@ TEST_LINE <= (others => '0'); gen_leds : for i in 1 to 8 generate - LED(i) <= not leds((i-1)*2) when led_status(8) = '1' else '1'; + LED(i) <= not leds((i-1)*2) when led_status(8) = '1' else not led_status(i-1); end generate; -- 2.43.0