From bdc8baf97a83f7856c2fcff2c3bab88c253867d7 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Wed, 6 Jan 2016 19:23:41 +0100 Subject: [PATCH] Adding preliminary pinout and device config for dirich --- dirich/config.vhd | 8 ++++---- dirich/dirich.lpf | 18 ++++++++++++++---- dirich/dirich.vhd | 6 +++--- pinout/dirich.lpf | 44 ++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 65 insertions(+), 11 deletions(-) diff --git a/dirich/config.vhd b/dirich/config.vhd index 947e6d4..905c547 100644 --- a/dirich/config.vhd +++ b/dirich/config.vhd @@ -32,13 +32,13 @@ package config is --Address settings constant INIT_ADDRESS : std_logic_vector := x"F3D1"; - constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"70"; + constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"51"; --set to 0 for backplane serdes, set to 3 for front SFP serdes - constant INCLUDE_UART : integer := c_YES; - constant INCLUDE_SPI : integer := c_YES; - constant INCLUDE_LCD : integer := c_YES; + constant INCLUDE_UART : integer := c_NO; + constant INCLUDE_SPI : integer := c_NO; + constant INCLUDE_LCD : integer := c_NO; constant INCLUDE_DEBUG_INTERFACE: integer := c_YES; --input monitor and trigger generation logic diff --git a/dirich/dirich.lpf b/dirich/dirich.lpf index 90bb160..7765bf4 100644 --- a/dirich/dirich.lpf +++ b/dirich/dirich.lpf @@ -3,6 +3,20 @@ BLOCK RESETPATHS ; BLOCK ASYNCPATHS ; BLOCK RD_DURING_WR_PATHS ; + +SYSCONFIG MCCLK_FREQ=38.8 CONFIG_IOVOLTAGE=3.3 ; #BACKGROUND_RECONFIG=ON +BANK 0 VCCIO 2.5 V; +BANK 1 VCCIO 2.5 V; +BANK 2 VCCIO 2.5 V; +BANK 3 VCCIO 2.5 V; +BANK 6 VCCIO 2.5 V; +BANK 7 VCCIO 2.5 V; +BANK 8 VCCIO 3.3 V; + + +FREQUENCY PORT CLOCK_IN 240 MHz; + + BLOCK PATH TO PORT "LED*"; BLOCK PATH TO PORT "PROGRAMN"; BLOCK PATH TO PORT "TEMPSENS"; @@ -14,8 +28,4 @@ MULTICYCLE FROM CELL "THE_CLOCK_RESET/clear_n_i" 20 ns; MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns; MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns; - -FREQUENCY PORT CLOCK_IN 240 MHz; - -SYSCONFIG MCCLK_FREQ = 38.8; GSR_NET NET "GSR_N"; diff --git a/dirich/dirich.vhd b/dirich/dirich.vhd index cd7f5f5..7d8e030 100644 --- a/dirich/dirich.vhd +++ b/dirich/dirich.vhd @@ -274,9 +274,9 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record ADC_MISO => ADC_DOUT, ADC_CLK => ADC_CLK, --Trigger & Monitor - MONITOR_INPUTS => (others => '0'), - TRIG_GEN_INPUTS => (others => '0'), - TRIG_GEN_OUTPUTS => open, + MONITOR_INPUTS => INPUT, + TRIG_GEN_INPUTS => INPUT, + TRIG_GEN_OUTPUTS => CTRL(4 downto 3), --SED SED_ERROR_OUT => sed_error_i, --Slowcontrol diff --git a/pinout/dirich.lpf b/pinout/dirich.lpf index e69de29..4c176c3 100644 --- a/pinout/dirich.lpf +++ b/pinout/dirich.lpf @@ -0,0 +1,44 @@ +LOCATE COMP "INPUT[0]" SITE "B5" ; +LOCATE COMP "INPUT[1]" SITE "C4" ; +LOCATE COMP "INPUT[2]" SITE "A2" ; +LOCATE COMP "INPUT[3]" SITE "B2" ; +LOCATE COMP "INPUT[4]" SITE "C1" ; +LOCATE COMP "INPUT[5]" SITE "D2" ; +LOCATE COMP "INPUT[6]" SITE "K2" ; +LOCATE COMP "INPUT[7]" SITE "H1" ; +LOCATE COMP "INPUT[8]" SITE "K4" ; +LOCATE COMP "INPUT[9]" SITE "L4" ; +LOCATE COMP "INPUT[10]" SITE "M4" ; +LOCATE COMP "INPUT[11]" SITE "N4" ; +LOCATE COMP "INPUT[12]" SITE "P1" ; +LOCATE COMP "INPUT[13]" SITE "P3" ; +LOCATE COMP "INPUT[14]" SITE "U18" ; +LOCATE COMP "INPUT[15]" SITE "U16" ; +LOCATE COMP "INPUT[16]" SITE "C18" ; +LOCATE COMP "INPUT[17]" SITE "E16" ; +LOCATE COMP "INPUT[18]" SITE "K16" ; +LOCATE COMP "INPUT[19]" SITE "C20" ; +LOCATE COMP "INPUT[20]" SITE "D20" ; +LOCATE COMP "INPUT[21]" SITE "E20" ; +LOCATE COMP "INPUT[22]" SITE "N16" ; +LOCATE COMP "INPUT[23]" SITE "N18" ; +LOCATE COMP "INPUT[24]" SITE "N17" ; +LOCATE COMP "INPUT[25]" SITE "R16" ; +LOCATE COMP "INPUT[26]" SITE "N19" ; +LOCATE COMP "INPUT[27]" SITE "P19" ; +LOCATE COMP "INPUT[28]" SITE "N3" ; +LOCATE COMP "INPUT[29]" SITE "L3" ; +LOCATE COMP "INPUT[30]" SITE "N2" ; +LOCATE COMP "INPUT[31]" SITE "L1" ; +DEFINE PORT GROUP "INP_group" "INP*" ; +IOBUF GROUP "INP_group" IO_TYPE=LVDS DIFFRESISTOR=OFF BANK_VCCIO=2.5; + +LOCATE COMP "CLOCK_IN" SITE "L20"; +DEFINE PORT GROUP "CLK_group" "CL*" ; +IOBUF GROUP "CLK_group" IO_TYPE=LVDS DIFFRESISTOR=100 BANK_VCCIO=2.5; + +LOCATE COMP "TRIG_IN" SITE "L19"; +DEFINE PORT GROUP "TRIG_group" "TRIG*" ; +IOBUF GROUP "TRIG_group" IO_TYPE=LVDS DIFFRESISTOR=100 BANK_VCCIO=2.5; + + -- 2.43.0