From be0faab90a06a6e8865a32b22cddaff9f9bc5685 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Tue, 18 Jun 2019 11:58:30 +0200 Subject: [PATCH] update Mimosis Design with automatic setting of delay on inputs --- mimosis/compile.pl | 1 + mimosis/config.vhd | 121 +++++ mimosis/cores/mimosis_inp.fdc | 2 + mimosis/cores/mimosis_inp.lpc | 66 +++ mimosis/cores/mimosis_inp.sbx | 322 ++++++++++++ mimosis/cores/mimosis_inp.vhd | 205 ++++++++ mimosis/cores/pll_200_160/pll_200_160.fdc | 2 + mimosis/cores/pll_200_160/pll_200_160.lpc | 93 ++++ mimosis/cores/pll_200_160/pll_200_160.sbx | 430 ++++++++++++++++ mimosis/cores/pll_200_160/pll_200_160.vhd | 71 +++ mimosis/cores/testout.lpc | 66 +++ mimosis/cores/testout.sbx | 322 ++++++++++++ mimosis/cores/testout.vhd | 219 ++++++++ mimosis/par.p2t | 69 +++ mimosis/trb5sc_mimosis.lpf | 1 + mimosis/trb5sc_mimosis.prj | 202 ++++++++ mimosis/trb5sc_mimosis.vhd | 600 ++++++++++++++++++++++ 17 files changed, 2792 insertions(+) create mode 120000 mimosis/compile.pl create mode 100644 mimosis/config.vhd create mode 100644 mimosis/cores/mimosis_inp.fdc create mode 100644 mimosis/cores/mimosis_inp.lpc create mode 100644 mimosis/cores/mimosis_inp.sbx create mode 100644 mimosis/cores/mimosis_inp.vhd create mode 100644 mimosis/cores/pll_200_160/pll_200_160.fdc create mode 100644 mimosis/cores/pll_200_160/pll_200_160.lpc create mode 100644 mimosis/cores/pll_200_160/pll_200_160.sbx create mode 100644 mimosis/cores/pll_200_160/pll_200_160.vhd create mode 100644 mimosis/cores/testout.lpc create mode 100644 mimosis/cores/testout.sbx create mode 100644 mimosis/cores/testout.vhd create mode 100644 mimosis/par.p2t create mode 100644 mimosis/trb5sc_mimosis.lpf create mode 100644 mimosis/trb5sc_mimosis.prj create mode 100644 mimosis/trb5sc_mimosis.vhd diff --git a/mimosis/compile.pl b/mimosis/compile.pl new file mode 120000 index 0000000..8a19aa6 --- /dev/null +++ b/mimosis/compile.pl @@ -0,0 +1 @@ +../../trb3sc/scripts/compile.pl \ No newline at end of file diff --git a/mimosis/config.vhd b/mimosis/config.vhd new file mode 100644 index 0000000..b60ab95 --- /dev/null +++ b/mimosis/config.vhd @@ -0,0 +1,121 @@ +library ieee; +USE IEEE.std_logic_1164.ALL; +use ieee.numeric_std.all; +use work.trb_net_std.all; + +package config is + + +------------------------------------------------------------------------------ +--Begin of design configuration +------------------------------------------------------------------------------ + + +--set to 0 for backplane serdes, set to 1 for SFP serdes + constant SERDES_NUM : integer := 1; + +--TDC settings + constant FPGA_TYPE : integer := 5; --3: ECP3, 5: ECP5 + constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement + constant NUM_TDC_CHANNELS : integer range 1 to 65 := 33; -- number of tdc channels per module + constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons + constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3 + -- 0: single edge only, + -- 1: same channel, + -- 2: alternating channels, + -- 3: same channel with stretcher + constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size + -- mode: 0, 1, 2, 3, 7 + -- size: 32, 64, 96, 128, dyn + constant TDC_DATA_FORMAT : integer range 0 to 3 := 0; --type of data format for the TDC + -- 0: Single fine time as the sum of the two transitions + -- 1: Double fine time, individual transitions + -- 13: Debug - fine time + (if 0x3ff full chain) + -- 14: Debug - single fine time and the ROM addresses for the two transitions + -- 15: Debug - complete carry chain dump + + constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 13; -- size of the event buffer, 2**N + constant EVENT_MAX_SIZE : integer := 500; --maximum event size. Must not exceed EVENT_BUFFER_SIZE/2 + +--Runs with 120 MHz instead of 100 MHz + constant USE_120_MHZ : integer := c_NO; + +--Use sync mode, RX clock for all parts of the FPGA + constant USE_RXCLOCK : integer := c_NO; + +--Address settings + constant INIT_ADDRESS : std_logic_vector := x"F575"; + constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"82"; + + constant INCLUDE_UART : integer := c_NO; --300 slices + constant INCLUDE_SPI : integer := c_NO; --300 slices + constant INCLUDE_LCD : integer := c_NO; --800 slices + constant INCLUDE_DEBUG_INTERFACE: integer := c_NO; --300 slices + + --input monitor and trigger generation logic + constant INCLUDE_TRIGGER_LOGIC : integer := c_NO; --400 slices @32->2 + constant INCLUDE_STATISTICS : integer := c_NO; --1300 slices, 1 RAM @32 + constant TRIG_GEN_INPUT_NUM : integer := 32; + constant TRIG_GEN_OUTPUT_NUM : integer := 4; + constant MONITOR_INPUT_NUM : integer := 32; + +------------------------------------------------------------------------------ +--End of design configuration +------------------------------------------------------------------------------ + + + type data_t is array (0 to 1023) of std_logic_vector(7 downto 0); + constant LCD_DATA : data_t := (others => x"00"); + +------------------------------------------------------------------------------ +--Select settings by configuration +------------------------------------------------------------------------------ + type intlist_t is array(0 to 7) of integer; + type hw_info_t is array(0 to 7) of unsigned(31 downto 0); + constant HW_INFO_BASE : unsigned(31 downto 0) := x"A5000000"; + + constant CLOCK_FREQUENCY_ARR : intlist_t := (100,120, others => 0); + constant MEDIA_FREQUENCY_ARR : intlist_t := (200,240, others => 0); + + --declare constants, filled in body + constant HARDWARE_INFO : std_logic_vector(31 downto 0); + constant CLOCK_FREQUENCY : integer; + constant MEDIA_FREQUENCY : integer; + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0); + + +end; + +package body config is +--compute correct configuration mode + + constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector( HW_INFO_BASE ); + constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_120_MHZ); + constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_120_MHZ); + +function generateIncludedFeatures return std_logic_vector is + variable t : std_logic_vector(63 downto 0); + begin + t := (others => '0'); + t(63 downto 56) := std_logic_vector(to_unsigned(2,8)); --table version 1 + + t(7 downto 0) := std_logic_vector(to_unsigned(1,8)); + t(11 downto 8) := std_logic_vector(to_unsigned(DOUBLE_EDGE_TYPE,4)); + t(14 downto 12) := std_logic_vector(to_unsigned(RING_BUFFER_SIZE,3)); + t(15) := '1'; --TDC + t(17 downto 16) := std_logic_vector(to_unsigned(NUM_TDC_MODULES-1,2)); + + t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1)); + t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1)); + t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1)); + t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1)); + t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4)); + t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1)); + t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1)); + t(54 downto 54) := "0";--std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1)); + return t; + end function; + + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures; + +end package body; diff --git a/mimosis/cores/mimosis_inp.fdc b/mimosis/cores/mimosis_inp.fdc new file mode 100644 index 0000000..6fbcac9 --- /dev/null +++ b/mimosis/cores/mimosis_inp.fdc @@ -0,0 +1,2 @@ +###==== Start Configuration + diff --git a/mimosis/cores/mimosis_inp.lpc b/mimosis/cores/mimosis_inp.lpc new file mode 100644 index 0000000..30827bf --- /dev/null +++ b/mimosis/cores/mimosis_inp.lpc @@ -0,0 +1,66 @@ +[Device] +Family=ecp5um +PartType=LFE5UM-85F +PartName=LFE5UM-85F-8BG756C +SpeedGrade=8 +Package=CABGA756 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=DDR_GENERIC +CoreRevision=6.0 +ModuleName=mimosis_inp +SourceFormat=vhdl +ParameterFileVersion=1.0 +Date=06/03/2019 +Time=14:45:56 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +mode=Receive +trioddr=0 +io_type=LVDS +width=8 +freq_in=160 +bandwidth=2560 +aligned=Edge-to-Edge +pre-configuration=DISABLED +mode2=Receive +trioddr2=0 +io_type2=LVDS +freq_in2=160 +gear=2:1 +aligned2=Centered +width2=8 +DataLane=By Lane +EnECLK=0 +Interface=GDDRX1_RX.SCLK.Centered +Delay=Dynamic User Defined +DelVal=1 +EnInEdge= +NumEdge=BOTH +EnDynamic=0 +GenPll=0 +Freq= +AFreq= +Reference=0 +IOBUF= +ReceiverSync=0 +EnDynamicAlign= +DynamicAlign= +MIPIFilter=0 +enClkIBuf=0 +ClkIBuf=LVDS + +[Command] +cmd_line= -w -n mimosis_inp -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type iol -mode Receive -io_type LVDS -width 8 -freq_in 160 -gear 2 -del 1 -dynamic_delay -data_lane diff --git a/mimosis/cores/mimosis_inp.sbx b/mimosis/cores/mimosis_inp.sbx new file mode 100644 index 0000000..e0c4c05 --- /dev/null +++ b/mimosis/cores/mimosis_inp.sbx @@ -0,0 +1,322 @@ + + + + Lattice Semiconductor Corporation + LEGACY + DDR_GENERIC + 6.0 + + + Diamond_Simulation + simulation + + ./mimosis_inp.vhd + vhdlSource + + + + Diamond_Synthesis + synthesis + + ./mimosis_inp.vhd + vhdlSource + + + + + + Configuration + none + ${sbp_path}/generate_core.tcl + CONFIG + + + Generation + none + ${sbp_path}/${instance}/generate_core.tcl + GENERATE + + + + + + + + LFE5UM-85F-8BG756C + synplify + 2019-05-31.19:33:04 + 2019-06-03.14:45:58 + 3.10.3.144 + VHDL + + false + false + false + false + false + false + false + false + false + false + LPM + PRIMARY + PRIMARY + false + false + + + + + + Family + ecp5um + + + OperatingCondition + COM + + + Package + CABGA756 + + + PartName + LFE5UM-85F-8BG756C + + + PartType + LFE5UM-85F + + + SpeedGrade + 8 + + + Status + P + + + + CoreName + DDR_GENERIC + + + CoreRevision + 6.0 + + + CoreStatus + Demo + + + CoreType + LPM + + + Date + 06/03/2019 + + + ModuleName + mimosis_inp + + + ParameterFileVersion + 1.0 + + + SourceFormat + vhdl + + + Time + 14:45:56 + + + VendorName + Lattice Semiconductor Corporation + + + + AFreq + + + + ClkIBuf + LVDS + + + DataLane + By Lane + + + DelVal + 1 + + + Delay + Dynamic User Defined + + + Destination + Synplicity + + + DynamicAlign + + + + EDIF + 1 + + + EnDynamic + 0 + + + EnDynamicAlign + + + + EnECLK + 0 + + + EnInEdge + + + + Expression + BusA(0 to 7) + + + Freq + + + + GenPll + 0 + + + IO + 0 + + + IOBUF + + + + Interface + GDDRX1_RX.SCLK.Centered + + + MIPIFilter + 0 + + + NumEdge + BOTH + + + Order + Big Endian [MSB:LSB] + + + ReceiverSync + 0 + + + Reference + 0 + + + VHDL + 1 + + + Verilog + 0 + + + aligned + Edge-to-Edge + + + aligned2 + Centered + + + bandwidth + 2560 + + + enClkIBuf + 0 + + + freq_in + 160 + + + freq_in2 + 160 + + + gear + 2:1 + + + io_type + LVDS + + + io_type2 + LVDS + + + mode + Receive + + + mode2 + Receive + + + pre-configuration + DISABLED + + + trioddr + 0 + + + trioddr2 + 0 + + + width + 8 + + + width2 + 8 + + + + cmd_line + -w -n mimosis_inp -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type iol -mode Receive -io_type LVDS -width 8 -freq_in 160 -gear 2 -del 1 -dynamic_delay -data_lane + + + + + + + LATTICE + LOCAL + mimosis_inp + 1.0 + + + + diff --git a/mimosis/cores/mimosis_inp.vhd b/mimosis/cores/mimosis_inp.vhd new file mode 100644 index 0000000..c460848 --- /dev/null +++ b/mimosis/cores/mimosis_inp.vhd @@ -0,0 +1,205 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.10.3.144 +-- Module Version: 5.8 +--/d/jspc29/lattice/diamond/3.10_x64/ispfpga/bin/lin64/scuba -w -n mimosis_inp -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type iol -mode Receive -io_type LVDS -width 8 -freq_in 160 -gear 2 -del 1 -dynamic_delay -data_lane -fdc /d/jspc22/trb/lattice/sio/mimosis_inp/mimosis_inp.fdc + +-- Mon Jun 3 14:45:58 2019 + +library IEEE; +use IEEE.std_logic_1164.all; +library ecp5um; +use ecp5um.components.all; + +entity mimosis_inp is + port ( + clkin: in std_logic; + reset: in std_logic; + sclk: out std_logic; + data_cflag: out std_logic_vector(7 downto 0); + data_direction: in std_logic_vector(7 downto 0); + data_loadn: in std_logic_vector(7 downto 0); + data_move: in std_logic_vector(7 downto 0); + datain: in std_logic_vector(7 downto 0); + q: out std_logic_vector(15 downto 0)); +end mimosis_inp; + +architecture Structure of mimosis_inp is + + -- internal signal declarations + signal buf_clkin: std_logic; + signal qb7: std_logic; + signal qa7: std_logic; + signal qb6: std_logic; + signal qa6: std_logic; + signal qb5: std_logic; + signal qa5: std_logic; + signal qb4: std_logic; + signal qa4: std_logic; + signal qb3: std_logic; + signal qa3: std_logic; + signal qb2: std_logic; + signal qa2: std_logic; + signal qb1: std_logic; + signal qa1: std_logic; + signal qb0: std_logic; + signal qa0: std_logic; + signal sclk_t: std_logic; + signal dataini_t7: std_logic; + signal dataini_t6: std_logic; + signal dataini_t5: std_logic; + signal dataini_t4: std_logic; + signal dataini_t3: std_logic; + signal dataini_t2: std_logic; + signal dataini_t1: std_logic; + signal dataini_t0: std_logic; + signal buf_dataini7: std_logic; + signal buf_dataini6: std_logic; + signal buf_dataini5: std_logic; + signal buf_dataini4: std_logic; + signal buf_dataini3: std_logic; + signal buf_dataini2: std_logic; + signal buf_dataini1: std_logic; + signal buf_dataini0: std_logic; + + attribute IO_TYPE : string; +-- attribute IO_TYPE of Inst3_IB : label is "LVDS"; + attribute IO_TYPE of Inst1_IB7 : label is "LVDS"; + attribute IO_TYPE of Inst1_IB6 : label is "LVDS"; + attribute IO_TYPE of Inst1_IB5 : label is "LVDS"; + attribute IO_TYPE of Inst1_IB4 : label is "LVDS"; + attribute IO_TYPE of Inst1_IB3 : label is "LVDS"; + attribute IO_TYPE of Inst1_IB2 : label is "LVDS"; + attribute IO_TYPE of Inst1_IB1 : label is "LVDS"; + attribute IO_TYPE of Inst1_IB0 : label is "LVDS"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements +-- Inst3_IB: IB +-- port map (I=>clkin, O=>buf_clkin); +buf_clkin <= clkin; + + Inst2_IDDRX1F7: IDDRX1F + port map (D=>dataini_t7, SCLK=>sclk_t, RST=>reset, Q0=>qa7, + Q1=>qb7); + + Inst2_IDDRX1F6: IDDRX1F + port map (D=>dataini_t6, SCLK=>sclk_t, RST=>reset, Q0=>qa6, + Q1=>qb6); + + Inst2_IDDRX1F5: IDDRX1F + port map (D=>dataini_t5, SCLK=>sclk_t, RST=>reset, Q0=>qa5, + Q1=>qb5); + + Inst2_IDDRX1F4: IDDRX1F + port map (D=>dataini_t4, SCLK=>sclk_t, RST=>reset, Q0=>qa4, + Q1=>qb4); + + Inst2_IDDRX1F3: IDDRX1F + port map (D=>dataini_t3, SCLK=>sclk_t, RST=>reset, Q0=>qa3, + Q1=>qb3); + + Inst2_IDDRX1F2: IDDRX1F + port map (D=>dataini_t2, SCLK=>sclk_t, RST=>reset, Q0=>qa2, + Q1=>qb2); + + Inst2_IDDRX1F1: IDDRX1F + port map (D=>dataini_t1, SCLK=>sclk_t, RST=>reset, Q0=>qa1, + Q1=>qb1); + + Inst2_IDDRX1F0: IDDRX1F + port map (D=>dataini_t0, SCLK=>sclk_t, RST=>reset, Q0=>qa0, + Q1=>qb0); + + udel_dataini7: DELAYF + generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED") + port map (A=>buf_dataini7, LOADN=>data_loadn(7), + MOVE=>data_move(7), DIRECTION=>data_direction(7), + Z=>dataini_t7, CFLAG=>data_cflag(7)); + + udel_dataini6: DELAYF + generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED") + port map (A=>buf_dataini6, LOADN=>data_loadn(6), + MOVE=>data_move(6), DIRECTION=>data_direction(6), + Z=>dataini_t6, CFLAG=>data_cflag(6)); + + udel_dataini5: DELAYF + generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED") + port map (A=>buf_dataini5, LOADN=>data_loadn(5), + MOVE=>data_move(5), DIRECTION=>data_direction(5), + Z=>dataini_t5, CFLAG=>data_cflag(5)); + + udel_dataini4: DELAYF + generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED") + port map (A=>buf_dataini4, LOADN=>data_loadn(4), + MOVE=>data_move(4), DIRECTION=>data_direction(4), + Z=>dataini_t4, CFLAG=>data_cflag(4)); + + udel_dataini3: DELAYF + generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED") + port map (A=>buf_dataini3, LOADN=>data_loadn(3), + MOVE=>data_move(3), DIRECTION=>data_direction(3), + Z=>dataini_t3, CFLAG=>data_cflag(3)); + + udel_dataini2: DELAYF + generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED") + port map (A=>buf_dataini2, LOADN=>data_loadn(2), + MOVE=>data_move(2), DIRECTION=>data_direction(2), + Z=>dataini_t2, CFLAG=>data_cflag(2)); + + udel_dataini1: DELAYF + generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED") + port map (A=>buf_dataini1, LOADN=>data_loadn(1), + MOVE=>data_move(1), DIRECTION=>data_direction(1), + Z=>dataini_t1, CFLAG=>data_cflag(1)); + + udel_dataini0: DELAYF + generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED") + port map (A=>buf_dataini0, LOADN=>data_loadn(0), + MOVE=>data_move(0), DIRECTION=>data_direction(0), + Z=>dataini_t0, CFLAG=>data_cflag(0)); + + Inst1_IB7: IB + port map (I=>datain(7), O=>buf_dataini7); + + Inst1_IB6: IB + port map (I=>datain(6), O=>buf_dataini6); + + Inst1_IB5: IB + port map (I=>datain(5), O=>buf_dataini5); + + Inst1_IB4: IB + port map (I=>datain(4), O=>buf_dataini4); + + Inst1_IB3: IB + port map (I=>datain(3), O=>buf_dataini3); + + Inst1_IB2: IB + port map (I=>datain(2), O=>buf_dataini2); + + Inst1_IB1: IB + port map (I=>datain(1), O=>buf_dataini1); + + Inst1_IB0: IB + port map (I=>datain(0), O=>buf_dataini0); + + sclk <= sclk_t; + q(15) <= qb7; + q(14) <= qa7; + q(13) <= qb6; + q(12) <= qa6; + q(11) <= qb5; + q(10) <= qa5; + q(9) <= qb4; + q(8) <= qa4; + q(7) <= qb3; + q(6) <= qa3; + q(5) <= qb2; + q(4) <= qa2; + q(3) <= qb1; + q(2) <= qa1; + q(1) <= qb0; + q(0) <= qa0; + sclk_t <= buf_clkin; +end Structure; diff --git a/mimosis/cores/pll_200_160/pll_200_160.fdc b/mimosis/cores/pll_200_160/pll_200_160.fdc new file mode 100644 index 0000000..6fbcac9 --- /dev/null +++ b/mimosis/cores/pll_200_160/pll_200_160.fdc @@ -0,0 +1,2 @@ +###==== Start Configuration + diff --git a/mimosis/cores/pll_200_160/pll_200_160.lpc b/mimosis/cores/pll_200_160/pll_200_160.lpc new file mode 100644 index 0000000..ab48278 --- /dev/null +++ b/mimosis/cores/pll_200_160/pll_200_160.lpc @@ -0,0 +1,93 @@ +[Device] +Family=ecp5um +PartType=LFE5UM-85F +PartName=LFE5UM-85F-8BG756C +SpeedGrade=8 +Package=CABGA756 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PLL +CoreRevision=5.8 +ModuleName=pll_200_160 +SourceFormat=vhdl +ParameterFileVersion=1.0 +Date=06/04/2019 +Time=11:21:53 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +CLKI_FREQ=200 +CLKI_DIV=5 +ENABLE_HBW=DISABLED +REFERENCE=0 +IOBUF=LVDS +CLKOP_FREQ=160 +CLKOP_TOL=0.0 +CLKOP_DIV=4 +CLKOP_ACTUAL_FREQ=160.000000 +CLKOP_MUXA=DISABLED +CLKOS_Enable=DISABLED +CLKOS_FREQ=100.00 +CLKOS_TOL=0.0 +CLKOS_DIV=1 +CLKOS_ACTUAL_FREQ= +CLKOS_MUXB=DISABLED +CLKOS2_Enable=DISABLED +CLKOS2_FREQ=100.00 +CLKOS2_TOL=0.0 +CLKOS2_DIV=1 +CLKOS2_ACTUAL_FREQ= +CLKOS2_MUXC=DISABLED +CLKOS3_Enable=DISABLED +CLKOS3_FREQ=100.00 +CLKOS3_TOL=0.0 +CLKOS3_DIV=1 +CLKOS3_ACTUAL_FREQ= +CLKOS3_MUXD=DISABLED +FEEDBK_PATH=CLKOP +CLKFB_DIV=4 +FRACN_ENABLE=DISABLED +FRACN_DIV= +VCO_RATE=640.000 +PLL_BW=4.655 +CLKOP_DPHASE=0 +CLKOP_APHASE=0.00 +CLKOP_TRIM_POL=Rising +CLKOP_TRIM_DELAY=0 +CLKOS_DPHASE=0 +CLKOS_APHASE=0.00 +CLKOS_TRIM_POL=Rising +CLKOS_TRIM_DELAY=0 +CLKOS2_DPHASE=0 +CLKOS2_APHASE=0.00 +CLKOS2_TRIM_POL=Rising +CLKOS2_TRIM_DELAY=0 +CLKOS3_DPHASE=0 +CLKOS3_APHASE=0.00 +CLKOS3_TRIM_POL=Rising +CLKOS3_TRIM_DELAY=0 +CLKSEL_ENA=DISABLED +DPHASE_SOURCE=STATIC +ENABLE_CLKOP=DISABLED +ENABLE_CLKOS=DISABLED +ENABLE_CLKOS2=DISABLED +ENABLE_CLKOS3=DISABLED +STDBY_ENABLE=DISABLED +PLLRST_ENA=DISABLED +PLL_LOCK_MODE=DISABLED +PLL_LOCK_STK=DISABLED +PLL_USE_SMI=DISABLED + +[Command] +cmd_line= -w -n pll_200_160 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 200 -fclkop 160 -fclkop_tol 0.0 -phase_cntl STATIC -fb_mode 1 diff --git a/mimosis/cores/pll_200_160/pll_200_160.sbx b/mimosis/cores/pll_200_160/pll_200_160.sbx new file mode 100644 index 0000000..b1c56f9 --- /dev/null +++ b/mimosis/cores/pll_200_160/pll_200_160.sbx @@ -0,0 +1,430 @@ + + + + Lattice Semiconductor Corporation + LEGACY + PLL + 5.8 + + + Diamond_Simulation + simulation + + ./pll_200_160.vhd + vhdlSource + + + + Diamond_Synthesis + synthesis + + ./pll_200_160.vhd + vhdlSource + + + + + + Configuration + none + ${sbp_path}/generate_core.tcl + CONFIG + + + Generation + none + ${sbp_path}/${instance}/generate_core.tcl + GENERATE + + + + + + + + LFE5UM-85F-8BG756C + synplify + 2019-06-04.11:21:55 + 2019-06-04.11:21:55 + 3.10.3.144 + VHDL + + false + false + false + false + false + false + false + false + false + false + LPM + PRIMARY + PRIMARY + false + false + + + + + + Family + ecp5um + + + OperatingCondition + COM + + + Package + CABGA756 + + + PartName + LFE5UM-85F-8BG756C + + + PartType + LFE5UM-85F + + + SpeedGrade + 8 + + + Status + P + + + + CoreName + PLL + + + CoreRevision + 5.8 + + + CoreStatus + Demo + + + CoreType + LPM + + + Date + 06/04/2019 + + + ModuleName + pll_200_160 + + + ParameterFileVersion + 1.0 + + + SourceFormat + vhdl + + + Time + 11:21:53 + + + VendorName + Lattice Semiconductor Corporation + + + + CLKFB_DIV + 4 + + + CLKI_DIV + 5 + + + CLKI_FREQ + 200 + + + CLKOP_ACTUAL_FREQ + 160.000000 + + + CLKOP_APHASE + 0.00 + + + CLKOP_DIV + 4 + + + CLKOP_DPHASE + 0 + + + CLKOP_FREQ + 160 + + + CLKOP_MUXA + DISABLED + + + CLKOP_TOL + 0.0 + + + CLKOP_TRIM_DELAY + 0 + + + CLKOP_TRIM_POL + Rising + + + CLKOS2_ACTUAL_FREQ + + + + CLKOS2_APHASE + 0.00 + + + CLKOS2_DIV + 1 + + + CLKOS2_DPHASE + 0 + + + CLKOS2_Enable + DISABLED + + + CLKOS2_FREQ + 100.00 + + + CLKOS2_MUXC + DISABLED + + + CLKOS2_TOL + 0.0 + + + CLKOS2_TRIM_DELAY + 0 + + + CLKOS2_TRIM_POL + Rising + + + CLKOS3_ACTUAL_FREQ + + + + CLKOS3_APHASE + 0.00 + + + CLKOS3_DIV + 1 + + + CLKOS3_DPHASE + 0 + + + CLKOS3_Enable + DISABLED + + + CLKOS3_FREQ + 100.00 + + + CLKOS3_MUXD + DISABLED + + + CLKOS3_TOL + 0.0 + + + CLKOS3_TRIM_DELAY + 0 + + + CLKOS3_TRIM_POL + Rising + + + CLKOS_ACTUAL_FREQ + + + + CLKOS_APHASE + 0.00 + + + CLKOS_DIV + 1 + + + CLKOS_DPHASE + 0 + + + CLKOS_Enable + DISABLED + + + CLKOS_FREQ + 100.00 + + + CLKOS_MUXB + DISABLED + + + CLKOS_TOL + 0.0 + + + CLKOS_TRIM_DELAY + 0 + + + CLKOS_TRIM_POL + Rising + + + CLKSEL_ENA + DISABLED + + + DPHASE_SOURCE + STATIC + + + Destination + Synplicity + + + EDIF + 1 + + + ENABLE_CLKOP + DISABLED + + + ENABLE_CLKOS + DISABLED + + + ENABLE_CLKOS2 + DISABLED + + + ENABLE_CLKOS3 + DISABLED + + + ENABLE_HBW + DISABLED + + + Expression + BusA(0 to 7) + + + FEEDBK_PATH + CLKOP + + + FRACN_DIV + + + + FRACN_ENABLE + DISABLED + + + IO + 0 + + + IOBUF + LVDS + + + Order + Big Endian [MSB:LSB] + + + PLLRST_ENA + DISABLED + + + PLL_BW + 4.655 + + + PLL_LOCK_MODE + DISABLED + + + PLL_LOCK_STK + DISABLED + + + PLL_USE_SMI + DISABLED + + + REFERENCE + 0 + + + STDBY_ENABLE + DISABLED + + + VCO_RATE + 640.000 + + + VHDL + 1 + + + Verilog + 0 + + + + cmd_line + -w -n pll_200_160 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 200 -fclkop 160 -fclkop_tol 0.0 -phase_cntl STATIC -fb_mode 1 + + + + + + + LATTICE + LOCAL + pll_200_160 + 1.0 + + + + diff --git a/mimosis/cores/pll_200_160/pll_200_160.vhd b/mimosis/cores/pll_200_160/pll_200_160.vhd new file mode 100644 index 0000000..dc3853d --- /dev/null +++ b/mimosis/cores/pll_200_160/pll_200_160.vhd @@ -0,0 +1,71 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.10.3.144 +-- Module Version: 5.7 +--/d/jspc29/lattice/diamond/3.10_x64/ispfpga/bin/lin64/scuba -w -n pll_200_160 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 200 -fclkop 160 -fclkop_tol 0.0 -phase_cntl STATIC -fb_mode 1 -fdc /d/jspc22/trb/git/trb5sc/mimosis/project/pll_200_160/pll_200_160.fdc + +-- Tue Jun 4 11:21:55 2019 + +library IEEE; +use IEEE.std_logic_1164.all; +library ecp5um; +use ecp5um.components.all; + +entity pll_200_160 is + port ( + CLKI: in std_logic; + CLKOP: out std_logic); +end pll_200_160; + +architecture Structure of pll_200_160 is + + -- internal signal declarations + signal REFCLK: std_logic; + signal LOCK: std_logic; + signal CLKOP_t: std_logic; + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + + attribute FREQUENCY_PIN_CLKOP : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute ICP_CURRENT : string; + attribute LPF_RESISTOR : string; + attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "160.000000"; + attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000"; + attribute ICP_CURRENT of PLLInst_0 : label is "12"; + attribute LPF_RESISTOR of PLLInst_0 : label is "8"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + PLLInst_0: EHXPLLL + generic map (PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED", + STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED", + CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 0, CLKOS2_FPHASE=> 0, + CLKOS2_CPHASE=> 0, CLKOS_FPHASE=> 0, CLKOS_CPHASE=> 0, + CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 3, PLL_LOCK_MODE=> 0, + CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "FALLING", + CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "FALLING", + OUTDIVIDER_MUXD=> "DIVD", CLKOS3_ENABLE=> "DISABLED", + OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "DISABLED", + OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "DISABLED", + OUTDIVIDER_MUXA=> "DIVA", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 1, + CLKOS2_DIV=> 1, CLKOS_DIV=> 1, CLKOP_DIV=> 4, CLKFB_DIV=> 4, + CLKI_DIV=> 5, FEEDBK_PATH=> "CLKOP") + port map (CLKI=>CLKI, CLKFB=>CLKOP_t, PHASESEL1=>scuba_vlo, + PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo, + PHASESTEP=>scuba_vlo, PHASELOADREG=>scuba_vlo, + STDBY=>scuba_vlo, PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo, + ENCLKOP=>scuba_vlo, ENCLKOS=>scuba_vlo, ENCLKOS2=>scuba_vlo, + ENCLKOS3=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>open, + CLKOS2=>open, CLKOS3=>open, LOCK=>LOCK, INTLOCK=>open, + REFCLK=>REFCLK, CLKINTFB=>open); + + CLKOP <= CLKOP_t; +end Structure; diff --git a/mimosis/cores/testout.lpc b/mimosis/cores/testout.lpc new file mode 100644 index 0000000..c705e50 --- /dev/null +++ b/mimosis/cores/testout.lpc @@ -0,0 +1,66 @@ +[Device] +Family=ecp5um +PartType=LFE5UM-85F +PartName=LFE5UM-85F-8BG756C +SpeedGrade=8 +Package=CABGA756 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=DDR_GENERIC +CoreRevision=6.0 +ModuleName=testout +SourceFormat=vhdl +ParameterFileVersion=1.0 +Date=06/05/2019 +Time=14:55:39 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +mode=Transmit +trioddr=0 +io_type=LVDS +width=8 +freq_in=160 +bandwidth=2560 +aligned=Edge-to-Edge +pre-configuration=DISABLED +mode2=Transmit +trioddr2=0 +io_type2=LVDS +freq_in2=160 +gear=2:1 +aligned2=Edge-to-Edge +width2=8 +DataLane=By Lane +EnECLK=0 +Interface=GDDRX1_TX.SCLK.Aligned +Delay=Dynamic User Defined +DelVal=1 +EnInEdge= +NumEdge=BOTH +EnDynamic=0 +GenPll=0 +Freq= +AFreq= +Reference=0 +IOBUF= +ReceiverSync=0 +EnDynamicAlign= +DynamicAlign= +MIPIFilter=0 +enClkIBuf=0 +ClkIBuf=LVDS + +[Command] +cmd_line= -w -n testout -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type iol -mode Transmit -io_type LVDS -width 8 -freq_in 160 -gear 2 -aligned -del 1 -dynamic_delay -data_lane diff --git a/mimosis/cores/testout.sbx b/mimosis/cores/testout.sbx new file mode 100644 index 0000000..7b87c2e --- /dev/null +++ b/mimosis/cores/testout.sbx @@ -0,0 +1,322 @@ + + + + Lattice Semiconductor Corporation + LEGACY + DDR_GENERIC + 6.0 + + + Diamond_Simulation + simulation + + ./testout.vhd + vhdlSource + + + + Diamond_Synthesis + synthesis + + ./testout.vhd + vhdlSource + + + + + + Configuration + none + ${sbp_path}/generate_core.tcl + CONFIG + + + Generation + none + ${sbp_path}/${instance}/generate_core.tcl + GENERATE + + + + + + + + LFE5UM-85F-8BG756C + synplify + 2019-06-05.14:55:41 + 2019-06-05.14:55:41 + 3.10.3.144 + VHDL + + false + false + false + false + false + false + false + false + false + false + LPM + PRIMARY + PRIMARY + false + false + + + + + + Family + ecp5um + + + OperatingCondition + COM + + + Package + CABGA756 + + + PartName + LFE5UM-85F-8BG756C + + + PartType + LFE5UM-85F + + + SpeedGrade + 8 + + + Status + P + + + + CoreName + DDR_GENERIC + + + CoreRevision + 6.0 + + + CoreStatus + Demo + + + CoreType + LPM + + + Date + 06/05/2019 + + + ModuleName + testout + + + ParameterFileVersion + 1.0 + + + SourceFormat + vhdl + + + Time + 14:55:39 + + + VendorName + Lattice Semiconductor Corporation + + + + AFreq + + + + ClkIBuf + LVDS + + + DataLane + By Lane + + + DelVal + 1 + + + Delay + Dynamic User Defined + + + Destination + Synplicity + + + DynamicAlign + + + + EDIF + 1 + + + EnDynamic + 0 + + + EnDynamicAlign + + + + EnECLK + 0 + + + EnInEdge + + + + Expression + BusA(0 to 7) + + + Freq + + + + GenPll + 0 + + + IO + 0 + + + IOBUF + + + + Interface + GDDRX1_TX.SCLK.Aligned + + + MIPIFilter + 0 + + + NumEdge + BOTH + + + Order + Big Endian [MSB:LSB] + + + ReceiverSync + 0 + + + Reference + 0 + + + VHDL + 1 + + + Verilog + 0 + + + aligned + Edge-to-Edge + + + aligned2 + Edge-to-Edge + + + bandwidth + 2560 + + + enClkIBuf + 0 + + + freq_in + 160 + + + freq_in2 + 160 + + + gear + 2:1 + + + io_type + LVDS + + + io_type2 + LVDS + + + mode + Transmit + + + mode2 + Transmit + + + pre-configuration + DISABLED + + + trioddr + 0 + + + trioddr2 + 0 + + + width + 8 + + + width2 + 8 + + + + cmd_line + -w -n testout -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type iol -mode Transmit -io_type LVDS -width 8 -freq_in 160 -gear 2 -aligned -del 1 -dynamic_delay -data_lane + + + + + + + LATTICE + LOCAL + testout + 1.0 + + + + diff --git a/mimosis/cores/testout.vhd b/mimosis/cores/testout.vhd new file mode 100644 index 0000000..7c1451c --- /dev/null +++ b/mimosis/cores/testout.vhd @@ -0,0 +1,219 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.10.3.144 +-- Module Version: 5.8 +--/d/jspc29/lattice/diamond/3.10_x64/ispfpga/bin/lin64/scuba -w -n testout -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type iol -mode Transmit -io_type LVDS -width 8 -freq_in 160 -gear 2 -aligned -del 1 -dynamic_delay -data_lane -fdc /d/jspc22/trb/lattice/sio/testout/testout.fdc + +-- Wed Jun 5 14:55:41 2019 + +library IEEE; +use IEEE.std_logic_1164.all; +library ecp5um; +use ecp5um.components.all; + +entity testout is + port ( + clkout: out std_logic; + refclk: in std_logic; + reset: in std_logic; + data: in std_logic_vector(15 downto 0); + data_cflag: out std_logic_vector(7 downto 0); + data_direction: in std_logic_vector(7 downto 0); + data_loadn: in std_logic_vector(7 downto 0); + data_move: in std_logic_vector(7 downto 0); + dout: out std_logic_vector(7 downto 0)); +end testout; + +architecture Structure of testout is + + -- internal signal declarations + signal db7: std_logic; + signal da7: std_logic; + signal db6: std_logic; + signal da6: std_logic; + signal db5: std_logic; + signal da5: std_logic; + signal db4: std_logic; + signal da4: std_logic; + signal db3: std_logic; + signal da3: std_logic; + signal db2: std_logic; + signal da2: std_logic; + signal db1: std_logic; + signal da1: std_logic; + signal db0: std_logic; + signal da0: std_logic; + signal scuba_vlo: std_logic; + signal scuba_vhi: std_logic; + signal sclk_t: std_logic; + signal clkos: std_logic; + signal clkop: std_logic; + signal buf_clkout: std_logic; + signal douto_t7: std_logic; + signal buf_douto7: std_logic; + signal douto_t6: std_logic; + signal buf_douto6: std_logic; + signal douto_t5: std_logic; + signal buf_douto5: std_logic; + signal douto_t4: std_logic; + signal buf_douto4: std_logic; + signal douto_t3: std_logic; + signal buf_douto3: std_logic; + signal douto_t2: std_logic; + signal buf_douto2: std_logic; + signal douto_t1: std_logic; + signal buf_douto1: std_logic; + signal douto_t0: std_logic; + signal buf_douto0: std_logic; + + attribute IO_TYPE : string; + attribute IO_TYPE of Inst2_OB : label is "LVDS"; + attribute IO_TYPE of Inst1_OB7 : label is "LVDS"; + attribute IO_TYPE of Inst1_OB6 : label is "LVDS"; + attribute IO_TYPE of Inst1_OB5 : label is "LVDS"; + attribute IO_TYPE of Inst1_OB4 : label is "LVDS"; + attribute IO_TYPE of Inst1_OB3 : label is "LVDS"; + attribute IO_TYPE of Inst1_OB2 : label is "LVDS"; + attribute IO_TYPE of Inst1_OB1 : label is "LVDS"; + attribute IO_TYPE of Inst1_OB0 : label is "LVDS"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + Inst4_ODDRX1F7: ODDRX1F + port map (SCLK=>sclk_t, RST=>reset, D0=>da7, D1=>db7, + Q=>buf_douto7); + + Inst4_ODDRX1F6: ODDRX1F + port map (SCLK=>sclk_t, RST=>reset, D0=>da6, D1=>db6, + Q=>buf_douto6); + + Inst4_ODDRX1F5: ODDRX1F + port map (SCLK=>sclk_t, RST=>reset, D0=>da5, D1=>db5, + Q=>buf_douto5); + + Inst4_ODDRX1F4: ODDRX1F + port map (SCLK=>sclk_t, RST=>reset, D0=>da4, D1=>db4, + Q=>buf_douto4); + + Inst4_ODDRX1F3: ODDRX1F + port map (SCLK=>sclk_t, RST=>reset, D0=>da3, D1=>db3, + Q=>buf_douto3); + + Inst4_ODDRX1F2: ODDRX1F + port map (SCLK=>sclk_t, RST=>reset, D0=>da2, D1=>db2, + Q=>buf_douto2); + + Inst4_ODDRX1F1: ODDRX1F + port map (SCLK=>sclk_t, RST=>reset, D0=>da1, D1=>db1, + Q=>buf_douto1); + + Inst4_ODDRX1F0: ODDRX1F + port map (SCLK=>sclk_t, RST=>reset, D0=>da0, D1=>db0, + Q=>buf_douto0); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + Inst3_ODDRX1F: ODDRX1F + port map (SCLK=>clkos, RST=>reset, D0=>scuba_vhi, D1=>scuba_vlo, + Q=>buf_clkout); + + Inst2_OB: OB + port map (I=>buf_clkout, O=>clkout); + + Inst1_OB7: OB + port map (I=>douto_t7, O=>dout(7)); + + Inst1_OB6: OB + port map (I=>douto_t6, O=>dout(6)); + + Inst1_OB5: OB + port map (I=>douto_t5, O=>dout(5)); + + Inst1_OB4: OB + port map (I=>douto_t4, O=>dout(4)); + + Inst1_OB3: OB + port map (I=>douto_t3, O=>dout(3)); + + Inst1_OB2: OB + port map (I=>douto_t2, O=>dout(2)); + + Inst1_OB1: OB + port map (I=>douto_t1, O=>dout(1)); + + Inst1_OB0: OB + port map (I=>douto_t0, O=>dout(0)); + + udel_douto7: DELAYF + generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED") + port map (A=>buf_douto7, LOADN=>data_loadn(7), + MOVE=>data_move(7), DIRECTION=>data_direction(7), + Z=>douto_t7, CFLAG=>data_cflag(7)); + + udel_douto6: DELAYF + generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED") + port map (A=>buf_douto6, LOADN=>data_loadn(6), + MOVE=>data_move(6), DIRECTION=>data_direction(6), + Z=>douto_t6, CFLAG=>data_cflag(6)); + + udel_douto5: DELAYF + generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED") + port map (A=>buf_douto5, LOADN=>data_loadn(5), + MOVE=>data_move(5), DIRECTION=>data_direction(5), + Z=>douto_t5, CFLAG=>data_cflag(5)); + + udel_douto4: DELAYF + generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED") + port map (A=>buf_douto4, LOADN=>data_loadn(4), + MOVE=>data_move(4), DIRECTION=>data_direction(4), + Z=>douto_t4, CFLAG=>data_cflag(4)); + + udel_douto3: DELAYF + generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED") + port map (A=>buf_douto3, LOADN=>data_loadn(3), + MOVE=>data_move(3), DIRECTION=>data_direction(3), + Z=>douto_t3, CFLAG=>data_cflag(3)); + + udel_douto2: DELAYF + generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED") + port map (A=>buf_douto2, LOADN=>data_loadn(2), + MOVE=>data_move(2), DIRECTION=>data_direction(2), + Z=>douto_t2, CFLAG=>data_cflag(2)); + + udel_douto1: DELAYF + generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED") + port map (A=>buf_douto1, LOADN=>data_loadn(1), + MOVE=>data_move(1), DIRECTION=>data_direction(1), + Z=>douto_t1, CFLAG=>data_cflag(1)); + + udel_douto0: DELAYF + generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED") + port map (A=>buf_douto0, LOADN=>data_loadn(0), + MOVE=>data_move(0), DIRECTION=>data_direction(0), + Z=>douto_t0, CFLAG=>data_cflag(0)); + + db7 <= data(15); + da7 <= data(14); + db6 <= data(13); + da6 <= data(12); + db5 <= data(11); + da5 <= data(10); + db4 <= data(9); + da4 <= data(8); + db3 <= data(7); + da3 <= data(6); + db2 <= data(5); + da2 <= data(4); + db1 <= data(3); + da1 <= data(2); + db0 <= data(1); + da0 <= data(0); + sclk_t <= clkop; + clkos <= refclk; + clkop <= refclk; +end Structure; diff --git a/mimosis/par.p2t b/mimosis/par.p2t new file mode 100644 index 0000000..9e4ef4d --- /dev/null +++ b/mimosis/par.p2t @@ -0,0 +1,69 @@ +-w +#-y +-l 5 +#-m nodelist.txt # Controlled by the compile.pl script. +#-n 1 # Controlled by the compile.pl script. +-s 10 +-t 2 +-c 2 +-e 2 +-i 10 +#-exp parPlcInLimit=0 +#-exp parPlcInNeighborSize=1 +#General PAR Command Line Options +# -w With this option, any files generated will overwrite existing files +# (e.g., any .par, .pad files). +# -y Adds the Delay Summary Report in the .par file and creates the delay +# file (in .dly format) at the end of the par run. +# +#PAR Placement Command Line Options +# -l Specifies the effort level of the design from 1 (simplest designs) +# to 5 (most complex designs). +# -m Multi-tasking option. Controlled by the compile.pl script. +# -n Sets the number of iterations performed at the effort level +# specified by the -l option. Controlled by the compile.pl script. +# -s Save the number of best results for this run. +# -t Start placement at the specified cost table. Default is 1. +# +#PAR Routing Command Line Options +# -c Run number of cost-based cleanup passes of the router. +# -e Run number of delay-based cleanup passes of the router on +# completely-routed designs only. +# -i Run a maximum number of passes, stopping earlier only if the routing +# goes to 100 percent completion and all constraints are met. +# +#PAR Explorer Command Line Options +# parCDP Enable the congestion-driven placement (CDP) algorithm. CDP is +# compatible with all Lattice FPGA device families; however, most +# benefit has been demonstrated with benchmarks targeted to ECP5, +# LatticeECP2/M, LatticeECP3, and LatticeXP2 device families. +# parCDR Enable the congestion-driven router (CDR) algorithm. +# Congestion-driven options like parCDR and parCDP can improve +# performance given a design with multiple congestion “hotspots.” The +# Layer > Congestion option of the Design Planner Floorplan View can +# help visualize routing congestion. Large congested areas may prevent +# the options from finding a successful solution. +# CDR is compatible with all Lattice FPGA device families however most +# benefit has been demonstrated with benchmarks targeted to ECP5, +# LatticeECP2/M,LatticeECP3, and LatticeXP2 device families. +# paruseNBR NBR Router or Negotiation-based routing option. Supports all +# FPGA device families except LatticeXP and MachXO. +# When turned on, an alternate routing engine from the traditional +# Rip-up-based routing selection (RBR) is used. This involves an +# iterative routing algorithm that routes connections to achieve +# minimum delay cost. It does so by computing the demand on each +# routing resource and applying cost values per node. It will +# complete when an optimal solution is arrived at or the number of +# iterations is reached. +# parPathBased Path-based placement option. Path-based timing driven +# placement will yield better performance and more +# predictable results in many cases. +# parHold Additional hold time correction option. This option +# forces the router to automatically insert extra wires to compensate for the +# hold time violation. +# parHoldLimit This option allows you to set a limit on the number of +# hold time violations to be processed by the auto hold time correction option +# parHold. +# parPlcInLimit Cannot find in the online help +# parPlcInNeighborSize Cannot find in the online help +-exp parHold=ON:parHoldLimit=10000:parCDP=1:parCDR=1:parPathBased=OFF:paruseNBR=1 diff --git a/mimosis/trb5sc_mimosis.lpf b/mimosis/trb5sc_mimosis.lpf new file mode 100644 index 0000000..10bf0c6 --- /dev/null +++ b/mimosis/trb5sc_mimosis.lpf @@ -0,0 +1 @@ +BLOCK NET "bustdc_tx*"; diff --git a/mimosis/trb5sc_mimosis.prj b/mimosis/trb5sc_mimosis.prj new file mode 100644 index 0000000..6fcd57f --- /dev/null +++ b/mimosis/trb5sc_mimosis.prj @@ -0,0 +1,202 @@ + +# implementation: "workdir" +impl -add workdir -type fpga + +# device options +set_option -technology ECP5UM +set_option -part LFE5UM_85F +set_option -package BG756C +set_option -speed_grade -8 +set_option -part_companion "" + +# compilation/mapping options +set_option -default_enum_encoding sequential +set_option -symbolic_fsm_compiler 1 +set_option -top_module "trb5sc_mimosis" +set_option -resource_sharing false + +# map options +set_option -frequency 120 +set_option -fanout_limit 100 +set_option -disable_io_insertion 0 +set_option -retiming 1 +set_option -pipe 1 +set_option -forcegsr false +set_option -fixgatedclocks 3 +set_option -fixgeneratedclocks 3 +set_option -compiler_compatible true +set_option -multi_file_compilation_unit 1 + +set_option -max_parallel_jobs 3 +#set_option -automatic_compile_point 1 +#set_option -continue_on_error 1 +set_option -resolve_multiple_driver 1 + +# simulation options +set_option -write_verilog 0 +set_option -write_vhdl 1 + +# automatic place and route (vendor) options +set_option -write_apr_constraint 0 + +# set result format/file last +project -result_format "edif" +project -result_file "workdir/trb5sc_mimosis.edf" +set_option log_file "workdir/trb5sc_project.srf" +#implementation attributes + +set_option -vlog_std v2001 +set_option -project_relative_includes 1 +impl -active "workdir" + +#################### + +add_file -vhdl -lib work "workdir/lattice-diamond/cae_library/synthesis/vhdl/ecp5um.vhd" + +#Packages +add_file -vhdl -lib work "workdir/version.vhd" +add_file -vhdl -lib work "config.vhd" +add_file -vhdl -lib work "../../trb3/base/trb3_components.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" + +#Basic Infrastructure +add_file -vhdl -lib work "../../dirich/cores/pll_240_100/pll_240_100.vhd" +add_file -vhdl -lib work "../../dirich/code/clock_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd" +add_file -vhdl -lib work "../../dirich/code/sedcheck.vhd" + + +#Fifos +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net16_fifo_arch.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16bit_dualport/lattice_ecp5_fifo_16bit_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net_fifo_16bit_bram_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x256_oreg/fifo_36x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x2k_oreg/fifo_18x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_9x2k_oreg/fifo_9x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16x16_dualport/lattice_ecp5_fifo_16x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport/lattice_ecp5_fifo_18x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" + + +#Flash & Reload, Tools +add_file -vhdl -lib work "../../trbnet/special/slv_register.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" +add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd" +add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd" +add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd" +add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" +add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd" +add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd" +add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd" + +#SlowControl files +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd" + +#Media interface +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync.vhd" + + +######################################### +#channel 0, backplane +#add_file -vhdl -lib work "../../dirich/cores/serdes_sync_0.vhd" +#add_file -verilog -lib work "../../dirich/cores/serdes_sync_0_softlogic.v" + +#channel 1, SFP +add_file -vhdl -lib work "../cores/serdes_sync_0/serdes_sync_0.vhd" +add_file -verilog -lib work "../cores/serdes_sync_0/serdes_sync_0_softlogic.v" +########################################## + +add_file -vhdl -lib work "../../dirich/cores/pcs.vhd" + +#TrbNet Endpoint +add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd" +add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd" + +add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd" + +add_file -vhdl -lib work "../../trbnet/special/trb_net_i2cwire.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_gstart.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim.vhd" + +add_file -vhdl -lib work "./cores/mimosis_inp.vhd" +add_file -vhdl -lib work "./cores/testout.vhd" +add_file -vhdl -lib work "./cores/pll_200_160/pll_200_160.vhd" + +add_file -vhdl -lib work "./trb5sc_mimosis.vhd" +#add_file -fpga_constraint "./synplify.fdc" + + + diff --git a/mimosis/trb5sc_mimosis.vhd b/mimosis/trb5sc_mimosis.vhd new file mode 100644 index 0000000..66da8c7 --- /dev/null +++ b/mimosis/trb5sc_mimosis.vhd @@ -0,0 +1,600 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.version.all; +use work.config.all; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.med_sync_define.all; + +entity trb5sc_mimosis is + port( + CLK_200 : in std_logic; + CLK_125 : in std_logic; + CLK_EXT : in std_logic; + + TRIG_IN_BACKPL : in std_logic; --Reference Time + TRIG_IN_RJ45 : in std_logic; --Reference Time + IN_SELECT_EXT_CLOCK : in std_logic; + + SPARE : out std_logic_vector(1 downto 0); -- trigger output 2+3 + BACK_GPIO : inout std_logic_vector(3 downto 0); --0: Serdes out, 1: Serdes in, 2,3: trigger output 0+1 + + SFP_TX_DIS : out std_logic; + SFP_LOS : in std_logic; + SFP_MOD_0 : in std_logic; + + --AddOn +-- FE_GPIO : inout std_logic_vector(11 downto 0); +-- FE_CLK : out std_logic_vector( 2 downto 1); +-- FE_DIFF : inout std_logic_vector(63 downto 0); + INP : inout std_logic_vector(63 downto 0); + MOSI : in std_logic; + + --ADC + ADC_SCLK : out std_logic; + ADC_NCS : out std_logic; + ADC_MOSI : out std_logic; + ADC_MISO : in std_logic; + --Flash, Reload + FLASH_SCLK : out std_logic; + FLASH_NCS : out std_logic; + FLASH_MOSI : out std_logic; + FLASH_MISO : in std_logic; + FLASH_HOLD : out std_logic; + FLASH_WP : out std_logic; + PROGRAMN : out std_logic; + --I2C + I2C_SDA : inout std_logic; + I2C_SCL : inout std_logic; + TMP_ALERT : in std_logic; + + --LED + LED : out std_logic_vector(8 downto 1); + LED_SFP_YELLOW : out std_logic; + LED_SFP_GREEN : out std_logic; + LED_SFP_RED : out std_logic; + LED_RJ_GREEN : out std_logic_vector(1 downto 0); + LED_RJ_RED : out std_logic_vector(1 downto 0); + LED_EXT_CLOCK : out std_logic; + + --Other Connectors + TEST : inout std_logic_vector(14 downto 1); + HDR_IO : inout std_logic_vector(15 downto 0) + ); + + + attribute syn_useioff : boolean; + attribute syn_useioff of FLASH_NCS : signal is true; + attribute syn_useioff of FLASH_SCLK : signal is true; + attribute syn_useioff of FLASH_MOSI : signal is true; + attribute syn_useioff of FLASH_MISO : signal is true; + + +end entity; + +architecture arch of trb5sc_mimosis is + attribute syn_keep : boolean; + attribute syn_preserve : boolean; + + signal clk_sys, clk_full, clk_full_osc, clk_160 : std_logic; + signal GSR_N : std_logic; + signal reset_i : std_logic; + signal clear_i : std_logic; + signal trigger_in_i : std_logic; + + + attribute syn_keep of GSR_N : signal is true; + attribute syn_preserve of GSR_N : signal is true; + + signal debug_clock_reset : std_logic_vector(31 downto 0); + signal debug_tools : std_logic_vector(31 downto 0); + + --Media Interface + signal med2int : med2int_array_t(0 to 0); + signal int2med : int2med_array_t(0 to 0); + signal med_stat_debug : std_logic_vector (1*64-1 downto 0); + signal sfp_los_i, sfp_txdis_i, sfp_prsnt_i : std_logic; + + + signal readout_rx : READOUT_RX; + signal readout_tx : readout_tx_array_t(0 to 0); + + signal ctrlbus_tx, bustdc_tx, bussci_tx, bustools_tx, bustc_tx, busthresh_tx, bus_master_in : CTRLBUS_TX; + signal ctrlbus_rx, bustdc_rx, bussci_rx, bustools_rx, bustc_rx, busthresh_rx, bus_master_out : CTRLBUS_RX; + + signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); + signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); + + signal sed_error_i : std_logic; + signal clock_select : std_logic; + signal bus_master_active : std_logic; + signal flash_ncs_i : std_logic; + + signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0); + signal header_io_i : std_logic_vector(10 downto 1); + signal timer : TIMERS; + signal add_reg : std_logic_vector(31 downto 0); + + + + signal clk_rx : std_logic; + signal s_cflag, s_loadn, s_move : std_logic_vector(7 downto 0) := (others => '0'); + signal data_i : std_logic_vector(15 downto 0); + signal inp_i : std_logic_vector(7 downto 0); + + signal out_data : std_logic_vector(15 downto 0); + signal out_i : std_logic_vector( 7 downto 0); + + type state_t is (START, LISTEN, STEP, CALC, SET1, SET2, ENDWAIT); + type state_arrt is array (0 to 7) of state_t; + + type unsigned_arr is array(0 to 7) of unsigned(6 downto 0); + signal sample_good, sample_bad : unsigned_arr := (others => (others => '0')); + signal first_good, first_bad : unsigned_arr := (others => (others => '1')); + signal last_good, last_bad, posi : unsigned_arr := (others => (others => '0')); + + +begin + + +trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and not IN_SELECT_EXT_CLOCK); + + +--------------------------------------------------------------------------- +-- Clock & Reset Handling +--------------------------------------------------------------------------- + THE_CLOCK_RESET : entity work.clock_reset_handler + port map( + CLOCK_IN => CLK_200, + RESET_FROM_NET => med2int(0).stat_op(13), + SEND_RESET_IN => med2int(0).stat_op(15), + + BUS_RX => bustc_rx, + BUS_TX => bustc_tx, + + RESET_OUT => reset_i, + CLEAR_OUT => clear_i, + GSR_OUT => GSR_N, + + REF_CLK_OUT => clk_full, + SYS_CLK_OUT => clk_sys, + RAW_CLK_OUT => clk_full_osc, + + DEBUG_OUT => debug_clock_reset + ); + + + +THE_160_PLL : entity work.pll_200_160 + port map( + CLKI => clk_full_osc, + CLKOP => clk_160 + ); + + + +--------------------------------------------------------------------------- +-- TrbNet Uplink +--------------------------------------------------------------------------- + + THE_MEDIA_INTERFACE : entity work.med_ecp5_sfp_sync + generic map( + SERDES_NUM => 0, + IS_SYNC_SLAVE => c_YES + ) + port map( + CLK_REF_FULL => clk_full_osc, --med2int(0).clk_full, + CLK_INTERNAL_FULL => clk_full_osc, + SYSCLK => clk_sys, + RESET => reset_i, + CLEAR => clear_i, + --Internal Connection + MEDIA_MED2INT => med2int(0), + MEDIA_INT2MED => int2med(0), + + --Sync operation + RX_DLM => open, + RX_DLM_WORD => open, + TX_DLM => open, + TX_DLM_WORD => open, + + --SFP Connection + SD_PRSNT_N_IN => sfp_prsnt_i, + SD_LOS_IN => sfp_los_i, + SD_TXDIS_OUT => sfp_txdis_i, + --Control Interface + BUS_RX => bussci_rx, + BUS_TX => bussci_tx, + -- Status and control port + STAT_DEBUG => med_stat_debug(63 downto 0), + CTRL_DEBUG => open + ); + + gen_sfp_con : if SERDES_NUM = 1 generate + sfp_los_i <= SFP_LOS; + sfp_prsnt_i <= SFP_MOD_0; + SFP_TX_DIS <= sfp_txdis_i; + end generate; + gen_bpl_con : if SERDES_NUM = 0 generate + sfp_los_i <= BACK_GPIO(1); + sfp_prsnt_i <= BACK_GPIO(1); + BACK_GPIO(0) <= sfp_txdis_i; + end generate; + + +--------------------------------------------------------------------------- +-- Endpoint +--------------------------------------------------------------------------- + THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record + generic map ( + ADDRESS_MASK => x"FFFF", + BROADCAST_BITMASK => x"FF", + REGIO_INIT_ENDPOINT_ID => x"0001", + REGIO_USE_1WIRE_INTERFACE => c_I2C, + TIMING_TRIGGER_RAW => c_YES, + --Configure data handler + DATA_INTERFACE_NUMBER => 1, + DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE, + DATA_BUFFER_WIDTH => 32, + DATA_BUFFER_FULL_THRESH => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE, + TRG_RELEASE_AFTER_DATA => c_YES, + HEADER_BUFFER_DEPTH => 9, + HEADER_BUFFER_FULL_THRESH => 2**9-16 + ) + + port map( + -- Misc + CLK => clk_sys, + RESET => reset_i, + CLK_EN => '1', + + -- Media direction port + MEDIA_MED2INT => med2int(0), + MEDIA_INT2MED => int2med(0), + + --Timing trigger in + TRG_TIMING_TRG_RECEIVED_IN => trigger_in_i, + + READOUT_RX => readout_rx, + READOUT_TX => readout_tx, + + --Slow Control Port + REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00 + REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 + BUS_RX => ctrlbus_rx, + BUS_TX => ctrlbus_tx, + BUS_MASTER_IN => bus_master_in, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + + ONEWIRE_INOUT => open, + I2C_SCL => I2C_SCL, + I2C_SDA => I2C_SDA, + --Timing registers + TIMERS_OUT => timer + ); + +--------------------------------------------------------------------------- +-- Bus Handler +--------------------------------------------------------------------------- + + + THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record + generic map( + PORT_NUMBER => 4, + PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"c000", others => x"0000"), + PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 12, others => 0), + PORT_MASK_ENABLE => 1 + ) + port map( + CLK => clk_sys, + RESET => reset_i, + + REGIO_RX => ctrlbus_rx, + REGIO_TX => ctrlbus_tx, + + BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED + BUS_RX(1) => bussci_rx, --SCI Serdes + BUS_RX(2) => bustc_rx, --Clock switch + BUS_RX(3) => bustdc_rx, + BUS_TX(0) => bustools_tx, + BUS_TX(1) => bussci_tx, + BUS_TX(2) => bustc_tx, + BUS_TX(3) => bustdc_tx, + + STAT_DEBUG => open + ); + +--------------------------------------------------------------------------- +-- Control Tools +--------------------------------------------------------------------------- + THE_TOOLS : entity work.trb3sc_tools + port map( + CLK => clk_sys, + RESET => reset_i, + + --Flash & Reload + FLASH_CS => flash_ncs_i, + FLASH_CLK => FLASH_SCLK, + FLASH_IN => FLASH_MISO, + FLASH_OUT => FLASH_MOSI, + PROGRAMN => PROGRAMN, + REBOOT_IN => common_ctrl_reg(15), + --SPI + SPI_CS_OUT => spi_cs, + SPI_MOSI_OUT => spi_mosi, + SPI_MISO_IN => spi_miso, + SPI_CLK_OUT => spi_clk, + --Header + HEADER_IO => open, --HDR_IO(9 downto 0), + ADDITIONAL_REG => add_reg, + --LCD + LCD_DATA_IN => (others => '0'), + --ADC + ADC_CS => ADC_NCS, + ADC_MOSI => ADC_MOSI, + ADC_MISO => ADC_MISO, + ADC_CLK => ADC_SCLK, + --Trigger & Monitor + MONITOR_INPUTS => (others => '0'), + TRIG_GEN_INPUTS => (others => '0'), + TRIG_GEN_OUTPUTS(1 downto 0) => BACK_GPIO(3 downto 2), + TRIG_GEN_OUTPUTS(3 downto 2) => SPARE(1 downto 0), + --SED + SED_ERROR_OUT => sed_error_i, + --Slowcontrol + BUS_RX => bustools_rx, + BUS_TX => bustools_tx, + --Control master for default settings + BUS_MASTER_IN => bus_master_in, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + DEBUG_OUT => debug_tools + ); + + + + FLASH_HOLD <= '1'; + FLASH_WP <= '1'; + + +--------------------------------------------------------------------------- +-- LED +--------------------------------------------------------------------------- + + LED_SFP_GREEN <= not med2int(0).stat_op(9); + LED_SFP_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)); + LED_SFP_YELLOW <= not med2int(0).stat_op(8); + LED <= x"F0"; + LED_RJ_GREEN <= "00"; + LED_RJ_RED <= "11"; + LED_EXT_CLOCK <= IN_SELECT_EXT_CLOCK; + + TEST(13 downto 1) <= (others => '0'); + TEST(14) <= flash_ncs_i; + FLASH_NCS <= flash_ncs_i; + + --------------------------------------------------------------------------- +-- Output stage +--------------------------------------------------------------------------- + THE_OUT : entity work.testout + port map( + clkout => open, + refclk => clk_160, + reset => reset_i, + data => out_data, + data_cflag => open, + data_direction => (others => '0'), + data_loadn => (others => '1'), + data_move => (others => '0'), + dout => out_i + ); + + PROC_OUT : process + variable cnt : integer range 0 to 7; + begin + wait until rising_edge(clk_160); + cnt := cnt + 1; + case cnt is + when 0 => out_data <= x"ffff"; + when 1 => out_data <= x"ffff"; + when 2 => out_data <= x"ffff"; + when 3 => out_data <= x"0000"; + when 4 => out_data <= x"5555"; + when 5 => out_data <= x"5555"; + when 6 => out_data <= x"5555"; + when 7 => out_data <= x"5555"; + end case; + end process; + + +--------------------------------------------------------------------------- +-- Input stage +--------------------------------------------------------------------------- + + + THE_IN : entity work.mimosis_inp + port map ( + clkin=>clk_160, + reset=>reset_i, + sclk=>clk_rx, + data_cflag(7 downto 0)=>s_cflag, + data_direction(7 downto 0)=>(others => '0'), + data_loadn(7 downto 0)=>s_loadn, + data_move(7 downto 0)=>s_move, + datain(7 downto 0)=>inp_i, + q(15 downto 0)=>data_i + ); + + HDR_IO <= data_i; + + inp_i <= INP(14) & INP(12) & INP(10) & INP(8) & INP(6) & INP(4) & INP(2) & INP(0); + INP(30) <= out_i(7); + INP(28) <= out_i(6); + INP(26) <= out_i(5); + INP(24) <= out_i(4); + INP(22) <= out_i(3); + INP(20) <= out_i(2); + INP(18) <= out_i(1); + INP(16) <= out_i(0); + +-- s_move <= add_reg(7 downto 0); + + +gen_finders : for i in 0 to 7 generate + signal timer : unsigned(14 downto 0); + signal state : state_t; + signal count : unsigned(11 downto 0); + signal pos : unsigned(6 downto 0); + signal lastsample : std_logic; + signal train : unsigned(3 downto 0); + signal last : std_logic_vector(1 downto 0); + +begin + PROC_FIND : process begin + wait until rising_edge(clk_160); + s_loadn(i) <= not add_reg(i+16); + + case state is + when START => + timer <= 0; + count <= 0; + s_move(i) <= '0'; + state <= LISTEN; + + when LISTEN => + if timer(timer'left) = '1' then + state <= STEP; + if count >= 2047 and count <= 2049 then + sample_good(i) <= sample_good(i) + 1; + lastsample <= '1'; + if first_good(i) > pos then + first_good(i) <= pos; + end if; + if last_bad(i) < pos and lastsample = '0' then + last_bad(i) <= pos; + end if; + + else + lastsample <= '0'; + sample_bad(i) <= sample_bad(i) + 1; + if first_bad(i) > pos then + first_bad(i) <= pos; + end if; + if last_good(i) < pos and lastsample = '1' then + last_good(i) <= pos; + end if; + end if; + else + timer <= timer + 1; + end if; + + last <= data_i(i*2+1 downto i*2); + + if (data_i(i*2+1 downto i*2) = "01" or data_i(i*2+1 downto i*2) = "10") and + data_i(i*2+1 downto i*2) = last then + train <= train + 1; + else + train <= x"0"; + end if; + + if train = x"3" then + count <= count + 1; + end if; + + + when STEP => + if s_cflag(i) = '0' then + s_move(i) <= '1'; + pos <= pos + 1; + state <= START; + else + state <= CALC; + s_loadn(i) <= '1'; + end if; + + when CALC => + pos <= (('0' & last_bad(i)) + ('0' & first_bad(i)))(7 downto 1) + "1000000"; + posi(i) <= (('0' & last_bad(i)) + ('0' & first_bad(i)))(7 downto 1) + "1000000"; + state <= SET1; + + when SET1 => + state <= SET2; + s_move(i) <= '1'; + + when SET2 => + s_move(i) <= '0'; + if pos = 0 then + state <= ENDWAIT; + else + state <= SET1; + pos <= pos - 1; + end if; + + when ENDWAIT => + + state <= ENDWAIT; + + end case; + + if reset_i = '1' or add_reg(0) = '1' then + state <= START; + pos <= 0; + sample_good(i) <= 0; + sample_bad(i) <= 0; + last_good(i) <= 0; + last_bad(i) <= 0; + first_good(i) <= (others => '1'); + first_bad(i) <= (others => '1'); + end if; + end process; +end generate; + +PROC_REGS : process + variable addr : integer range 0 to 7; +begin + wait until rising_edge(clk_sys); + bustdc_tx.ack <= '0'; + bustdc_tx.unknown <= '0'; + bustdc_tx.nack <= '0'; + bustdc_tx.data <= (others => '0'); + addr := to_integer(unsigned(bustdc_rx.addr(2 downto 0))); + + if bustdc_rx.read = '1' then + bustdc_tx.ack <= '1'; + if bustdc_rx.addr(15 downto 4) = x"000" then + if bustdc_rx.addr(3) = '0' then + bustdc_tx.data(6 downto 0) <= std_logic_vector(sample_good(addr)); + bustdc_tx.data(14 downto 8) <= std_logic_vector(sample_bad(addr)); + bustdc_tx.data(16) <= s_cflag(addr); + bustdc_tx.data(30 downto 24)<= std_logic_vector(posi(addr)); + else + bustdc_tx.data(6 downto 0) <= std_logic_vector(first_good(addr)); + bustdc_tx.data(14 downto 8) <= std_logic_vector(last_good(addr)); + bustdc_tx.data(22 downto 16) <= std_logic_vector(first_bad(addr)); + bustdc_tx.data(30 downto 24) <= std_logic_vector(last_bad(addr)); + end if; + else + bustdc_tx.ack <= '0'; + bustdc_tx.unknown <= '1'; + + end if; + end if; +end process; + +------------------------------------------------------------------------------- +-- No trigger/data endpoint included +------------------------------------------------------------------------------- +readout_tx(0).data_finished <= '1'; +readout_tx(0).data_write <= '0'; +readout_tx(0).busy_release <= '1'; + + +end architecture; + + + -- 2.43.0