From be9459b18beed83cf15ae9ef49cc9d6a1d60362b Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Wed, 2 Jul 2014 18:58:37 +0200 Subject: [PATCH] added UART to trb3_gbe design --- base/trb3_central.lpf | 22 +++++++++++----- trb3_gbe/config_default.vhd | 3 +++ trb3_gbe/trb3_central.p2t | 2 +- trb3_gbe/trb3_central.prj | 4 +++ trb3_gbe/trb3_central.vhd | 52 ++++++++++++++++++++++++++++++++----- 5 files changed, 69 insertions(+), 14 deletions(-) diff --git a/base/trb3_central.lpf b/base/trb3_central.lpf index ec8db6c..e05fd0a 100644 --- a/base/trb3_central.lpf +++ b/base/trb3_central.lpf @@ -30,12 +30,20 @@ LOCATE COMP "CLK_GPLL_LEFT" SITE "Y9"; LOCATE COMP "CLK_PCLK_LEFT" SITE "V9"; LOCATE COMP "CLK_PCLK_RIGHT" SITE "U28"; -DEFINE PORT GROUP "CLK_group" "CLK*" ; +DEFINE PORT GROUP "CLK_group" "CLK_*" ; IOBUF GROUP "CLK_group" IO_TYPE=LVDS25; LOCATE COMP "ENPIRION_CLOCK" SITE "G18"; IOBUF PORT "ENPIRION_CLOCK" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=4; +LOCATE COMP "CLKRJ_0" SITE "U9"; +LOCATE COMP "CLKRJ_1" SITE "U8"; +LOCATE COMP "CLKRJ_2" SITE "Y34"; +LOCATE COMP "CLKRJ_3" SITE "Y33"; +DEFINE PORT GROUP "CLKRJ_group" "CLKRJ*" ; +IOBUF GROUP "CLKRJ_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=4; + + ################################################################# # Trigger I/O ################################################################# @@ -61,12 +69,12 @@ LOCATE COMP "TRIGGER_EXT_3" SITE "W4"; #was EXT_TRIG_2 DEFINE PORT GROUP "TRIGGER_EXT_group" "TRIGGER_EXT*" ; IOBUF GROUP "TRIGGER_EXT_group" IO_TYPE=LVDS25; -LOCATE COMP "CLK_TEST_OUT_2" SITE "Y34"; -IOBUF PORT "CLK_TEST_OUT_2" IO_TYPE=LVDS25 ; -LOCATE COMP "CLK_TEST_OUT_1" SITE "W4"; -IOBUF PORT "CLK_TEST_OUT_1" IO_TYPE=LVDS25 ; -LOCATE COMP "CLK_TEST_OUT_0" SITE "U9"; -IOBUF PORT "CLK_TEST_OUT_0" IO_TYPE=LVDS25 ; +#LOCATE COMP "CLK_TEST_OUT_2" SITE "Y34"; +#IOBUF PORT "CLK_TEST_OUT_2" IO_TYPE=LVDS25 ; +#LOCATE COMP "CLK_TEST_OUT_1" SITE "W4"; +#IOBUF PORT "CLK_TEST_OUT_1" IO_TYPE=LVDS25 ; +#LOCATE COMP "CLK_TEST_OUT_0" SITE "U9"; +#IOBUF PORT "CLK_TEST_OUT_0" IO_TYPE=LVDS25 ; ################################################################# diff --git a/trb3_gbe/config_default.vhd b/trb3_gbe/config_default.vhd index 266f505..c9a9ebe 100644 --- a/trb3_gbe/config_default.vhd +++ b/trb3_gbe/config_default.vhd @@ -42,6 +42,8 @@ package config is constant INCLUDE_TRIGGER_LOGIC : integer := c_YES; constant PHYSICAL_INPUTS : integer := 16; +--Include generic UART on clock RJ-45? + constant INCLUDE_UART : integer := c_YES; ------------------------------------------------------------------------------ --End of design configuration ------------------------------------------------------------------------------ @@ -124,6 +126,7 @@ package body config is t(16 downto 16) := std_logic_vector(to_unsigned(USE_ETHERNET,1)); t(17 downto 17) := std_logic_vector(to_unsigned(1,1)); --sctrl via GbE t(26 downto 24) := std_logic_vector(to_unsigned(1,3)); --num SFPs with TrbNet + t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1)); t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1)); t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4)); t(52 downto 52) := std_logic_vector(to_unsigned(USE_125_MHZ,1)); diff --git a/trb3_gbe/trb3_central.p2t b/trb3_gbe/trb3_central.p2t index 58b56ca..53dc97b 100644 --- a/trb3_gbe/trb3_central.p2t +++ b/trb3_gbe/trb3_central.p2t @@ -4,7 +4,7 @@ -n 1 -y -s 12 --t 16 +-t 1 -c 1 -e 2 #-g guidefile.ncd diff --git a/trb3_gbe/trb3_central.prj b/trb3_gbe/trb3_central.prj index 59da346..f804983 100644 --- a/trb3_gbe/trb3_central.prj +++ b/trb3_gbe/trb3_central.prj @@ -73,6 +73,10 @@ add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net_gbe_components.vhd" add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/serdes_ch4.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_9x2k_oreg.vhd" add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_frame_receiver.vhd" add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_receive_control.vhd" diff --git a/trb3_gbe/trb3_central.vhd b/trb3_gbe/trb3_central.vhd index ab55f2e..7d14fbb 100644 --- a/trb3_gbe/trb3_central.vhd +++ b/trb3_gbe/trb3_central.vhd @@ -22,7 +22,7 @@ entity trb3_central is CLK_GPLL_RIGHT : in std_logic; --Clock Manager 1/9, 125 MHz <-- for GbE CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz - CLK_TEST_OUT : out std_logic_vector(2 downto 0); + CLKRJ : inout std_logic_vector(3 downto 0); --single-ended on clock rj45 --Trigger TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out @@ -279,6 +279,15 @@ signal stat_ack : std_logic := '0'; signal stat_nack : std_logic := '0'; signal stat_addr : std_logic_vector(15 downto 0) := (others => '0'); +signal uart_din : std_logic_vector(31 downto 0); +signal uart_dout : std_logic_vector(31 downto 0); +signal uart_write : std_logic := '0'; +signal uart_read : std_logic := '0'; +signal uart_ack : std_logic := '0'; +signal uart_nack : std_logic := '0'; +signal uart_empty : std_logic := '0'; +signal uart_addr : std_logic_vector(15 downto 0) := (others => '0'); + signal debug : std_logic_vector(63 downto 0); signal next_reset, make_reset_via_network_q : std_logic; @@ -764,9 +773,9 @@ end generate; --------------------------------------------------------------------------- THE_BUS_HANDLER : trb_net16_regio_bus_handler generic map( - PORT_NUMBER => 8, - PORT_ADDRESSES => (0 => x"d000", 1 => x"8100", 2 => x"8300", 3 => x"b000", 4 => x"b200", 5 => x"d300", 6 => x"cf00", 7 => x"cf80", others => x"0000"), - PORT_ADDR_MASK => (0 => 9, 1 => 8, 2 => 8, 3 => 9, 4 => 9, 5 => 0, 6 => 7, 7 => 7, others => 0) + PORT_NUMBER => 9, + PORT_ADDRESSES => (0 => x"d000", 1 => x"8100", 2 => x"8300", 3 => x"b000", 4 => x"b200", 5 => x"d300", 6 => x"cf00", 7 => x"cf80", 8 => x"d600", others => x"0000"), + PORT_ADDR_MASK => (0 => 9, 1 => 8, 2 => 8, 3 => 9, 4 => 9, 5 => 0, 6 => 7, 7 => 7, 8 => 1, others => 0) ) port map( CLK => clk_sys_i, @@ -883,6 +892,17 @@ THE_BUS_HANDLER : trb_net16_regio_bus_handler BUS_NO_MORE_DATA_IN(7) => '0', BUS_UNKNOWN_ADDR_IN(7) => stat_nack, + --Uart + BUS_READ_ENABLE_OUT(8) => uart_read, + BUS_WRITE_ENABLE_OUT(8) => uart_write, + BUS_DATA_OUT(8*32+31 downto 8*32) => uart_din, + BUS_ADDR_OUT(8*16+15 downto 8*16) => uart_addr, + BUS_TIMEOUT_OUT(8) => open, + BUS_DATA_IN(8*32+31 downto 8*32) => uart_dout, + BUS_DATAREADY_IN(8) => uart_ack, + BUS_WRITE_ACK_IN(8) => uart_ack, + BUS_NO_MORE_DATA_IN(8) => uart_empty, + BUS_UNKNOWN_ADDR_IN(8) => uart_nack, STAT_DEBUG => open ); @@ -971,6 +991,25 @@ end generate; monitor_inputs_i(15 downto 0) <= trig_inputs; monitor_inputs_i(19 downto 16) <= trig_outputs(3 downto 0); +gen_uart : if INCLUDE_UART = 1 generate + THE_UART : entity work.uart + port map( + CLK => clk_sys_i, + RESET => reset_i, + UART_RX => CLKRJ(0), + UART_TX => CLKRJ(2), + DATA_OUT => uart_dout, + DATA_IN => uart_din, + ADDR_IN => uart_addr, + WRITE_IN => uart_write, + READ_IN => uart_read, + ACK_OUT => uart_ack, + EMPTY_OUT => uart_empty, + UNKWN_OUT => uart_nack + ); +end generate; + + --------------------------------------------------------------------------- -- Clock and Trigger Configuration --------------------------------------------------------------------------- @@ -1047,9 +1086,10 @@ end process; TEST_LINE(31 downto 10) <= (others => '0'); - CLK_TEST_OUT <= clk_med_i & '0' & clk_sys_i; - +-- CLK_TEST_OUT <= clk_med_i & '0' & clk_sys_i; + CLKRJ(1) <= 'Z'; + CLKRJ(3) <= 'Z'; -- 2.43.0