From bf35a07d557d3d9b517d20de253bc8fd4f601aac Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Mon, 12 May 2014 11:31:38 +0200 Subject: [PATCH] changed generic COMPILE_VERSION from 16 to 64 bit --- trb_net16_endpoint_hades_full.vhd | 2 +- trb_net16_endpoint_hades_full_handler.vhd | 2 +- trb_net16_endpoint_sctrl.vhd | 2 +- trb_net16_hub_base.vhd | 2 +- trb_net16_hub_func.vhd | 8 ++++---- trb_net16_hub_streaming_port.vhd | 2 +- trb_net16_hub_streaming_port_sctrl.vhd | 2 +- trb_net16_hub_streaming_port_sctrl_cts.vhd | 2 +- trb_net16_regIO.vhd | 10 +++++----- trb_net_components.vhd | 8 ++++---- 10 files changed, 20 insertions(+), 20 deletions(-) diff --git a/trb_net16_endpoint_hades_full.vhd b/trb_net16_endpoint_hades_full.vhd index 6ff5e2a..ba5d9c0 100644 --- a/trb_net16_endpoint_hades_full.vhd +++ b/trb_net16_endpoint_hades_full.vhd @@ -43,7 +43,7 @@ entity trb_net16_endpoint_hades_full is REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222"; REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; - REGIO_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; + REGIO_COMPILE_VERSION : std_logic_vector(63 downto 0) := (others => '0'); REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; REGIO_USE_1WIRE_INTERFACE : integer := c_YES; --c_YES,c_NO,c_MONITOR REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO; diff --git a/trb_net16_endpoint_hades_full_handler.vhd b/trb_net16_endpoint_hades_full_handler.vhd index 894e0cd..a1e4fd4 100644 --- a/trb_net16_endpoint_hades_full_handler.vhd +++ b/trb_net16_endpoint_hades_full_handler.vhd @@ -25,7 +25,7 @@ entity trb_net16_endpoint_hades_full_handler is REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222"; REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; - REGIO_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; + REGIO_COMPILE_VERSION : std_logic_vector(63 downto 0) := (others => '0'); REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; REGIO_USE_1WIRE_INTERFACE : integer := c_YES; --c_YES,c_NO,c_MONITOR REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO; diff --git a/trb_net16_endpoint_sctrl.vhd b/trb_net16_endpoint_sctrl.vhd index d1ffe61..cf987c5 100644 --- a/trb_net16_endpoint_sctrl.vhd +++ b/trb_net16_endpoint_sctrl.vhd @@ -34,7 +34,7 @@ entity trb_net16_endpoint_sctrl is REGIO_INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876"; REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222"; REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; - REGIO_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; + REGIO_COMPILE_VERSION : std_logic_vector(63 downto 0) := (others => '0'); REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; REGIO_USE_1WIRE_INTERFACE : integer := c_YES; --c_YES,c_NO,c_MONITOR REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO; diff --git a/trb_net16_hub_base.vhd b/trb_net16_hub_base.vhd index 57f2990..df6aa64 100644 --- a/trb_net16_hub_base.vhd +++ b/trb_net16_hub_base.vhd @@ -28,7 +28,7 @@ entity trb_net16_hub_base is x"00000000_00000000_00007077_00000000" & x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF"; COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; - COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; + COMPILE_VERSION : std_logic_vector(63 downto 0) := (others => '0'); INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO; HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; diff --git a/trb_net16_hub_func.vhd b/trb_net16_hub_func.vhd index 44ea559..37cf57b 100644 --- a/trb_net16_hub_func.vhd +++ b/trb_net16_hub_func.vhd @@ -101,7 +101,7 @@ package trb_net16_hub_func is x"00000000_00000000_000050FF_00000000" & x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF"; COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; - COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; + COMPILE_VERSION : std_logic_vector(63 downto 0) := (others => '0'); INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO; HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; @@ -206,7 +206,7 @@ component trb_net16_hub_streaming_port is INIT_ADDRESS : std_logic_vector(15 downto 0) := x"F004"; INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := (others => '0'); COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; - COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; + COMPILE_VERSION : std_logic_vector(63 downto 0) := (others => '0'); HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"7E"; @@ -602,7 +602,7 @@ component trb_net16_hub_streaming_port_sctrl is INIT_ADDRESS : std_logic_vector(15 downto 0) := x"F004"; INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := (others => '0'); COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; - COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; + COMPILE_VERSION : std_logic_vector(63 downto 0) := (others => '0'); HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"7E"; @@ -712,7 +712,7 @@ component trb_net16_hub_streaming_port_sctrl_cts is INIT_ADDRESS : std_logic_vector(15 downto 0) := x"F3C0"; INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := (others => '0'); COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; - COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; + COMPILE_VERSION : std_logic_vector(63 downto 0) := (others => '0'); HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"9000CE00"; INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0005"; BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"7E"; diff --git a/trb_net16_hub_streaming_port.vhd b/trb_net16_hub_streaming_port.vhd index e8c8a8f..073aab0 100644 --- a/trb_net16_hub_streaming_port.vhd +++ b/trb_net16_hub_streaming_port.vhd @@ -22,7 +22,7 @@ entity trb_net16_hub_streaming_port is INIT_ADDRESS : std_logic_vector(15 downto 0) := x"F004"; INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := (others => '0'); COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; - COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; + COMPILE_VERSION : std_logic_vector(63 downto 0) := (others => '0'); HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"7E"; diff --git a/trb_net16_hub_streaming_port_sctrl.vhd b/trb_net16_hub_streaming_port_sctrl.vhd index 6438936..2b27288 100644 --- a/trb_net16_hub_streaming_port_sctrl.vhd +++ b/trb_net16_hub_streaming_port_sctrl.vhd @@ -35,7 +35,7 @@ entity trb_net16_hub_streaming_port_sctrl is INIT_ADDRESS : std_logic_vector(15 downto 0) := x"F004"; INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := (others => '0'); COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; - COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; + COMPILE_VERSION : std_logic_vector(63 downto 0) := (others => '0'); HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"7E"; diff --git a/trb_net16_hub_streaming_port_sctrl_cts.vhd b/trb_net16_hub_streaming_port_sctrl_cts.vhd index f21ace2..3620663 100644 --- a/trb_net16_hub_streaming_port_sctrl_cts.vhd +++ b/trb_net16_hub_streaming_port_sctrl_cts.vhd @@ -51,7 +51,7 @@ entity trb_net16_hub_streaming_port_sctrl_cts is INIT_ADDRESS : std_logic_vector(15 downto 0) := x"F3C0"; INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := (others => '0'); COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; - COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; + COMPILE_VERSION : std_logic_vector(63 downto 0) := (others => '0'); HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"9000CE00"; INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0005"; BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"7E"; diff --git a/trb_net16_regIO.vhd b/trb_net16_regIO.vhd index 81837df..779375b 100644 --- a/trb_net16_regIO.vhd +++ b/trb_net16_regIO.vhd @@ -26,7 +26,7 @@ entity trb_net16_regIO is INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222"; INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; --not used any more! - COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; + COMPILE_VERSION : std_logic_vector(63 downto 0) := (others => '0'); HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; CLOCK_FREQ : integer range 1 to 200 := 100 --MHz ); @@ -931,12 +931,12 @@ begin generic map( INIT0 => COMPILE_TIME_LIB(15 downto 0), INIT1 => COMPILE_TIME_LIB(31 downto 16), - INIT2 => COMPILE_VERSION, - INIT3 => (others => '0'), + INIT2 => COMPILE_VERSION(15 downto 0), + INIT3 => COMPILE_VERSION(31 downto 16), INIT4 => HARDWARE_VERSION(15 downto 0), INIT5 => HARDWARE_VERSION(31 downto 16), - INIT6 => (others => '0'), - INIT7 => (others => '0') + INIT6 => COMPILE_VERSION(47 downto 32), + INIT7 => COMPILE_VERSION(63 downto 48) ) port map( CLK => CLK, diff --git a/trb_net_components.vhd b/trb_net_components.vhd index 8e5d6c5..60d623a 100644 --- a/trb_net_components.vhd +++ b/trb_net_components.vhd @@ -615,7 +615,7 @@ package trb_net_components is REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222"; REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; - REGIO_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; + REGIO_COMPILE_VERSION : std_logic_vector(63 downto 0) := (others => '0'); REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; REGIO_USE_1WIRE_INTERFACE : integer := c_YES; --c_YES,c_NO,c_MONITOR REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO; @@ -746,7 +746,7 @@ package trb_net_components is REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222"; REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; - REGIO_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; + REGIO_COMPILE_VERSION : std_logic_vector(63 downto 0) := (others => '0'); REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; REGIO_USE_1WIRE_INTERFACE : integer := c_YES; --c_YES,c_NO,c_MONITOR REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO; @@ -886,7 +886,7 @@ package trb_net_components is REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"0000_0000"; REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; - REGIO_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; + REGIO_COMPILE_VERSION : std_logic_vector(63 downto 0) := (others => '0'); REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"50000000"; REGIO_USE_1WIRE_INTERFACE : integer := c_YES; --c_YES,c_NO,c_MONITOR REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO; @@ -2554,7 +2554,7 @@ package trb_net_components is INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222"; INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; - COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; + COMPILE_VERSION : std_logic_vector(63 downto 0) := (others => '0'); HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; CLOCK_FREQ : integer range 1 to 200 := 100 --MHz ); -- 2.43.0