From bf59a285f8305cc8797d8375eebb2fb6bc5e1a49 Mon Sep 17 00:00:00 2001
From: hadeshyp <hadeshyp>
Date: Thu, 14 Jun 2012 12:55:52 +0000
Subject: [PATCH] *** empty log message ***

---
 trb3/DacProgramming.tex | 28 ++++++++++++++++++----------
 trb3/MultiTestAddOn.tex |  2 +-
 2 files changed, 19 insertions(+), 11 deletions(-)

diff --git a/trb3/DacProgramming.tex b/trb3/DacProgramming.tex
index 69ed6c6..d8142d2 100644
--- a/trb3/DacProgramming.tex
+++ b/trb3/DacProgramming.tex
@@ -2,26 +2,34 @@
 Programming the DAC for threshold generation is simple: A standard SPI interface takes 32 Bit of data, the device is chainable. A Perl software module cares about the data content, a simple VHDL core outputs the data and controls the CS signal.
 
 The slow-control interface:
-\begin{itemize}
- \item 32 Bit Data Memory: 0xd400 - 0xd40f, Length register 0xd410 
+\begin{itemize*}
+ \item 32 Bit Data Memory: 0xd400 - 0xd40f, Chain select mask 0xd410, Length register 0xd411 
  \item Transfer is started when the length register (counting 32 Bit words) is written. 
  \item While busy, the writing to the length register will be ignored and gives back a no-more-data flag.
- \item Doing a memory write with 17 words will do the job, should be faster than two individual accesses for data and length.
+ \item Doing a memory write with 18 words will do the job, should be faster than two individual accesses for data and length.
  \item All data is sent MSB first (Bit 31), Bits 31-24 are the don't-care-Bits of the DAC. 
  \item Interface speed: e.g. 6.25 MHz -> max. 80us for 16 chips
-\end{itemize}
+\end{itemize*}
 
 The software takes a text file as input and generates the correct SPI sequence to load and activate the DAC.
 The ASCII format is shown below, the commands can be found in table~\ref{ltc2600cmd}.
 \begin{verbatim}
-# DAC     Channel       Command       Value
-  0       0             3             0x3450
-  0       1             3             0x1230
-  1       0             3             0x6780
-  2       0             F             0
-
+# Board   Chain     ChainLen   DAC     Channel       Command       Value
+  f333    1         4          0       0             3             0x3450
+  f333    1         4          0       1             3             0x1230
+  f333    1         4          1       0             3             0x6780
+  f333    1         4          2       0             3             0x3450
 \end{verbatim}
 
+\begin{itemize*}
+ \item Board: The TrbNet address of the board. Can be a broadcast address
+ \item Chain: A bitmask to select one or more individual SPI chains out of 16 possible ones
+ \item ChainLen: The length of the selected chain, possible are 1 - 16 DACs in one chain. Valid values are 0x0001 to 0xffff
+ \item DAC: The DAC number in the chain, counting from 0 to 15
+ \item Channel: The Channel of the DAC (0..7)
+ \item Value: The value to load. 16 Bit value. Note that we are using LTC2620 which are 12 Bit only, the lower 4 Bit are "don't care" in this case and should be 0
+\end{itemize*}
+
 \begin{table}
 \centering
 \begin{tabular}{c|l}
diff --git a/trb3/MultiTestAddOn.tex b/trb3/MultiTestAddOn.tex
index f8abbbb..7a2a9f1 100644
--- a/trb3/MultiTestAddOn.tex
+++ b/trb3/MultiTestAddOn.tex
@@ -8,5 +8,5 @@
 \subsubsection{Known bugs}
 \begin{itemize*}
  \item The serial interface to ADC 1 is not usable - CSB and PDWN are input-only on the FPGA
- \item LVDS_INP_2 is the only LVDS port that is terminated by an external resistor. Do not switch on corresponding LVDS termiantion in FPGA
+ \item LVDS\_INP\_2 is the only LVDS port that is terminated by an external resistor. Do not switch on corresponding LVDS termiantion in FPGA
 \end{itemize*}
\ No newline at end of file
-- 
2.43.0