From bf6a00406659273b71b6cd64136a46b904b849a7 Mon Sep 17 00:00:00 2001 From: Adrian Weber Date: Mon, 13 Sep 2021 12:32:47 +0200 Subject: [PATCH] add new board DiRICH5s with some debug settings --- dirich5s/compile.pl | 1 + dirich5s/config.vhd | 141 ++++++++ dirich5s/config_compile_frankfurt.pl | 26 ++ dirich5s/config_compile_giessen.pl | 28 ++ dirich5s/config_compile_gsi.pl | 24 ++ dirich5s/dirich.lpf | 82 +++++ dirich5s/dirich.prj | 224 +++++++++++++ dirich5s/dirich.vhd | 470 +++++++++++++++++++++++++++ dirich5s/nodelist_frankfurt.txt | 21 ++ dirich5s/par.p2t | 70 ++++ dirich5s/tdc_release | 1 + pinout/dirich5s.lpf | 145 +++++++++ 12 files changed, 1233 insertions(+) create mode 120000 dirich5s/compile.pl create mode 100644 dirich5s/config.vhd create mode 100644 dirich5s/config_compile_frankfurt.pl create mode 100644 dirich5s/config_compile_giessen.pl create mode 100644 dirich5s/config_compile_gsi.pl create mode 100644 dirich5s/dirich.lpf create mode 100644 dirich5s/dirich.prj create mode 100644 dirich5s/dirich.vhd create mode 100644 dirich5s/nodelist_frankfurt.txt create mode 100644 dirich5s/par.p2t create mode 120000 dirich5s/tdc_release create mode 100644 pinout/dirich5s.lpf diff --git a/dirich5s/compile.pl b/dirich5s/compile.pl new file mode 120000 index 0000000..933ff60 --- /dev/null +++ b/dirich5s/compile.pl @@ -0,0 +1 @@ +../../trb3/scripts/compile.pl \ No newline at end of file diff --git a/dirich5s/config.vhd b/dirich5s/config.vhd new file mode 100644 index 0000000..5daa38e --- /dev/null +++ b/dirich5s/config.vhd @@ -0,0 +1,141 @@ +library ieee; +USE IEEE.std_logic_1164.ALL; +use ieee.numeric_std.all; +use work.trb_net_std.all; + +package config is + + +------------------------------------------------------------------------------ +--Begin of design configuration +------------------------------------------------------------------------------ + + constant DIRICH_VERSION : integer := 2; --1 or 2. + +--TDC settings + constant BOARD : string := "dirich"; -- Options: dirich, trb3 + constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement + constant NUM_TDC_CHANNELS : integer range 1 to 65 := 33; -- number of tdc channels per module + constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons + constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3 + -- 0: single edge only, + -- 1: same channel, + -- 2: alternating channels, + -- 3: same channel with stretcher + constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size + -- mode: 0, 1, 2, 3, 7 + -- size: 32, 64, 96, 128, dyn + constant TDC_DATA_FORMAT : integer range 0 to 3 := 0; --type of data format for the TDC + -- 0: Single fine time as the sum of the two transitions + -- 1: Double fine time, individual transitions + -- 13: Debug - fine time + (if 0x3ff full chain) + -- 14: Debug - single fine time and the ROM addresses for the two transitions + -- 15: Debug - complete carry chain dump + + constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 13; -- size of the event buffer, 2**N + constant EVENT_MAX_SIZE : integer := 500; --maximum event size. Must not exceed EVENT_BUFFER_SIZE/2 + +--Runs with 120 MHz instead of 100 MHz + constant USE_120_MHZ : integer := c_NO; + +--Use sync mode, RX clock for all parts of the FPGA + constant USE_RXCLOCK : integer := c_NO; + +--Address settings + constant INIT_ADDRESS : std_logic_vector := x"F3D7"; + constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"57"; + + constant INCLUDE_UART : integer := c_NO; --300 slices + constant INCLUDE_SPI : integer := c_YES; --300 slices --needed for Dirich2 + constant INCLUDE_LCD : integer := c_NO; --800 slices + constant INCLUDE_DEBUG_INTERFACE: integer := c_NO; --300 slices + +--input monitor and trigger generation logic + constant INCLUDE_TRIGGER_LOGIC : integer := c_NO; --400 slices @32->2 + constant INCLUDE_STATISTICS : integer := c_NO; --1300 slices, 1 RAM @32 + constant TRIG_GEN_INPUT_NUM : integer := 32; + constant TRIG_GEN_OUTPUT_NUM : integer := 2; + constant MONITOR_INPUT_NUM : integer := 32; + +--Retransmission + constant USE_RETRANSMISSION : integer := c_NO;--c_YES; + +--Misc + constant FPGA_SIZE : string := "85KUM"; + constant FPGA_TYPE : integer := 5; --3: ECP3, 5: ECP5 + +------------------------------------------------------------------------------ +--End of design configuration +------------------------------------------------------------------------------ + + + type data_t is array (0 to 1023) of std_logic_vector(7 downto 0); + constant LCD_DATA : data_t := ( + x"36",x"48",x"3A",x"55",x"29",x"2A",x"00",x"00", --config don't touch + x"00",x"EF",x"2B",x"00",x"00",x"01",x"3F",x"2C", --config don't touch + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", --config don't touch + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", --config don't touch + + x"44", x"69", x"52", x"69", x"63", x"68", x"0a", + x"0a", + x"41", x"64", x"64", x"72", x"65", x"73", x"73", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"80", x"0a", + x"55", x"49", x"44", x"20", x"20", x"89", x"88", x"87", x"86", x"0a", + x"43", x"6f", x"6d", x"70", x"69", x"6c", x"65", x"54", x"69", x"6d", x"65", x"20", x"20", x"84", x"83", x"0a", + x"54", x"69", x"6d", x"65", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"82", x"81", x"0a", + x"54", x"65", x"6d", x"70", x"65", x"72", x"61", x"74", x"75", x"72", x"65", x"20", x"20", x"20", x"20", x"20", x"20", x"85", x"0a", + x"8a", x"0a", + x"8b", x"0a", + others => x"00"); + +------------------------------------------------------------------------------ +--Select settings by configuration +------------------------------------------------------------------------------ + type intlist_t is array(0 to 7) of integer; + type hw_info_t is array(0 to 7) of unsigned(31 downto 0); + constant HW_INFO_BASE : unsigned(31 downto 0) := x"9A000000"; + + constant CLOCK_FREQUENCY_ARR : intlist_t := (100,120, others => 0); + constant MEDIA_FREQUENCY_ARR : intlist_t := (200,240, others => 0); + + --declare constants, filled in body + constant HARDWARE_INFO : std_logic_vector(31 downto 0); + constant CLOCK_FREQUENCY : integer; + constant MEDIA_FREQUENCY : integer; + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0); + + +end; + +package body config is +--compute correct configuration mode + + constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector( HW_INFO_BASE ); + constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_120_MHZ); + constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_120_MHZ); + +function generateIncludedFeatures return std_logic_vector is + variable t : std_logic_vector(63 downto 0); + begin + t := (others => '0'); + t(63 downto 56) := std_logic_vector(to_unsigned(2,8)); --table version 1 + + t(7 downto 0) := std_logic_vector(to_unsigned(1,8)); + t(11 downto 8) := std_logic_vector(to_unsigned(DOUBLE_EDGE_TYPE,4)); + t(14 downto 12) := std_logic_vector(to_unsigned(RING_BUFFER_SIZE,3)); + t(15) := '1'; --TDC + t(17 downto 16) := std_logic_vector(to_unsigned(NUM_TDC_MODULES-1,2)); + + t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1)); + t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1)); + t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1)); + t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1)); + t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4)); + t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1)); + t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1)); + t(54 downto 54) := "0";--std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1)); + return t; + end function; + + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures; + +end package body; diff --git a/dirich5s/config_compile_frankfurt.pl b/dirich5s/config_compile_frankfurt.pl new file mode 100644 index 0000000..2dd81ea --- /dev/null +++ b/dirich5s/config_compile_frankfurt.pl @@ -0,0 +1,26 @@ +Familyname => 'ECP5UM', +Devicename => 'LFE5UM-85F', +Package => 'CABGA381', +Speedgrade => '8', + + +TOPNAME => "dirich", +lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; +lm_license_file_for_par => "1702\@jspc29", +lattice_path => '/d/jspc29/lattice/diamond/3.10_x64', +synplify_path => '/d/jspc29/lattice/synplify/O-2018.09-SP1', + +nodelist_file => '../nodelist_frankfurt.txt', +pinout_file => 'dirich5s', +par_options => '../par.p2t', + + +#Include only necessary lpf files +#pinout_file => '', #name of pin-out file, if not equal TOPNAME +include_TDC => 1, +include_GBE => 0, + +#Report settings +firefox_open => 0, +twr_number_of_errors => 20, +no_ltxt2ptxt => 1, #if there is no serdes being used diff --git a/dirich5s/config_compile_giessen.pl b/dirich5s/config_compile_giessen.pl new file mode 100644 index 0000000..f4f9196 --- /dev/null +++ b/dirich5s/config_compile_giessen.pl @@ -0,0 +1,28 @@ +Familyname => 'ECP5UM', +Devicename => 'LFE5UM-85F', +Package => 'CABGA381', +Speedgrade => '8', + + +TOPNAME => "dirich", +lm_license_file_for_synplify => "7788\@fb07pc-u102325", +lm_license_file_for_par => "7788\@fb07pc-u102325", +lattice_path => '/usr/local/diamond/3.11_x64/', +synplify_path => '/usr/local/diamond/3.11_x64/synpbase', +synplify_command => "synpwrap -fg -options", + +nodelist_file => '../nodelist_frankfurt.txt', +pinout_file => 'dirich5s', +par_options => '../par.p2t', + + +#Include only necessary lpf files +include_TDC => 1, +include_GBE => 0, + +#Report settings +firefox_open => 0, +twr_number_of_errors => 20, +no_ltxt2ptxt => 1, #if there is no serdes being used +#make_jed => 1, + diff --git a/dirich5s/config_compile_gsi.pl b/dirich5s/config_compile_gsi.pl new file mode 100644 index 0000000..c5679b3 --- /dev/null +++ b/dirich5s/config_compile_gsi.pl @@ -0,0 +1,24 @@ +Familyname => 'ECP5UM', +Devicename => 'LFE5UM-85F', +Package => 'CABGA381', +Speedgrade => '8', + +TOPNAME => "dirich", +lm_license_file_for_synplify => "27000\@lxcad01.gsi.de", +lm_license_file_for_par => "1702\@hadeb05.gsi.de", +lattice_path => '/opt/lattice/diamond/3.8_x64', +synplify_path => '/opt/synplicity/K-2015.09', +#synplify_command => "/opt/lattice/diamond/3.5_x64/bin/lin64/synpwrap -fg -options", +synplify_command => "/opt/synplicity/K-2015.09/bin/synplify_premier_dp", + +nodelist_file => '../nodes_lxhadeb07.txt', +pinout_file => 'dirich5s', +par_options => '../par.p2t', + + +include_TDC => 1, +include_GBE => 0, + +firefox_open => 0, +twr_number_of_errors => 20, +no_ltxt2ptxt => 1, #if there is no serdes being used diff --git a/dirich5s/dirich.lpf b/dirich5s/dirich.lpf new file mode 100644 index 0000000..0d6d626 --- /dev/null +++ b/dirich5s/dirich.lpf @@ -0,0 +1,82 @@ +COMMERCIAL ; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +BLOCK RD_DURING_WR_PATHS ; + +################################################################# +# Basic Settings +################################################################# + +FREQUENCY PORT CLOCK_CORE 200 MHz; +FREQUENCY PORT CLOCK_IN 200 MHz; +FREQUENCY PORT CLOCK_CAL 200 MHz; + +FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz; +FREQUENCY NET "med_stat_debug[11]" 200 MHz; + +FREQUENCY NET "med2int_0.clk_full" 200 MHz; +FREQUENCY NET THE_MEDIA_INTERFACE/clk_rx_full 200 MHz; + + +BLOCK PATH TO PORT "LED*"; +BLOCK PATH TO PORT "PROGRAMN"; +BLOCK PATH TO PORT "TEMP_LINE"; +BLOCK PATH FROM PORT "TEMP_LINE"; +BLOCK PATH TO PORT "TEST_LINE*"; + +#MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/trb_reset_pulse*" 20 ns; +#MULTICYCLE FROM CELL "THE_CLOCK_RESET/clear_n_i" 20 ns; +#MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns; +#MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns; + +MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_SCI_READER/PROC_SCI_CTRL.BUS_TX*" 10 ns; +MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT*" 10 ns; + +GSR_NET NET "clear_i"; + +# LOCATE COMP "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/DCU0_inst" SITE "DCU0" ; + + +REGION "MEDIA" "R81C44D" 13 30; +LOCATE UGROUP "THE_MEDIA_INTERFACE/media_interface_group" REGION "MEDIA" ; + + +UGROUP "INPGATE_LEFT" BBOX 35 2 + BLKNAME THE_TDC/GEN_HitSelect.1.Double.HitSelect.hit_in_s_12_u[1] + BLKNAME THE_TDC/GEN_HitSelect.2.Double.HitSelect.hit_in_s_20_u[2] + BLKNAME THE_TDC/GEN_HitSelect.3.Double.HitSelect.hit_in_s_28_u[3] + BLKNAME THE_TDC/GEN_HitSelect.4.Double.HitSelect.hit_in_s_36_u[4] + BLKNAME THE_TDC/GEN_HitSelect.5.Double.HitSelect.hit_in_s_44_u[5] + BLKNAME THE_TDC/GEN_HitSelect.6.Double.HitSelect.hit_in_s_52_u[6] + BLKNAME THE_TDC/GEN_HitSelect.7.Double.HitSelect.hit_in_s_60_u[7] + BLKNAME THE_TDC/GEN_HitSelect.8.Double.HitSelect.hit_in_s_68_u[8] + BLKNAME THE_TDC/GEN_HitSelect.9.Double.HitSelect.hit_in_s_76_u[9] + BLKNAME THE_TDC/GEN_HitSelect.10.Double.HitSelect.hit_in_s_84_u[10] + BLKNAME THE_TDC/GEN_HitSelect.11.Double.HitSelect.hit_in_s_92_u[11] + BLKNAME THE_TDC/GEN_HitSelect.12.Double.HitSelect.hit_in_s_100_u[12] + BLKNAME THE_TDC/GEN_HitSelect.13.Double.HitSelect.hit_in_s_108_u[13] + BLKNAME THE_TDC/GEN_HitSelect.14.Double.HitSelect.hit_in_s_116_u[14] + BLKNAME THE_TDC/GEN_HitSelect.15.Double.HitSelect.hit_in_s_124_u[15] + BLKNAME THE_TDC/GEN_HitSelect.16.Double.HitSelect.hit_in_s_132_u[16] + ; +LOCATE UGROUP "INPGATE_LEFT" SITE "R9C2D" ; + +UGROUP "INPGATE_RIGHT" BBOX 80 2 + BLKNAME THE_TDC/GEN_HitSelect.17.Double.HitSelect.hit_in_s_140_u[17] + BLKNAME THE_TDC/GEN_HitSelect.18.Double.HitSelect.hit_in_s_148_u[18] + BLKNAME THE_TDC/GEN_HitSelect.19.Double.HitSelect.hit_in_s_156_u[19] + BLKNAME THE_TDC/GEN_HitSelect.20.Double.HitSelect.hit_in_s_164_u[20] + BLKNAME THE_TDC/GEN_HitSelect.21.Double.HitSelect.hit_in_s_172_u[21] + BLKNAME THE_TDC/GEN_HitSelect.22.Double.HitSelect.hit_in_s_180_u[22] + BLKNAME THE_TDC/GEN_HitSelect.23.Double.HitSelect.hit_in_s_188_u[23] + BLKNAME THE_TDC/GEN_HitSelect.24.Double.HitSelect.hit_in_s_196_u[24] + BLKNAME THE_TDC/GEN_HitSelect.25.Double.HitSelect.hit_in_s_204_u[25] + BLKNAME THE_TDC/GEN_HitSelect.26.Double.HitSelect.hit_in_s_212_u[26] + BLKNAME THE_TDC/GEN_HitSelect.27.Double.HitSelect.hit_in_s_220_u[27] + BLKNAME THE_TDC/GEN_HitSelect.28.Double.HitSelect.hit_in_s_228_u[28] + BLKNAME THE_TDC/GEN_HitSelect.29.Double.HitSelect.hit_in_s_236_u[29] + BLKNAME THE_TDC/GEN_HitSelect.30.Double.HitSelect.hit_in_s_244_u[30] + BLKNAME THE_TDC/GEN_HitSelect.31.Double.HitSelect.hit_in_s_252_u[31] + BLKNAME THE_TDC/GEN_HitSelect.32.Double.HitSelect.hit_in_s_260_u[32] + ; +LOCATE UGROUP "INPGATE_RIGHT" SITE "R9C123D" ; diff --git a/dirich5s/dirich.prj b/dirich5s/dirich.prj new file mode 100644 index 0000000..f4f4dfa --- /dev/null +++ b/dirich5s/dirich.prj @@ -0,0 +1,224 @@ + +# implementation: "workdir" +impl -add workdir -type fpga + +# device options +set_option -technology ECP5UM +set_option -part LFE5UM_85F +set_option -package BG381C +set_option -speed_grade -8 +set_option -part_companion "" + +# compilation/mapping options +set_option -default_enum_encoding sequential +set_option -symbolic_fsm_compiler 1 +set_option -top_module "dirich" +set_option -resource_sharing false + +# map options +set_option -frequency 120 +set_option -fanout_limit 100 +set_option -disable_io_insertion 0 +set_option -retiming 1 +set_option -pipe 1 +set_option -forcegsr false +set_option -fixgatedclocks 3 +set_option -fixgeneratedclocks 3 +set_option -compiler_compatible true +set_option -multi_file_compilation_unit 1 + +set_option -max_parallel_jobs 3 +#set_option -automatic_compile_point 1 +#set_option -continue_on_error 1 +set_option -resolve_multiple_driver 1 + +# simulation options +set_option -write_verilog 0 +set_option -write_vhdl 1 + +# automatic place and route (vendor) options +set_option -write_apr_constraint 0 + +# set result format/file last +project -result_format "edif" +project -result_file "workdir/dirich.edf" +set_option log_file "workdir/dirich_project.srf" +#implementation attributes + +set_option -vlog_std v2001 +set_option -project_relative_includes 1 +impl -active "workdir" + +#################### + +add_file -vhdl -lib work "workdir/lattice-diamond/cae_library/synthesis/vhdl/ecp5um.vhd" + +#Packages +add_file -vhdl -lib work "workdir/version.vhd" +add_file -vhdl -lib work "config.vhd" +add_file -vhdl -lib work "../../trb3/base/trb3_components.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" +add_file -vhdl -lib work "tdc_release/tdc_version.vhd" + +#Basic Infrastructure +add_file -vhdl -lib work "../cores/pll_240_100/pll_240_100.vhd" +add_file -vhdl -lib work "../code/clock_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd" +add_file -vhdl -lib work "../../vhdlbasics/ecp5/sedcheck.vhd" +add_file -vhdl -lib work "../code/pwm_generator.vhd" + + +#Fifos +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net16_fifo_arch.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16bit_dualport/lattice_ecp5_fifo_16bit_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net_fifo_16bit_bram_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x256_oreg/fifo_36x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x2k_oreg/fifo_18x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_9x2k_oreg/fifo_9x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16x16_dualport/lattice_ecp5_fifo_16x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport/lattice_ecp5_fifo_18x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" + + +#Flash & Reload, Tools +add_file -vhdl -lib work "../../trbnet/special/slv_register.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" +add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd" +add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd" +add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd" +add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" +add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd" +add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd" +add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd" + +#SlowControl files +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd" + +#Media interface +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync.vhd" + +#add_file -verilog -lib work "diamond/pcs/serdes_sync_0/serdes_sync_0_softlogic.v" +#add_file -vhdl -lib work "diamond/pcs/serdes_sync_0/serdes_sync_0.vhd" +#add_file -vhdl -lib work "diamond/pcs/pcs.vhd" +add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0_softlogic.v" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_0/serdes_sync_0.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs2.vhd" + + +#TrbNet Endpoint +add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_gbe.vhd" +add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd" + +add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd" + +add_file -vhdl -lib work "tdc_release/tdc_components.vhd" +add_file -vhdl -lib work "tdc_release/bit_sync.vhd" +add_file -vhdl -lib work "tdc_release/BusHandler_record.vhd" +add_file -vhdl -lib work "tdc_release/Channel_200.vhd" +add_file -vhdl -lib work "tdc_release/Channel.vhd" +add_file -vhdl -lib work "tdc_release/Encoder_288_Bit.vhd" +add_file -vhdl -lib work "tdc_release/fallingEdgeDetect.vhd" +add_file -vhdl -lib work "tdc_release/hit_mux.vhd" +add_file -vhdl -lib work "tdc_release/LogicAnalyser.vhd" +add_file -vhdl -lib work "tdc_release/Readout_record.vhd" +add_file -vhdl -lib work "tdc_release/risingEdgeDetect.vhd" +add_file -vhdl -lib work "tdc_release/ROM_encoder_ecp5.vhd" +add_file -vhdl -lib work "tdc_release/ShiftRegisterSISO.vhd" +add_file -vhdl -lib work "tdc_release/Stretcher_A.vhd" +add_file -vhdl -lib work "tdc_release/Stretcher_B.vhd" +add_file -vhdl -lib work "tdc_release/Stretcher.vhd" +add_file -vhdl -lib work "tdc_release/TDC_record.vhd" +add_file -vhdl -lib work "tdc_release/TriggerHandler.vhd" +add_file -vhdl -lib work "tdc_release/up_counter.vhd" + +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/TDC/Adder_288/Adder_288.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x128_OutReg/FIFO_DC_36x128_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x64_OutReg/FIFO_DC_36x64_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x32_OutReg/FIFO_DC_36x32_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x128_OutReg/FIFO_36x128_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x64_OutReg/FIFO_36x64_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x32_OutReg/FIFO_36x32_OutReg.vhd" +#add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in125_out33/pll_in125_out33.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in3125_out50/pll_in3125_out50.vhd" + + +add_file -vhdl -lib work "./dirich.vhd" +#add_file -fpga_constraint "./synplify.fdc" + + + diff --git a/dirich5s/dirich.vhd b/dirich5s/dirich.vhd new file mode 100644 index 0000000..f40167d --- /dev/null +++ b/dirich5s/dirich.vhd @@ -0,0 +1,470 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.version.all; +use work.config.all; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.med_sync_define.all; + +entity dirich is + port( + CLOCK_CORE : in std_logic; --Main Oscillator + CLOCK_IN : in std_logic; --external Clock + TRIG_IN : in std_logic; --Reference Time + CLOCK_CAL : in std_logic; --on-board calibration oscillator + + CLOCK_OUT : out std_logic; -- CLK to clock cleaner + CLOCK_CLEAN : in std_logic_vector(1 downto 0); -- CLK from clock cleaner + + INPUT : in std_logic_vector(32 downto 1); +-- PWM : out std_logic_vector(32 downto 1); + + --Additional IO + SIG : inout std_logic_vector(4 downto 1); + --1:master ready, 2: slave ready, 3-4 trigger, 5 reset + --LED + LED_GREEN : out std_logic; + LED_YELLOW : out std_logic; + LED_ORANGE : out std_logic; + LED_RED : out std_logic; + --ADC + ADC_SCLK : out std_logic; + ADC_CS : out std_logic; + ADC_DIN : out std_logic; + ADC_DOUT : in std_logic; + --Flash, 1-wire, Reload + FLASH_CLK : out std_logic; + FLASH_CS : out std_logic; + FLASH_IN : out std_logic; + FLASH_OUT : in std_logic; + FLASH_HOLD : out std_logic; + FLASH_WP : out std_logic; + PROGRAMN : out std_logic; + TEMP_LINE : inout std_logic; + + MISO_IN : in std_logic_vector(1 downto 0); + MOSI_OUT : out std_logic_vector(1 downto 0); + SCLK_OUT : out std_logic_vector(1 downto 0); + CS_OUT : out std_logic_vector(1 downto 0); + + --Test Connectors + TEST_LINE : inout std_logic_vector(14 downto 1) + ); + + + attribute syn_useioff : boolean; +-- attribute syn_useioff of FLASH_CLK : signal is true; + attribute syn_useioff of FLASH_CS : signal is true; + attribute syn_useioff of FLASH_IN : signal is true; + attribute syn_useioff of FLASH_OUT : signal is true; + attribute syn_useioff of INPUT : signal is false; + +end entity; + +architecture dirich_arch of dirich is + attribute syn_keep : boolean; + attribute syn_preserve : boolean; + + signal clk_sys, clk_full, clk_full_osc, clk_cal : std_logic; + signal GSR_N : std_logic; + signal reset_i : std_logic; + signal clear_i : std_logic; + + signal time_counter : unsigned(31 downto 0) := (others => '0'); + signal debug_clock_reset : std_logic_vector(31 downto 0); + signal debug_tools : std_logic_vector(31 downto 0); + + --Media Interface + signal med2int : med2int_array_t(0 to 0); + signal int2med : int2med_array_t(0 to 0); + signal med_stat_debug : std_logic_vector (1*64-1 downto 0); + signal link_stat_in, link_stat_out : std_logic; + --READOUT + signal readout_rx : READOUT_RX; + signal readout_tx : readout_tx_array_t(0 to 0); + + signal ctrlbus_tx, bustdc_tx, bussci_tx, bustools_tx, bustc_tx, busthresh_tx, bus_master_in : CTRLBUS_TX; + signal ctrlbus_rx, bustdc_rx, bussci_rx, bustools_rx, bustc_rx, busthresh_rx, bus_master_out : CTRLBUS_RX; + + signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); + signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); + + signal sed_error_i : std_logic; + signal clock_select : std_logic; + signal bus_master_active : std_logic; + signal flash_clk_i : std_logic; + + signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0); + + signal pwm_i : std_logic_vector(31 downto 0); + signal timer : TIMERS; + signal hdr_io : std_logic_vector(9 downto 0); + signal led_off : std_logic; + --TDC + signal hit_in_i : std_logic_vector(32 downto 1); + signal logic_analyser_i : std_logic_vector(16 downto 1); + +-- signal led_los_lock : std_logic; +-- signal los_count : unsigned(23 downto 0); + + attribute syn_keep of GSR_N : signal is true; + attribute syn_preserve of GSR_N : signal is true; + + signal link_stat_in_reg : std_logic; + + + component usrmclk + port( + USRMCLKI : in std_ulogic; + USRMCLKTS : in std_ulogic + ); + end component; + attribute syn_noprune : boolean; + attribute syn_noprune of USRMCLK : component is true; + + +begin + +--------------------------------------------------------------------------- +-- Clock & Reset Handling +--------------------------------------------------------------------------- + THE_CLOCK_RESET : entity work.clock_reset_handler + port map( + CLOCK_IN => CLOCK_CORE, + RESET_FROM_NET => med2int(0).stat_op(13), + SEND_RESET_IN => med2int(0).stat_op(15), + + BUS_RX => bustc_rx, + BUS_TX => bustc_tx, + + RESET_OUT => reset_i, + CLEAR_OUT => clear_i, + GSR_OUT => GSR_N, + + REF_CLK_OUT => clk_full, + SYS_CLK_OUT => clk_sys, + RAW_CLK_OUT => clk_full_osc, + + DEBUG_OUT => debug_clock_reset + ); + +-- process +-- begin +-- wait until rising_edge(CLOCK_CAL); +-- if debug_clock_reset(0) = '0' then +-- led_los_lock <= '0'; +-- los_count <= (others => '0'); +-- elsif los_count(23) = '0' then +-- los_count <= los_count + 1; +-- else +-- led_los_lock <= '1'; +-- end if; +-- end process; + +THE_CAL_PLL : entity work.pll_in3125_out50 + port map( + CLKI => CLOCK_CAL, + CLKOP => clk_cal + ); + +--------------------------------------------------------------------------- +-- TrbNet Uplink +--------------------------------------------------------------------------- + + THE_MEDIA_INTERFACE : entity work.med_ecp5_sfp_sync + generic map( + SERDES_NUM => 0, + --USE_RETRANSMISSION => USE_RETRANSMISSION, + IS_SYNC_SLAVE => c_YES + ) + port map( + CLK_REF_FULL => clk_full_osc, --med2int(0).clk_full, + CLK_INTERNAL_FULL => clk_full_osc, + SYSCLK => clk_sys, + RESET => reset_i, + CLEAR => clear_i, + --Internal Connection + MEDIA_MED2INT => med2int(0), + MEDIA_INT2MED => int2med(0), + + --Sync operation + RX_DLM => open, + RX_DLM_WORD => open, + TX_DLM => open, + TX_DLM_WORD => open, + + --SFP Connection + SD_PRSNT_N_IN => link_stat_in, + SD_LOS_IN => link_stat_in, + SD_TXDIS_OUT => link_stat_out, + --Control Interface + BUS_RX => bussci_rx, + BUS_TX => bussci_tx, + -- Status and control port + STAT_DEBUG => med_stat_debug(63 downto 0), + CTRL_DEBUG => open + ); + + SIG(2) <= '1' when link_stat_out = '1' else '0'; + link_stat_in <= '0';--SIG(1); + +--------------------------------------------------------------------------- +-- Endpoint +--------------------------------------------------------------------------- + THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record + generic map ( + ADDRESS_MASK => x"FFFF", + BROADCAST_BITMASK => x"FF", + REGIO_INIT_ENDPOINT_ID => x"0001", + TIMING_TRIGGER_RAW => c_YES, + --Configure data handler + DATA_INTERFACE_NUMBER => 1, + DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE, + DATA_BUFFER_WIDTH => 32, + DATA_BUFFER_FULL_THRESH => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE, + TRG_RELEASE_AFTER_DATA => c_YES, + HEADER_BUFFER_DEPTH => 9, + HEADER_BUFFER_FULL_THRESH => 2**9-16 + ) + + port map( + -- Misc + CLK => clk_sys, + RESET => reset_i, + CLK_EN => '1', + + -- Media direction port + MEDIA_MED2INT => med2int(0), + MEDIA_INT2MED => int2med(0), + + --Timing trigger in + TRG_TIMING_TRG_RECEIVED_IN => TRIG_IN, + + READOUT_RX => readout_rx, + READOUT_TX => readout_tx, + + --Slow Control Port + REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00 + REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 + BUS_RX => ctrlbus_rx, + BUS_TX => ctrlbus_tx, + BUS_MASTER_IN => bus_master_in, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + + ONEWIRE_INOUT => TEMP_LINE, + --Timing registers + TIMERS_OUT => timer + ); + +--------------------------------------------------------------------------- +-- Bus Handler +--------------------------------------------------------------------------- + + + THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record + generic map( + PORT_NUMBER => 5, + PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"a000", 4 => x"c000", others => x"0000"), + PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 8, 4 => 12, others => 0), + PORT_MASK_ENABLE => 1 + ) + port map( + CLK => clk_sys, + RESET => reset_i, + + REGIO_RX => ctrlbus_rx, + REGIO_TX => ctrlbus_tx, + + BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED + BUS_RX(1) => bussci_rx, --SCI Serdes + BUS_RX(2) => bustc_rx, --Clock switch + BUS_RX(3) => busthresh_rx, + BUS_RX(4) => bustdc_rx, + BUS_TX(0) => bustools_tx, + BUS_TX(1) => bussci_tx, + BUS_TX(2) => bustc_tx, + BUS_TX(3) => busthresh_tx, + BUS_TX(4) => bustdc_tx, + + STAT_DEBUG => open + ); + +--------------------------------------------------------------------------- +-- Control Tools +--------------------------------------------------------------------------- + THE_TOOLS : entity work.trb3sc_tools + port map( + CLK => clk_sys, + RESET => reset_i, + + --Flash & Reload + FLASH_CS => FLASH_CS, --FLASH_CS, + FLASH_CLK => FLASH_CLK, + FLASH_IN => FLASH_OUT, --FLASH_OUT, + FLASH_OUT => FLASH_IN, --FLASH_IN, + PROGRAMN => PROGRAMN, + REBOOT_IN => common_ctrl_reg(15), + --SPI + SPI_CS_OUT => spi_cs, + SPI_MOSI_OUT => spi_mosi, + SPI_MISO_IN => spi_miso, + SPI_CLK_OUT => spi_clk, + --Header + HEADER_IO => hdr_io, + ADDITIONAL_REG(0) => led_off, + --LCD + LCD_DATA_IN => (others => '0'), + --ADC + ADC_CS => ADC_CS, + ADC_MOSI => ADC_DIN, + ADC_MISO => ADC_DOUT, + ADC_CLK => ADC_SCLK, + --Trigger & Monitor + MONITOR_INPUTS => INPUT, + TRIG_GEN_INPUTS => INPUT, + TRIG_GEN_OUTPUTS => SIG(4 downto 3), + --SED + SED_ERROR_OUT => sed_error_i, + --Slowcontrol + BUS_RX => bustools_rx, + BUS_TX => bustools_tx, + --Control master for default settings + BUS_MASTER_IN => bus_master_in, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + DEBUG_OUT => debug_tools + ); + + + + FLASH_HOLD <= '1'; + FLASH_WP <= '1'; + + +--------------------------------------------------------------------------- +-- PWM / Thresh +--------------------------------------------------------------------------- +gen_pwm: if DIRICH_VERSION = 1 generate + THE_PWM_GEN : entity work.pwm_generator + port map( + CLK => clk_sys, + CLK_FAST => CLOCK_IN, + BUS_RX => busthresh_rx, + BUS_TX => busthresh_tx, + TEMP_IN => timer.temperature, + PWM => pwm_i + ); + +-- PWM <= pwm_i; +end generate; + +gen_DAC : if DIRICH_VERSION = 2 generate + MOSI_OUT <= spi_mosi(1 downto 0); + SCLK_OUT <= spi_clk(1 downto 0); + CS_OUT <= spi_cs(1 downto 0); + spi_miso(1 downto 0) <= MISO_IN; +end generate; + +--------------------------------------------------------------------------- +-- I/O +--------------------------------------------------------------------------- + + +--Debug UART + --hdr_io(8) <= TEST_LINE(1); + --TEST_LINE(2) <= hdr_io(9); + +-- TEST_LINE(8 downto 1) <= hdr_io(7 downto 0); +-- TEST_LINE(14 downto 11) <= time_counter(31 downto 28); +-- TEST_LINE(14 downto 1) <= med2int(0).stat_op(13) & clear_i & reset_i & debug_clock_reset(10 downto 6) & "00" & link_stat_out & link_stat_in_reg & debug_clock_reset(1 downto 0) ; + --& med_stat_debug(18 downto 8); +-- link_stat_in_reg <= link_stat_in when rising_edge(clk_full_osc); + +--TEST_LINE(8 downto 1) <= med_stat_debug(7 downto 0); +--TEST_LINE(8 downto 1) <= clk_sys & med_stat_debug(9) & med_stat_debug(10) & med_stat_debug(11) & clear_i & reset_i & link_stat_out & link_stat_in_reg; +-- TEST_LINE(8 downto 3) <= clear_i & reset_i & link_stat_out & link_stat_in_reg & debug_clock_reset(0) & med_stat_debug(4);-- & med_stat_debug(5) & med_stat_debug(6); + + TEST_LINE(1) <= time_counter(0); + TEST_LINE(2) <= time_counter(1); + TEST_LINE(3) <= time_counter(2); + + TEST_LINE(4) <= not med2int(0).stat_op(9) or led_off; --LED_GREEN + TEST_LINE(5) <= debug_clock_reset(0) or led_off; --LED_ORANGE + TEST_LINE(6) <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)) or led_off; --LED_RED + TEST_LINE(7) <= not med2int(0).stat_op(8) or led_off; --LED_YELLOW + TEST_LINE(8) <= reset_i; + TEST_LINE(9) <= int2med(0).ctrl_op(15); -- SEND_LINK_RESET_IN + TEST_LINE(10) <= int2med(0).dataready; -- To SFP + TEST_LINE(11) <= med2int(0).dataready; -- from SFP + + +--------------------------------------------------------------------------- +-- LED +--------------------------------------------------------------------------- + + LED_GREEN <= not med2int(0).stat_op(9) or led_off; + LED_ORANGE <= debug_clock_reset(0) or led_off; + LED_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)) or led_off; + LED_YELLOW <= not med2int(0).stat_op(8) or led_off; + + + +--------------------------------------------------------------------------- +-- Test Circuits +--------------------------------------------------------------------------- + process + begin + wait until rising_edge(clk_sys); + time_counter <= time_counter + 1; + if reset_i = '1' then + time_counter <= (others => '0'); + end if; + end process; + +------------------------------------------------------------------------------- +-- TDC +------------------------------------------------------------------------------- + + THE_TDC : entity work.TDC_record + generic map ( + CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels per module + STATUS_REG_NR => 21, -- Number of status regs + DEBUG => c_NO, + SIMULATION => c_NO) + port map ( + RESET => reset_i, + CLK_TDC => CLOCK_CORE, + CLK_READOUT => clk_sys, -- Clock for the readout + REFERENCE_TIME => TRIG_IN, -- Reference time input + HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals + HIT_CAL_IN => clk_cal, -- Hits for calibrating the TDC + -- Trigger signals from handler + BUSRDO_RX => readout_rx, + BUSRDO_TX => readout_tx(0), + -- Slow control bus + BUS_RX => bustdc_rx, + BUS_TX => bustdc_tx, + -- Dubug signals + INFO_IN => timer, + LOGIC_ANALYSER_OUT => logic_analyser_i + ); + + gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate + hit_in_i <= INPUT; + end generate; + + + +-- readout_tx(0).data_finished <= '1'; +-- readout_tx(0).data_write <= '0'; +-- readout_tx(0).busy_release <= '1'; + +end architecture; + + + diff --git a/dirich5s/nodelist_frankfurt.txt b/dirich5s/nodelist_frankfurt.txt new file mode 100644 index 0000000..dab616f --- /dev/null +++ b/dirich5s/nodelist_frankfurt.txt @@ -0,0 +1,21 @@ +// nodes file for parallel place&route + + +[jspc37] +SYSTEM = linux +CORENUM = 4 +ENV = /d/jspc29/lattice/39_settings.sh +WORKDIR = /d/jspc22/trb/git/dirich/dirich/workdir + + +[jspc57] +SYSTEM = linux +CORENUM = 4 +ENV = /d/jspc29/lattice/39_settings.sh +WORKDIR = /d/jspc22/trb/git/dirich/dirich/workdir + +[jspc29] +SYSTEM = linux +CORENUM = 3 +ENV = /d/jspc29/lattice/39_settings.sh +WORKDIR = /d/jspc22/trb/git/dirich/dirich/workdir diff --git a/dirich5s/par.p2t b/dirich5s/par.p2t new file mode 100644 index 0000000..9750eae --- /dev/null +++ b/dirich5s/par.p2t @@ -0,0 +1,70 @@ +-w +#-y +-l 5 +#-m nodelist.txt # Controlled by the compile.pl script. +#-n 2 # Controlled by the compile.pl script. +-s 10 +-t 89 +-c 2 +-e 2 +-i 10 +# -t 20 was good +#-exp parPlcInLimit=0 +#-exp parPlcInNeighborSize=1 +#General PAR Command Line Options +# -w With this option, any files generated will overwrite existing files +# (e.g., any .par, .pad files). +# -y Adds the Delay Summary Report in the .par file and creates the delay +# file (in .dly format) at the end of the par run. +# +#PAR Placement Command Line Options +# -l Specifies the effort level of the design from 1 (simplest designs) +# to 5 (most complex designs). +# -m Multi-tasking option. Controlled by the compile.pl script. +# -n Sets the number of iterations performed at the effort level +# specified by the -l option. Controlled by the compile.pl script. +# -s Save the number of best results for this run. +# -t Start placement at the specified cost table. Default is 1. +# +#PAR Routing Command Line Options +# -c Run number of cost-based cleanup passes of the router. +# -e Run number of delay-based cleanup passes of the router on +# completely-routed designs only. +# -i Run a maximum number of passes, stopping earlier only if the routing +# goes to 100 percent completion and all constraints are met. +# +#PAR Explorer Command Line Options +# parCDP Enable the congestion-driven placement (CDP) algorithm. CDP is +# compatible with all Lattice FPGA device families; however, most +# benefit has been demonstrated with benchmarks targeted to ECP5, +# LatticeECP2/M, LatticeECP3, and LatticeXP2 device families. +# parCDR Enable the congestion-driven router (CDR) algorithm. +# Congestion-driven options like parCDR and parCDP can improve +# performance given a design with multiple congestion “hotspots.” The +# Layer > Congestion option of the Design Planner Floorplan View can +# help visualize routing congestion. Large congested areas may prevent +# the options from finding a successful solution. +# CDR is compatible with all Lattice FPGA device families however most +# benefit has been demonstrated with benchmarks targeted to ECP5, +# LatticeECP2/M,LatticeECP3, and LatticeXP2 device families. +# paruseNBR NBR Router or Negotiation-based routing option. Supports all +# FPGA device families except LatticeXP and MachXO. +# When turned on, an alternate routing engine from the traditional +# Rip-up-based routing selection (RBR) is used. This involves an +# iterative routing algorithm that routes connections to achieve +# minimum delay cost. It does so by computing the demand on each +# routing resource and applying cost values per node. It will +# complete when an optimal solution is arrived at or the number of +# iterations is reached. +# parPathBased Path-based placement option. Path-based timing driven +# placement will yield better performance and more +# predictable results in many cases. +# parHold Additional hold time correction option. This option +# forces the router to automatically insert extra wires to compensate for the +# hold time violation. +# parHoldLimit This option allows you to set a limit on the number of +# hold time violations to be processed by the auto hold time correction option +# parHold. +# parPlcInLimit Cannot find in the online help +# parPlcInNeighborSize Cannot find in the online help +-exp parHold=ON:parHoldLimit=10000:parCDP=1:parCDR=1:parPathBased=OFF:paruseNBR=1 diff --git a/dirich5s/tdc_release b/dirich5s/tdc_release new file mode 120000 index 0000000..6a654d0 --- /dev/null +++ b/dirich5s/tdc_release @@ -0,0 +1 @@ +../../tdc/releases/tdc_v2.3 \ No newline at end of file diff --git a/pinout/dirich5s.lpf b/pinout/dirich5s.lpf new file mode 100644 index 0000000..18adceb --- /dev/null +++ b/pinout/dirich5s.lpf @@ -0,0 +1,145 @@ +SYSCONFIG MCCLK_FREQ=38.8 CONFIG_IOVOLTAGE=3.3 ; #BACKGROUND_RECONFIG=ON +# BANK 0 VCCIO 2.5 V; +# BANK 1 VCCIO 2.5 V; +BANK 2 VCCIO 2.5 V; +BANK 3 VCCIO 2.5 V; +BANK 6 VCCIO 2.5 V; +BANK 7 VCCIO 2.5 V; +BANK 8 VCCIO 3.3 V; + + +LOCATE COMP "INPUT[1]" SITE "E5"; +LOCATE COMP "INPUT[2]" SITE "F4"; +LOCATE COMP "INPUT[3]" SITE "E4"; +LOCATE COMP "INPUT[4]" SITE "B5"; +LOCATE COMP "INPUT[5]" SITE "A4"; +LOCATE COMP "INPUT[6]" SITE "C4"; +LOCATE COMP "INPUT[7]" SITE "A3"; +LOCATE COMP "INPUT[8]" SITE "C3"; +LOCATE COMP "INPUT[9]" SITE "A2"; +LOCATE COMP "INPUT[10]" SITE "B2"; +LOCATE COMP "INPUT[11]" SITE "C1"; +LOCATE COMP "INPUT[12]" SITE "D2"; +LOCATE COMP "INPUT[13]" SITE "F2"; +LOCATE COMP "INPUT[14]" SITE "G3"; +LOCATE COMP "INPUT[15]" SITE "H4"; +LOCATE COMP "INPUT[16]" SITE "H5"; +LOCATE COMP "INPUT[17]" SITE "T19"; +LOCATE COMP "INPUT[18]" SITE "T20"; +LOCATE COMP "INPUT[19]" SITE "U19"; +LOCATE COMP "INPUT[20]" SITE "P20"; +LOCATE COMP "INPUT[21]" SITE "R16"; +LOCATE COMP "INPUT[22]" SITE "N19"; +LOCATE COMP "INPUT[23]" SITE "P19"; +LOCATE COMP "INPUT[24]" SITE "L18"; +LOCATE COMP "INPUT[25]" SITE "N18"; +LOCATE COMP "INPUT[26]" SITE "D18"; +LOCATE COMP "INPUT[27]" SITE "E16"; +LOCATE COMP "INPUT[28]" SITE "L16"; +LOCATE COMP "INPUT[29]" SITE "N16"; +LOCATE COMP "INPUT[30]" SITE "N17"; +LOCATE COMP "INPUT[31]" SITE "U16"; +LOCATE COMP "INPUT[32]" SITE "U18"; +DEFINE PORT GROUP "INP_group" "INP*" ; +IOBUF GROUP "INP_group" IO_TYPE=LVDS DIFFRESISTOR=OFF BANK_VCCIO=2.5; + +LOCATE COMP "CLOCK_CORE" SITE "J19"; +LOCATE COMP "CLOCK_IN" SITE "L20"; +LOCATE COMP "CLOCK_CAL" SITE "J20"; + +LOCATE COMP "CLOCK_OUT" SITE "K2"; +LOCATE COMP "CLOCK_CLEAN[0]" SITE "B11"; +LOCATE COMP "CLOCK_CLEAN[1]" SITE "A10"; + +DEFINE PORT GROUP "CLK_group" "CL*" ; +IOBUF GROUP "CLK_group" IO_TYPE=LVDS DIFFRESISTOR=100 BANK_VCCIO=2.5; + +LOCATE COMP "TRIG_IN" SITE "L19"; +DEFINE PORT GROUP "TRIG_group" "TRIG*" ; +IOBUF GROUP "TRIG_group" IO_TYPE=LVDS DIFFRESISTOR=100 BANK_VCCIO=2.5; + + +LOCATE COMP "LED_GREEN" SITE "G16"; +LOCATE COMP "LED_ORANGE" SITE "H16"; +LOCATE COMP "LED_RED" SITE "H18"; +LOCATE COMP "LED_YELLOW" SITE "H17"; +DEFINE PORT GROUP "LED_group" "LED*" ; +IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 DRIVE=8 BANK_VCCIO=2.5; + +LOCATE COMP "ADC_CS" SITE "J16"; +LOCATE COMP "ADC_DIN" SITE "K17"; +LOCATE COMP "ADC_DOUT" SITE "K16"; +LOCATE COMP "ADC_SCLK" SITE "J17"; +IOBUF PORT "ADC_CS" IO_TYPE=LVCMOS25 DRIVE=8 BANK_VCCIO=2.5; +IOBUF PORT "ADC_DIN" IO_TYPE=LVCMOS25 DRIVE=8 BANK_VCCIO=2.5; +IOBUF PORT "ADC_DOUT" IO_TYPE=LVCMOS25 BANK_VCCIO=2.5; +IOBUF PORT "ADC_SCLK" IO_TYPE=LVCMOS25 DRIVE=8 BANK_VCCIO=2.5; + + + +LOCATE COMP "PROGRAMN" SITE "T1"; +IOBUF PORT "PROGRAMN" IO_TYPE=LVTTL33 DRIVE=8 BANK_VCCIO=3.3; + +LOCATE COMP "SIG[1]" SITE "N4"; +LOCATE COMP "SIG[2]" SITE "N5"; +LOCATE COMP "SIG[3]" SITE "M5"; +LOCATE COMP "SIG[4]" SITE "M4"; +# LOCATE COMP "SIG[5]" SITE "L5"; +IOBUF PORT "SIG[1]" IO_TYPE=LVCMOS25 DRIVE=8 BANK_VCCIO=2.5 PULLMODE=UP; +IOBUF PORT "SIG[2]" IO_TYPE=LVCMOS25 DRIVE=8 BANK_VCCIO=2.5 ; +IOBUF PORT "SIG[3]" IO_TYPE=LVCMOS25 DRIVE=8 BANK_VCCIO=2.5; +IOBUF PORT "SIG[4]" IO_TYPE=LVCMOS25 DRIVE=8 BANK_VCCIO=2.5; + + +LOCATE COMP "FLASH_CLK" SITE "U1"; +LOCATE COMP "FLASH_CS" SITE "R2"; +LOCATE COMP "FLASH_IN" SITE "W2"; +LOCATE COMP "FLASH_OUT" SITE "V2"; +LOCATE COMP "FLASH_HOLD" SITE "W1"; +LOCATE COMP "FLASH_WP" SITE "Y2"; +IOBUF PORT "FLASH_CLK" IO_TYPE=LVTTL33 DRIVE=8 BANK_VCCIO=3.3; +IOBUF PORT "FLASH_IN" IO_TYPE=LVTTL33 DRIVE=8 BANK_VCCIO=3.3; +IOBUF PORT "FLASH_OUT" IO_TYPE=LVTTL33 BANK_VCCIO=3.3; +IOBUF PORT "FLASH_CS" IO_TYPE=LVTTL33 DRIVE=8 BANK_VCCIO=3.3; +IOBUF PORT "FLASH_HOLD" IO_TYPE=LVTTL33 BANK_VCCIO=3.3; +IOBUF PORT "FLASH_WP" IO_TYPE=LVTTL33 BANK_VCCIO=3.3; + + +LOCATE COMP "TEMP_LINE" SITE "R1"; +IOBUF PORT "TEMP_LINE" IO_TYPE=LVTTL33 DRIVE=8 BANK_VCCIO=3.3; + + +LOCATE COMP "TEST_LINE[1]" SITE "N3"; +LOCATE COMP "TEST_LINE[2]" SITE "M3"; +LOCATE COMP "TEST_LINE[3]" SITE "L3"; +LOCATE COMP "TEST_LINE[4]" SITE "K3"; +LOCATE COMP "TEST_LINE[5]" SITE "N2"; +LOCATE COMP "TEST_LINE[6]" SITE "J3"; +LOCATE COMP "TEST_LINE[7]" SITE "P1"; +LOCATE COMP "TEST_LINE[8]" SITE "L2"; +LOCATE COMP "TEST_LINE[9]" SITE "P2"; +LOCATE COMP "TEST_LINE[10]" SITE "L1"; +LOCATE COMP "TEST_LINE[11]" SITE "P3"; +LOCATE COMP "TEST_LINE[12]" SITE "M1"; +LOCATE COMP "TEST_LINE[13]" SITE "P4"; +LOCATE COMP "TEST_LINE[14]" SITE "N1"; +DEFINE PORT GROUP "TEST_group" "TEST*" ; +IOBUF GROUP "TEST_group" IO_TYPE=LVCMOS25 DRIVE=8 BANK_VCCIO=2.5; + + +LOCATE COMP "MISO_IN[0]" SITE "E7"; #DAC1_CTRL0 +LOCATE COMP "MISO_IN[1]" SITE "A17"; #DAC2_CTRL0 +LOCATE COMP "MOSI_OUT[0]" SITE "D7"; #DAC1_CTRL1 +LOCATE COMP "MOSI_OUT[1]" SITE "A18"; #DAC2_CTRL1 +LOCATE COMP "SCLK_OUT[0]" SITE "E6"; #DAC1_CTRL2 +LOCATE COMP "SCLK_OUT[1]" SITE "B19"; #DAC2_CTRL2 +LOCATE COMP "CS_OUT[0]" SITE "D6"; #DAC1_CTRL3 +LOCATE COMP "CS_OUT[1]" SITE "B18"; #DAC2_CTRL3 +IOBUF PORT "MISO_IN[0]" IO_TYPE=LVCMOS25 PULLMODE=UP; +IOBUF PORT "MOSI_OUT[0]" IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW; +IOBUF PORT "SCLK_OUT[0]" IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW; +IOBUF PORT "CS_OUT[0]" IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW; +IOBUF PORT "MISO_IN[1]" IO_TYPE=LVCMOS25 PULLMODE=UP; +IOBUF PORT "MOSI_OUT[1]" IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW; +IOBUF PORT "SCLK_OUT[1]" IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW; +IOBUF PORT "CS_OUT[1]" IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW; -- 2.43.0