From bfbc76d5d768049052b315c435054ad9cfb78d56 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Wed, 20 May 2009 13:16:58 +0000 Subject: [PATCH] first working version --- design/mdc_addon_daq_bus_0.vhd | 15 +++++++------ design/trigger_distributor.vhd | 40 ++++++++++++++++------------------ 2 files changed, 27 insertions(+), 28 deletions(-) diff --git a/design/mdc_addon_daq_bus_0.vhd b/design/mdc_addon_daq_bus_0.vhd index f990e9f..fe1221f 100644 --- a/design/mdc_addon_daq_bus_0.vhd +++ b/design/mdc_addon_daq_bus_0.vhd @@ -388,17 +388,18 @@ begin --behavioral LVL1_TRG_NUMBER_IN => LVL1_TRG_NUMBER_IN, LVL1_TRG_CODE_IN => LVL1_TRG_CODE_IN, LVL1_TRG_INFORMATION_IN => LVL1_TRG_INFORMATION_IN, - LVL1_ERROR_PATTERN_OUT => open, - LVL1_TRG_RELEASE_OUT => open, + LVL1_ERROR_PATTERN_OUT => x"00000000", + LVL1_TRG_RELEASE_OUT => LVL1_TRG_RELEASE_OUT, + IPU_NUMBER_IN => IPU_NUMBER_IN, IPU_INFORMATION_IN => IPU_INFORMATION_IN, IPU_START_READOUT_IN => IPU_START_READOUT_IN, - IPU_DATA_OUT => open, - IPU_DATAREADY_OUT => open, - IPU_READOUT_FINISHED_OUT => open, + IPU_DATA_OUT => IPU_DATA_OUT, + IPU_DATAREADY_OUT => IPU_DATAREADY_OUT, + IPU_READOUT_FINISHED_OUT => IPU_READOUT_FINISHED_OUT, IPU_READ_IN => IPU_READ_IN, - IPU_LENGTH_OUT => open, - IPU_ERROR_PATTERN_OUT => open); + IPU_LENGTH_OUT => IPU_LENGTH_OUT, + IPU_ERROR_PATTERN_OUT => x"00000000"); ------------------------------------------------------------------------------- -- connection to output diff --git a/design/trigger_distributor.vhd b/design/trigger_distributor.vhd index ddfb1da..9283af8 100644 --- a/design/trigger_distributor.vhd +++ b/design/trigger_distributor.vhd @@ -33,7 +33,7 @@ entity trigger_distributor is A_RDO_IN : in std_logic; TRIGGER_IN : in std_logic; - TRIGGER_TYPE_IN : in std_logic; + TRIGGER_TYPE_IN : in std_logic_vector(3 downto 0); INIT_ALL_BUSES_OUT : out std_logic_vector(3 downto 0); ROC1_WRITTEN_IN : in std_logic; TOKEN_TO_TRB_OUT : out std_logic; @@ -67,7 +67,8 @@ architecture behavioral of trigger_distributor is signal up_number_of_trigger : std_logic; signal register_trigger_condition : std_logic_vector(15 downto 0); signal internal_calibration_trigger : std_logic; - signal reg_trigger_type_in, reg_trigger_in : std_logic; + signal reg_trigger_type_in : std_logic_vector(3 downto 0); + signal reg_trigger_in : std_logic; signal reg_debug_register, next_debug_register : std_logic_vector(3 downto 0); signal debug_normal_trigger_number, debug_calibration_trigger_number : std_logic_vector(7 downto 0); signal debug_token_back_number : std_logic_vector(7 downto 0); @@ -122,7 +123,6 @@ begin -- behavioral not_reset <= not(RESET); - ------------------------------------------------------------------------------- -- Register and reset for the FSM -- Signals in the sensitivity list (CLK,RESET) are important for the simulation!! @@ -192,25 +192,24 @@ begin -- behavioral case current_state is - when idle_state => + when idle_state => next_debug_register <= x"1"; - next_LED_CNT_1_OUT <= '1'; - next_LED_CNT_2_OUT <= '1'; - next_LED_ERROR_OUT <= '1'; - next_LED_GOOD_OUT <= '1'; + next_LED_CNT_1_OUT <= '1'; + next_LED_CNT_2_OUT <= '1'; + next_LED_ERROR_OUT <= '1'; + next_LED_GOOD_OUT <= '1'; next_init_all_buses <= (others => '0'); next_token_to_trb <= '0'; up_number_of_trigger <= '0'; reset_calibration_counter <= '0'; - -- if pulse_begin_run_trigger = '1' then - if reg_trigger_in = '1' then - -- next_state <= begrun_trigger_state; --- elsif ( reg_trigger_in = '1') then --- next_state <= normal_trigger_state; + if pulse_begin_run_trigger = '1' then + next_state <= begrun_trigger_state; + elsif reg_trigger_in = '1' then + next_state <= normal_trigger_state; -- if (internal_calibration_trigger = '1') then -- next_state <= calibration_state; -- else - next_state <= normal_trigger_state; + next_state <= normal_trigger_state; -- end if; else next_state <= idle_state; @@ -258,9 +257,8 @@ begin -- behavioral next_token_to_trb <= '1'; up_number_of_trigger <= '0'; reset_calibration_counter <= '0'; - --next_state <= normal_trigger_state; - next_state <= idle_state; - + -- next_state <= normal_trigger_state; + next_state <= idle_state; ------------------------------------------------------------------------------- -- BEGRUN TRIGGER. -- After FPGA is loaded automatically done. @@ -279,7 +277,7 @@ begin -- behavioral when wait_roc1_written => next_debug_register <= x"6"; - next_LED_CNT_1_OUT <= '0'; + next_LED_CNT_1_OUT <= '1'; next_LED_CNT_2_OUT <= '1'; next_LED_ERROR_OUT <= '0'; next_LED_GOOD_OUT <= '1'; @@ -305,8 +303,8 @@ begin -- behavioral up_number_of_trigger <= '0'; reset_calibration_counter <= '0'; if counter_wait_after_roc1 = WAIT_AFTER_ROC1_IS_LOADED then - -- next_state <= normal_trigger_state; - next_state <= idle_state; + --next_state <= normal_trigger_state; + next_state <= idle_state; else next_state <= roc1_written_state; end if; @@ -395,7 +393,7 @@ begin -- behavioral begin if (rising_edge(CLK)) then if RESET = '1' then - reg_trigger_type_in <= '0'; + reg_trigger_type_in <= (others => '0'); reg_trigger_in <= '0'; else reg_trigger_type_in <= TRIGGER_TYPE_IN; -- 2.43.0