From c09446f649b4a2b3063f5c2d01587ba75242e1f8 Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Wed, 17 Aug 2022 23:40:13 +0200 Subject: [PATCH] better AN --- gbe_trb/base/inserter.vhd | 4 +- gbe_trb/base/parser.vhd | 204 +++++++++++++--------------- gbe_trb/base/remover.vhd | 4 +- gbe_trb_ecp3/media/gbe_med_fifo.vhd | 2 +- 4 files changed, 102 insertions(+), 112 deletions(-) diff --git a/gbe_trb/base/inserter.vhd b/gbe_trb/base/inserter.vhd index 27d1af1..f204a03 100644 --- a/gbe_trb/base/inserter.vhd +++ b/gbe_trb/base/inserter.vhd @@ -103,8 +103,8 @@ begin end process THE_SYNC_PROC; -- we have an /I/ candidate for dropping (in the input and in the first stage) - idle_x <= '1' when ((delay_q(7 downto 0) = x"bc") and (delay_q(8) = '1') and (delay_q(9) = '0') and - (PHY_D_IN = x"50") and (PHY_K_IN = '0') and (PHY_CD_IN = '0')) + idle_x <= '1' when ((delay_q(7 downto 0) = x"bc") and (delay_q(8) = '1') and (delay_q(9) = '0') and + ((PHY_D_IN = x"50") or (PHY_D_IN = x"c5")) and (PHY_K_IN = '0') and (PHY_CD_IN = '0')) else '0'; -- insert counter diff --git a/gbe_trb/base/parser.vhd b/gbe_trb/base/parser.vhd index 4db66cf..5f993c5 100644 --- a/gbe_trb/base/parser.vhd +++ b/gbe_trb/base/parser.vhd @@ -1,153 +1,143 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; - -entity parser is - port( - CLK : in std_logic; - RESET : in std_logic; - -- - PHY_D_IN : in std_logic_vector(7 downto 0); - PHY_K_IN : in std_logic; +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; + +entity parser is + port( + CLK : in std_logic; + RESET : in std_logic; + -- + PHY_D_IN : in std_logic_vector(7 downto 0); + PHY_K_IN : in std_logic; -- - UNKNOWN_OUT : out std_logic; - IDLE_OUT : out std_logic; - CFG_OUT : out std_logic - ); -end entity parser; - -architecture parser_arch of parser is - --- state machine signals - type state_t is (ST0, ST1, IDLE0, IDLE1, CFG0, CFG1, CFG2, CFG3, UK0, UK1); - signal STATE, NEXT_STATE : state_t; - + UNKNOWN_OUT : out std_logic; + IDLE_OUT : out std_logic; + CFG_OUT : out std_logic + ); +end entity parser; + +architecture parser_arch of parser is + +-- state machine signals + type state_t is (ST0, ST1, IDLE0, IDLE1, CFG0, CFG1, CFG2, CFG3, UK0, UK1); + signal STATE, NEXT_STATE : state_t; + -- Signals - signal phy_d_q : std_logic_vector(7 downto 0); - signal phy_d_qq : std_logic_vector(7 downto 0); - signal phy_k_q : std_logic; - signal phy_k_qq : std_logic; + signal phy_d_q : std_logic_vector(7 downto 0); + signal phy_d_qq : std_logic_vector(7 downto 0); + signal phy_k_q : std_logic; + signal phy_k_qq : std_logic; signal idle_x : std_logic; signal cfg_x : std_logic; signal unknown_x : std_logic; - -begin + +begin THE_SYNC_PROC: process( CLK ) begin if( rising_edge(CLK) ) then phy_d_qq <= phy_d_q; phy_d_q <= PHY_D_IN; - phy_k_qq <= phy_k_q; - phy_k_q <= PHY_K_IN; + phy_k_qq <= phy_k_q; + phy_k_q <= PHY_K_IN; end if; end process THE_SYNC_PROC; - - ----------------------------------------------------------- - -- statemachine: clocked process - ----------------------------------------------------------- - THE_FSM: process( CLK ) - begin - if( rising_edge(CLK) ) then - if( RESET = '1' ) then - STATE <= ST0; - else - STATE <= NEXT_STATE; - end if; - end if; - end process THE_FSM; - - THE_STATE_TRANSITIONS: process( STATE, phy_d_qq, phy_d_q, phy_k_qq, phy_k_q ) - begin + + ----------------------------------------------------------- + -- statemachine: clocked process + ----------------------------------------------------------- + THE_FSM: process( CLK ) + begin + if( rising_edge(CLK) ) then + if( RESET = '1' ) then + STATE <= ST0; + else + STATE <= NEXT_STATE; + end if; + end if; + end process THE_FSM; + + THE_STATE_TRANSITIONS: process( STATE, phy_d_qq, phy_d_q, phy_k_qq, phy_k_q ) + begin idle_x <= '0'; cfg_x <= '0'; unknown_x <= '0'; - - case STATE is + + case STATE is when ST0 => - if ( (phy_d_qq = x"bc") and (phy_k_qq = '1') and (phy_d_q = x"50") and (phy_k_q = '0') ) then + if ( (phy_d_qq = x"bc") and (phy_k_qq = '1') and ((phy_d_q = x"50") or (phy_d_q = x"c5")) and (phy_k_q = '0') ) then NEXT_STATE <= IDLE0; - elsif( (phy_d_qq = x"bc") and (phy_k_qq = '1') and (phy_d_q = x"b5") and (phy_k_q = '0') ) then - NEXT_STATE <= CFG0; - elsif( (phy_d_qq = x"bc") and (phy_k_qq = '1') and (phy_d_q = x"42") and (phy_k_q = '0') ) then - NEXT_STATE <= CFG0; + elsif( (phy_d_qq = x"bc") and (phy_k_qq = '1') and ((phy_d_q = x"b5") or (phy_d_q = x"42")) and (phy_k_q = '0') ) then + NEXT_STATE <= CFG0; else NEXT_STATE <= ST1; end if; - when ST1 => - if ( (phy_d_qq = x"bc") and (phy_k_qq = '1') and (phy_d_q = x"50") and (phy_k_q = '0') ) then - NEXT_STATE <= IDLE0; - elsif( (phy_d_qq = x"bc") and (phy_k_qq = '1') and (phy_d_q = x"b5") and (phy_k_q = '0') ) then - NEXT_STATE <= CFG0; - elsif( (phy_d_qq = x"bc") and (phy_k_qq = '1') and (phy_d_q = x"42") and (phy_k_q = '0') ) then - NEXT_STATE <= CFG0; - else - NEXT_STATE <= ST0; - end if; + when ST1 => + if ( (phy_d_qq = x"bc") and (phy_k_qq = '1') and ((phy_d_q = x"50") or (phy_d_q = x"c5")) and (phy_k_q = '0') ) then + NEXT_STATE <= IDLE0; + elsif( (phy_d_qq = x"bc") and (phy_k_qq = '1') and ((phy_d_q = x"b5") or (phy_d_q = x"42")) and (phy_k_q = '0') ) then + NEXT_STATE <= CFG0; + else + NEXT_STATE <= ST0; + end if; when IDLE0 => idle_x <= '1'; NEXT_STATE <= IDLE1; when IDLE1 => - idle_x <= '1'; - if ( (phy_d_qq = x"bc") and (phy_k_qq = '1') and (phy_d_q = x"50") and (phy_k_q = '0') ) then - NEXT_STATE <= IDLE0; - elsif( (phy_d_qq = x"bc") and (phy_k_qq = '1') and (phy_d_q = x"b5") and (phy_k_q = '0') ) then - NEXT_STATE <= CFG0; - elsif( (phy_d_qq = x"bc") and (phy_k_qq = '1') and (phy_d_q = x"42") and (phy_k_q = '0') ) then - NEXT_STATE <= CFG0; - else - NEXT_STATE <= UK0; - end if; + idle_x <= '1'; + if ( (phy_d_qq = x"bc") and (phy_k_qq = '1') and ((phy_d_q = x"50") or (phy_d_q = x"c5")) and (phy_k_q = '0') ) then + NEXT_STATE <= IDLE0; + elsif( (phy_d_qq = x"bc") and (phy_k_qq = '1') and ((phy_d_q = x"b5") or (phy_d_q = x"42")) and (phy_k_q = '0') ) then + NEXT_STATE <= CFG0; + else + NEXT_STATE <= UK0; + end if; when CFG0 => cfg_x <= '1'; NEXT_STATE <= CFG1; when CFG1 => - cfg_x <= '1'; - NEXT_STATE <= CFG2; + cfg_x <= '1'; + NEXT_STATE <= CFG2; when CFG2 => - cfg_x <= '1'; - NEXT_STATE <= CFG3; + cfg_x <= '1'; + NEXT_STATE <= CFG3; when CFG3 => - cfg_x <= '1'; - if ( (phy_d_qq = x"bc") and (phy_k_qq = '1') and (phy_d_q = x"50") and (phy_k_q = '0') ) then - NEXT_STATE <= IDLE0; - elsif( (phy_d_qq = x"bc") and (phy_k_qq = '1') and (phy_d_q = x"b5") and (phy_k_q = '0') ) then - NEXT_STATE <= CFG0; - elsif( (phy_d_qq = x"bc") and (phy_k_qq = '1') and (phy_d_q = x"42") and (phy_k_q = '0') ) then - NEXT_STATE <= CFG0; - else - NEXT_STATE <= UK0; - end if; + cfg_x <= '1'; + if ( (phy_d_qq = x"bc") and (phy_k_qq = '1') and ((phy_d_q = x"50") or (phy_d_q = x"c5")) and (phy_k_q = '0') ) then + NEXT_STATE <= IDLE0; + elsif( (phy_d_qq = x"bc") and (phy_k_qq = '1') and ((phy_d_q = x"b5") or (phy_d_q = x"42")) and (phy_k_q = '0') ) then + NEXT_STATE <= CFG0; + else + NEXT_STATE <= UK0; + end if; when UK0 => unknown_x <= '1'; NEXT_STATE <= UK1; - when UK1 => - unknown_x <= '1'; - if ( (phy_d_qq = x"bc") and (phy_k_qq = '1') and (phy_d_q = x"50") and (phy_k_q = '0') ) then - NEXT_STATE <= IDLE0; - elsif( (phy_d_qq = x"bc") and (phy_k_qq = '1') and (phy_d_q = x"b5") and (phy_k_q = '0') ) then - NEXT_STATE <= CFG0; - elsif( (phy_d_qq = x"bc") and (phy_k_qq = '1') and (phy_d_q = x"42") and (phy_k_q = '0') ) then - NEXT_STATE <= CFG0; - else - NEXT_STATE <= UK0; - end if; - - when others => - NEXT_STATE <= ST0; + when UK1 => + unknown_x <= '1'; + if ( (phy_d_qq = x"bc") and (phy_k_qq = '1') and ((phy_d_q = x"50") or (phy_d_q = x"c5")) and (phy_k_q = '0') ) then + NEXT_STATE <= IDLE0; + elsif( (phy_d_qq = x"bc") and (phy_k_qq = '1') and ((phy_d_q = x"b5") or (phy_d_q = x"42")) and (phy_k_q = '0') ) then + NEXT_STATE <= CFG0; + else + NEXT_STATE <= UK0; + end if; + + when others => + NEXT_STATE <= ST0; end case; @@ -156,5 +146,5 @@ begin IDLE_OUT <= idle_x when rising_edge(CLK); CFG_OUT <= cfg_x when rising_edge(CLK); UNKNOWN_OUT <= unknown_x when rising_edge(CLK); - -end architecture; + +end architecture; diff --git a/gbe_trb/base/remover.vhd b/gbe_trb/base/remover.vhd index 48a4aac..0e1cfaf 100644 --- a/gbe_trb/base/remover.vhd +++ b/gbe_trb/base/remover.vhd @@ -167,14 +167,14 @@ begin end if; when IDLE => - if( (phy_k_fifo = '1') and (phy_d_fifo = x"bc") and (fifofull = '0')) then + if( (phy_k_fifo = '1') and (phy_d_fifo = x"bc") and (fifofull = '0') ) then NEXT_STATE <= ONE; else NEXT_STATE <= IDLE; end if; when ONE => - if( (phy_k_fifo = '0') and (phy_d_fifo = x"50")) then + if( (phy_k_fifo = '0') and ((phy_d_fifo = x"50") or (phy_d_fifo = x"c5")) ) then NEXT_STATE <= TWO; replace_k_x <= '1'; else diff --git a/gbe_trb_ecp3/media/gbe_med_fifo.vhd b/gbe_trb_ecp3/media/gbe_med_fifo.vhd index 51b38fa..2a76be6 100644 --- a/gbe_trb_ecp3/media/gbe_med_fifo.vhd +++ b/gbe_trb_ecp3/media/gbe_med_fifo.vhd @@ -554,7 +554,7 @@ begin sd_rx_data_dst((i + 1) * 8 - 1 downto i * 8) <= sd_rx_data_src((i + 1) * 8 - 1 downto i * 8); sd_rx_kcntl_dst(i) <= sd_rx_kcntl_src(i); DLM_DATA_OUT((i + 1) * 8 - 1 downto i * 8) <= (others => '0'); - DLM_FOUND_OUT(i) <= 'i'; + DLM_FOUND_OUT(i) <= '0'; end generate NO_TRUDY_AND_EVE; ------------------------------------------------------------ ------------------------------------------------------------ -- 2.43.0