From c12503ae132584b46c20ce4b86167ed9fa0a4c6e Mon Sep 17 00:00:00 2001
From: hadeshyp <hadeshyp>
Date: Fri, 24 Oct 2008 16:25:33 +0000
Subject: [PATCH] *** empty log message ***

---
 trb_net16_med_ecp_sfp.vhd | 56 ++++++++++++++++++++++++++-------------
 1 file changed, 37 insertions(+), 19 deletions(-)

diff --git a/trb_net16_med_ecp_sfp.vhd b/trb_net16_med_ecp_sfp.vhd
index 4d8f387..12195e1 100644
--- a/trb_net16_med_ecp_sfp.vhd
+++ b/trb_net16_med_ecp_sfp.vhd
@@ -151,8 +151,11 @@ architecture med_ecp_sfp of trb_net16_med_ecp_sfp is
   signal rx_counter            : std_logic_vector(c_NUM_WIDTH-1 downto 0);
   signal reset_interface       : std_logic;
   signal buf_MED_DATAREADY_OUT : std_logic;
+  signal buf_MED_DATA_OUT      : std_logic_vector(c_DATA_WIDTH-1 downto 0);
+  signal buf_MED_PACKET_NUM_OUT: std_logic_vector(c_NUM_WIDTH-1 downto 0);
   signal swap_bytes            : std_logic;
   signal last_rx               : std_logic_vector(8 downto 0);
+  signal last_fifo_rx_empty    : std_logic;
   --tx path
   signal last_fifo_tx_empty : std_logic;
   --link status
@@ -241,31 +244,40 @@ begin
   process(ff_rxhalfclk)
     begin
       if rising_edge(ff_rxhalfclk) then
+        last_rx <= rx_k(1) & rx_data(15 downto 8);
         if swap_bytes = '0' then
-          fifo_rx_din   <= rx_k & rx_data;
-          fifo_rx_wr_en <= not or_all(rx_k) and rx_allow;
+          fifo_rx_din   <= rx_k(1) & rx_k(0) & rx_data(15 downto 8) & rx_data(7 downto 0);
+          fifo_rx_wr_en <= not rx_k(0) and rx_allow;
         else
-          last_rx <= rx_k(1) & rx_data(15 downto 8);
-          fifo_rx_din <= rx_k(1) & last_rx(8) & rx_data(7 downto 0) & last_rx(7 downto 0);
-          fifo_rx_wr_en <= not last_rx(8) and not rx_k(1) and rx_allow;
+          fifo_rx_din   <= rx_k(0) & last_rx(8) & rx_data(7 downto 0) & last_rx(7 downto 0);
+          fifo_rx_wr_en <= not last_rx(8) and rx_allow;
         end if;
       end if;
     end process;
 
-  MED_DATA_OUT          <= fifo_rx_dout(15 downto 0);
-  buf_MED_DATAREADY_OUT <= not fifo_rx_dout(17) and not fifo_rx_dout(16);
-  MED_PACKET_NUM_OUT    <= rx_counter;
+  buf_MED_DATA_OUT          <= fifo_rx_dout(15 downto 0);
+  buf_MED_DATAREADY_OUT <= not fifo_rx_dout(17) and not fifo_rx_dout(16) and not last_fifo_rx_empty;
+  buf_MED_PACKET_NUM_OUT    <= rx_counter;
   MED_READ_OUT          <= tx_allow;
-  MED_DATAREADY_OUT     <= buf_MED_DATAREADY_OUT;
+
+  process(CLK)
+    begin
+      if rising_edge(CLK) then
+         MED_DATAREADY_OUT     <= buf_MED_DATAREADY_OUT;
+         MED_DATA_OUT          <= buf_MED_DATA_OUT;
+         MED_PACKET_NUM_OUT    <= buf_MED_PACKET_NUM_OUT;
+      end if;
+    end process;
 
 --rx packet counter
 ---------------------
-  rx_counter_p : process(CLK)
+  rx_packets : process(CLK)
     begin
       if rising_edge(CLK) then
         if RESET = '1' or reset_interface = '1' then
           rx_counter <= c_H0;
         else
+          last_fifo_rx_empty <= fifo_rx_empty;
           if buf_MED_DATAREADY_OUT = '1' then
             if rx_counter = c_max_word_number then
               rx_counter <= (others => '0');
@@ -298,7 +310,7 @@ begin
   fifo_tx_reset <= reset or not tx_allow;
   fifo_tx_din   <= MED_PACKET_NUM_IN(2) & MED_PACKET_NUM_IN(0) & MED_DATA_IN;
   fifo_tx_wr_en <= MED_DATAREADY_IN and tx_allow;
-  fifo_tx_rd_en <= '1';
+  fifo_tx_rd_en <= tx_allow;
 
   make_serdes_input : process(ff_txhalfclk)
     begin
@@ -318,12 +330,14 @@ begin
 --link start-up state machine
 ----------------------
 
- medium_states : process(ff_rxhalfclk)  --correct clock?
+ medium_states : process(ff_rxhalfclk)
     begin
       if rising_edge(ff_rxhalfclk) then
         if RESET = '0' then
           counter <= counter + 1;
           swap_bytes <= '0';
+          tx_allow <= '0';
+          rx_allow <= '0';
         end if;
         swap_bytes <= swap_bytes;
         case state is
@@ -341,19 +355,21 @@ begin
               state   <= waitrxallow;
             end if;
             MED_ERROR_OUT <= ERROR_NC;
-          when waitrxallow =>  --care for byte alignment!
+          when waitrxallow =>
             if counter(28) = '1' then
               counter  <= (others => '0');
               rx_allow <= '1';
               state    <= waittxallow;
             end if;
+            if counter(27) = '1' then
+              if rx_k = "10" then
+                swap_bytes <= '1';
+              elsif rx_k = "01" then
+                swap_bytes <= '0';
+              end if;
+            end if;
             MED_ERROR_OUT <= ERROR_WAIT;
           when waittxallow =>
-            if rx_k = "10" then
-              swap_bytes <= '1';
-            elsif rx_k = "01" then
-              swap_bytes <= '0';
-            end if;
             if counter(28) = '1' then
               tx_allow <= '1';
               state <= working;
@@ -363,6 +379,7 @@ begin
             MED_ERROR_OUT <= ERROR_OK;
         end case;
         if (link_error(6) = '1' or link_error(7) = '1') and ffc_lane_rx_rst_ch2 = '0' then
+          counter  <= (others => '0');
           rx_allow <= '0';
           tx_allow <= '0';
           state <= waitrxallow;
@@ -394,6 +411,7 @@ begin
   STAT_DEBUG(20)           <= link_ok(0);
   STAT_DEBUG(38 downto 21) <= fifo_rx_din;
   STAT_DEBUG(39)           <= swap_bytes;
-  STAT_DEBUG(63 downto 40) <= (others => '0');
+  STAT_DEBUG(40)           <= fifo_rx_wr_en;
+  STAT_DEBUG(63 downto 41) <= (others => '0');
 
 end architecture;
\ No newline at end of file
-- 
2.43.0