From c182883fac172f1245c96c4000234ee360774ae1 Mon Sep 17 00:00:00 2001 From: Adrian Weber Date: Wed, 10 Jan 2018 14:03:10 +0100 Subject: [PATCH] new subsection FPGA based calibration --- trb3/Trb3scFpgaBasedTdcCalibration.tex | 31 ++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 trb3/Trb3scFpgaBasedTdcCalibration.tex diff --git a/trb3/Trb3scFpgaBasedTdcCalibration.tex b/trb3/Trb3scFpgaBasedTdcCalibration.tex new file mode 100644 index 0000000..8e05f5d --- /dev/null +++ b/trb3/Trb3scFpgaBasedTdcCalibration.tex @@ -0,0 +1,31 @@ +In order to calibrate the TDC data directly on a TrbSc, a FPGA based online TDC calibration was implemented. If this method is part of the FPGA design, the online calibration method can be activated (odd values) or deactivated (even values) with register \texttt{0xE000} of the TrbSc. If the online calibration is deactivated, the TrbSc can be used like a normal TrbSc.\\ +The calibration method is the linear calibration. Each TDC channel is calibrated individually. The TDC data is used to generate a new linear calibration and it is directly calibrated.\\ +The output format of the FPGA based calibration is slightly different to the software based calibration: +The fineTime values are now fixed between 0 and 1000. 0 equals a fine time of 0 ns, 1000 equals 5ns. In order to get the fineTime in ns, the output has to be multiplied by 5. With Go4 it is possible to multiply by 5 if you set an additional linear calibration between 0 and 1000.\\ + +In case that a TDC data value is out of the calibration range, it is put to the value 1010 (value is too small). If it is greater than the range, the value is put to 1015. This has to be taken into account for further data processing. If Go4 is used, the values greater 1000 are set to 1000. This leads to incorrect data. This has to be changed directly in the go4 source code until now (10. January 2018). + +The amount of TDC data that is necessary (statistics) to create a new calibration can be set by hand (Register \texttt{0xE001}). The value is set to 100.000 by default. The value has a lower limit of 10.000. It is not possible to go below this value.\\ +If the FPGA is started, the first 100.000 TDC data values have no calibration. The calibration is done with standard values. There is the possibility to load values to the Flash memory. If the flash is loaded with values, they are loaded at startup and directly used for the first 100.000 calibrations of a channel.\\ + +The flash address for this feature is starting at \texttt{0xE007} for channel 0. For channel 3 it is \texttt{0xE00A} and so on. The data written to this address consists of the lower fineTime limit and the upper fineTime limit. The lower limit is the smallest fineTime bin that is greater than 0. The upper limit is the greatest fineTime bin that is not equal 0. +Bit 0-9 is filled with the lower value. Bit 10-19 is filled with the upper value.\\ +The data is written to the flash by \textit{flash\_settings.pl} from \textit{daqtools/tools}.\\ + +Currently (10. january 2018) only a 11 channel TDC design for the TrbSc is available and tested. More channels could not be tested due to missing manpower for TDC development. + +\begin{table} +\centering +\begin{tabular}{|l|l|} +\hline + \textbf{Register} & \textbf{Description} \\ \hline + + \texttt{0xE000} & activate (odd values) or deactivate\\ + & (even values) the calibration\\ \hline + \texttt{0xE001} & amount of statistics of each channel\\ \hline + \texttt{0xE007} & default calibration values of channel 0 \\ \hline + \texttt{0xE008} & default calibration values of channel 1 \\ \hline + \texttt{0xE009} & default calibration values of channel 2 \\ \hline + \texttt{0xEXXX} & default calibration values of channel XXX \\ \hline +\end{tabular} +\end{table} -- 2.43.0